sim/v850/ChangeLog

   1 Thu Aug 29 13:53:29 1996  Jeffrey A Law  (law@cygnus.com)
   2
   3         * v850_sim.h: The V850 doesn't have split I&D spaces.  Change
   4         accordingly.  Remove many unused definitions.
   5         * interp.c: The V850 doesn't have split I&D spaces.  Change
   6         accordingly.
   7         (get_longlong, get_longword, get_word): Deleted.
   8         (write_longlong, write_longword, write_word): Deleted.
   9         (get_operands): Deleted.
  10         (get_byte, get_half, get_word): New functions.
  11         (put_byte, put_half, put_word): New functions.
  12         * simops.c: Remove unused functions.  Rough cut at
  13         "ld.b", "ld.h", "ld.w", "st.b", "st.h", "st.w" insns.
  14
  15         * v850_sim.h (struct _state): Remove "psw" field.  Add
  16         "sregs" field.
  17         (PSW): Remove bogus definition.
  18         * simops.c: Change condition code handling to use the psw
  19         register within the sregs array.  Handle "ldsr" and "stsr".
  20
  21         * simops.c: Handle "satadd", "satsub", "satsubi", "satsubr".
  22
  23         * interp.c (do_format_5): Get operands correctly and
  24         call the target function.
  25         (sim_resume): Don't do a PC update for format 5 instructions.
  26         * simops.c: Handle "jarl" and "jmp" instructions.
  27
  28         * simops.c: Fix minor typos.  Handle "cmp", "setf", "tst"
  29         "di", and "ei" instructions correctly.
  30
  31         * interp.c (do_format_3): Get operands correctly and call
  32         the target function.
  33         * simops.c: Handle bCC instructions.
  34
  35         * simops.c: Add condition code handling to shift insns.
  36         Fix minor typos in condition code handling for other insns.
  37
  38         * Makefile.in: Fix typo.
  39         * simops.c: Add condition code handling to "sub" "subr" and
  40         "divh" instructions.
  41
  42         * interp.c (hash): Update to be more accurate.
  43         (lookup_hash): Call hash rather than computing the hash
  44         code here.
  45         (do_format_1_2): Handle format 1 and format 2 instructions.
  46         Get operands correctly and call the target function.
  47         (do_format_6): Get operands correctly and call the target
  48         function.
  49         (do_formats_9_10): Rough cut so shift ops will work.
  50         (sim_resume): Tweak to deal with format 1 and format 2
  51         handling in a single funtion.  Don't update the PC
  52         for format 3 insns.  Fix typos.
  53         * simops.c: Slightly reorganize.  Add condition code handling
  54         to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
  55         and "not" instructions.
  56         * v850_sim.h (reg_t): Registers are 32bits.
  57         (_state): The V850 has 32 general registers.  Add a 32bit
  58         psw and pc register too.  Add accessor macros
  59
  60         * Makefile.in, interp.c, v850_sim.h: Bring over endianness
  61         changes from the d10v simulator.
  62
  63         * simops.c: Add shift support.
  64
  65         * simops.c: Add multiply & divide support.  Abort for system
  66         instructions.
  67
  68         * simops.c: Add logicals, mov, movhi, movea, add, addi, sub
  69         and subr.  No condition codes yet.
  70
  71 Wed Aug 28 13:53:22 1996  Jeffrey A Law  (law@cygnus.com)
  72
  73         * ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,
  74         gencode.c, interp.c, simops.c: Created.
  75