sim/v850/sim-main.h

   1 #define WITH_CORE
   2 #define WITH_MODULO_MEMORY 1
   3 #define WITH_WATCHPOINTS 1
   4 #define WITH_TARGET_WORD_MSB 31
   5
   6 #include "sim-basics.h"
   7
   8 #include <signal.h>
   9 typedef address_word sim_cia;
  10
  11
  12 /* This simulator doesn't cache state */
  13 #define SIM_ENGINE_HALT_HOOK(sd,last_cpu,cia) while (0)
  14 #define SIM_ENGINE_RESTART_HOOK(sd,last_cpu,cia) while (0)
  15
  16 /* Get the number of instructions.  FIXME: must be a more elegant way
  17    of doing this.  */
  18 #include "itable.h"
  19 #define MAX_INSNS (nr_itable_entries)
  20 #define INSN_NAME(i) itable[(i)].name
  21
  22 #include "sim-base.h"
  23
  24 typedef signed8 int8;
  25 typedef unsigned8 uint8;
  26 typedef signed16 int16;
  27 typedef unsigned16 uint16;
  28 typedef signed32 int32;
  29 typedef unsigned32 uint32;
  30 typedef unsigned32 reg_t;
  31
  32
  33 /* The current state of the processor; registers, memory, etc.  */
  34
  35 typedef struct _v850_regs {
  36   reg_t regs[32];               /* general-purpose registers */
  37   reg_t sregs[32];              /* system registers, including psw */
  38   reg_t pc;
  39   int dummy_mem;                /* where invalid accesses go */
  40   int pending_nmi;
  41 } v850_regs;
  42
  43 struct _sim_cpu
  44 {
  45   /* ... simulator specific members ... */
  46   v850_regs reg;
  47   /* ... base type ... */
  48   sim_cpu_base base;
  49 };
  50
  51 #define CPU_CIA(CPU) ((CPU)->reg.pc)
  52
  53 struct sim_state {
  54   sim_cpu cpu[MAX_NR_PROCESSORS];
  55 #if (WITH_SMP)
  56 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
  57 #else
  58 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
  59 #endif
  60 #if 0
  61   SIM_ADDR rom_size;
  62   SIM_ADDR low_end;
  63   SIM_ADDR high_start;
  64   SIM_ADDR high_base;
  65   void *mem;
  66 #endif
  67   sim_state_base base;
  68 };
  69
  70 /* For compatibility, until all functions converted to passing
  71    SIM_DESC as an argument */
  72 extern SIM_DESC simulator;
  73
  74
  75 #define V850_ROM_SIZE 0x8000
  76 #define V850_LOW_END 0x200000
  77 #define V850_HIGH_START 0xffe000
  78
  79
  80 #define SIG_V850_EXIT   -1      /* indication of a normal exit */
  81
  82 extern uint32 OP[4];
  83
  84 /* Because we are still using the old semantic table, provide compat
  85    macro's that store the instruction where the old simops expects
  86    it. */
  87
  88 #if 0
  89 OP[0] = inst & 0x1f;
  90 OP[1] = (inst >> 11) & 0x1f;
  91 OP[2] = (inst >> 16) & 0xffff;
  92 OP[3] = inst;
  93 #endif
  94
  95 #define COMPAT_1(CALL) \
  96 PC = cia; \
  97 OP[0] = instruction_0 & 0x1f; \
  98 OP[1] = (instruction_0 >> 11) & 0x1f; \
  99 OP[2] = 0; \
 100 OP[3] = instruction_0 ; \
 101 PC += (CALL); \
 102 nia = PC
 103
 104 #define COMPAT_2(CALL) \
 105 PC = cia; \
 106 OP[0] = instruction_0 & 0x1f; \
 107 OP[1] = (instruction_0 >> 11) & 0x1f; \
 108 OP[2] = instruction_1; \
 109 OP[3] = (instruction_1 << 16) | instruction_0; \
 110 PC += (CALL); \
 111 nia = PC
 112
 113
 114 #if 0
 115 extern struct simops Simops[];
 116 #endif
 117
 118 #define State    (STATE_CPU (simulator, 0)->reg)
 119 #define PC      (State.pc)
 120 #define SP      (State.regs[3])
 121 #define EP      (State.regs[30])
 122
 123 #define EIPC  (State.sregs[0])
 124 #define EIPSW (State.sregs[1])
 125 #define FEPC  (State.sregs[2])
 126 #define FEPSW (State.sregs[3])
 127 #define ECR   (State.sregs[4])
 128 #define PSW   (State.sregs[5])
 129 /* start-sanitize-v850e */
 130 #define CTPC  (State.sregs[16])
 131 #define CTPSW (State.sregs[17])
 132 /* end-sanitize-v850e */
 133 #define DBPC  (State.sregs[18])
 134 #define DBPSW (State.sregs[19])
 135 /* start-sanitize-v850e */
 136 #define CTBP  (State.sregs[20])
 137 /* end-sanitize-v850e */
 138
 139 #define PSW_NP 0x80
 140 #define PSW_EP 0x40
 141 #define PSW_ID 0x20
 142 #define PSW_SAT 0x10
 143 #define PSW_CY 0x8
 144 #define PSW_OV 0x4
 145 #define PSW_S 0x2
 146 #define PSW_Z 0x1
 147
 148 #define SEXT3(x)        ((((x)&0x7)^(~0x3))+0x4)
 149
 150 /* sign-extend a 4-bit number */
 151 #define SEXT4(x)        ((((x)&0xf)^(~0x7))+0x8)
 152
 153 /* sign-extend a 5-bit number */
 154 #define SEXT5(x)        ((((x)&0x1f)^(~0xf))+0x10)
 155
 156 /* sign-extend a 9-bit number */
 157 #define SEXT9(x)        ((((x)&0x1ff)^(~0xff))+0x100)
 158
 159 /* sign-extend a 22-bit number */
 160 #define SEXT22(x)       ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
 161
 162 /* sign extend a 40 bit number */
 163 #define SEXT40(x)       ((((x) & UNSIGNED64 (0xffffffffff)) \
 164                           ^ (~UNSIGNED64 (0x7fffffffff))) \
 165                          + UNSIGNED64 (0x8000000000))
 166
 167 /* sign extend a 44 bit number */
 168 #define SEXT44(x)       ((((x) & UNSIGNED64 (0xfffffffffff)) \
 169                           ^ (~ UNSIGNED64 (0x7ffffffffff))) \
 170                          + UNSIGNED64 (0x80000000000))
 171
 172 /* sign extend a 60 bit number */
 173 #define SEXT60(x)       ((((x) & UNSIGNED64 (0xfffffffffffffff)) \
 174                           ^ (~ UNSIGNED64 (0x7ffffffffffffff))) \
 175                          + UNSIGNED64 (0x800000000000000))
 176
 177 /* No sign extension */
 178 #define NOP(x)          (x)
 179
 180 #define INC_ADDR(x,i)   x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
 181
 182 #define RLW(x) load_mem (x, 4)
 183
 184 #ifdef _WIN32
 185 #ifndef SIGTRAP
 186 #define SIGTRAP 5
 187 #endif
 188 #ifndef SIGQUIT
 189 #define SIGQUIT 3
 190 #endif
 191 #endif
 192
 193 /* Function declarations.  */
 194
 195 #define IMEM(EA) \
 196 sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
 197                          PC, sim_core_execute_map, (EA))
 198
 199 #define IMEM_IMMED(EA,N) \
 200 sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
 201                          PC, sim_core_execute_map, (EA) + (N) * 2)
 202
 203 #define load_mem(ADDR,LEN) \
 204 sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \
 205                                PC, sim_core_read_map, (ADDR))
 206
 207 #define store_mem(ADDR,LEN,DATA) \
 208 sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
 209                                 PC, sim_core_write_map, (ADDR), (DATA))
 210
 211 #include "simops.h"