sim/v850/sim-main.h

   1 #ifndef SIM_MAIN_H
   2 #define SIM_MAIN_H
   3
   4 /* The v850 has 32bit words, numbered 31 (MSB) to 0 (LSB) */
   5
   6 #define WITH_TARGET_WORD_MSB 31
   7
   8 #include "sim-basics.h"
   9 #include "sim-signal.h"
  10 #include "sim-fpu.h"
  11 #include "sim-base.h"
  12
  13 #include "simops.h"
  14 #include "bfd.h"
  15
  16
  17 typedef signed8 int8;
  18 typedef unsigned8 uint8;
  19 typedef signed16 int16;
  20 typedef unsigned16 uint16;
  21 typedef signed32 int32;
  22 typedef unsigned32 uint32;
  23 typedef unsigned32 reg_t;
  24 typedef unsigned64 reg64_t;
  25
  26
  27 /* The current state of the processor; registers, memory, etc.  */
  28
  29 typedef struct _v850_regs {
  30   reg_t regs[32];               /* general-purpose registers */
  31   reg_t sregs[32];              /* system registers, including psw */
  32   reg_t pc;
  33   int dummy_mem;                /* where invalid accesses go */
  34   reg_t mpu0_sregs[28];         /* mpu0 system registers */
  35   reg_t mpu1_sregs[28];         /* mpu1 system registers */
  36   reg_t fpu_sregs[28];          /* fpu system registers */
  37   reg_t selID_sregs[7][32];     /* system registers, selID 1 thru selID 7 */
  38   reg64_t vregs[32];            /* vector registers.  */
  39 } v850_regs;
  40
  41 struct _sim_cpu
  42 {
  43   /* ... simulator specific members ... */
  44   v850_regs reg;
  45   reg_t psw_mask;               /* only allow non-reserved bits to be set */
  46   sim_event *pending_nmi;
  47   /* ... base type ... */
  48   sim_cpu_base base;
  49 };
  50
  51 /* For compatibility, until all functions converted to passing
  52    SIM_DESC as an argument */
  53 extern SIM_DESC simulator;
  54
  55
  56 #define V850_ROM_SIZE 0x8000
  57 #define V850_LOW_END 0x200000
  58 #define V850_HIGH_START 0xffe000
  59
  60
  61 /* Because we are still using the old semantic table, provide compat
  62    macro's that store the instruction where the old simops expects
  63    it. */
  64
  65 extern uint32 OP[4];
  66 #if 0
  67 OP[0] = inst & 0x1f;           /* RRRRR -> reg1 */
  68 OP[1] = (inst >> 11) & 0x1f;   /* rrrrr -> reg2 */
  69 OP[2] = (inst >> 16) & 0xffff; /* wwwww -> reg3 OR imm16 */
  70 OP[3] = inst;
  71 #endif
  72
  73 #define SAVE_1 \
  74 PC = cia; \
  75 OP[0] = instruction_0 & 0x1f; \
  76 OP[1] = (instruction_0 >> 11) & 0x1f; \
  77 OP[2] = 0; \
  78 OP[3] = instruction_0
  79
  80 #define COMPAT_1(CALL) \
  81 SAVE_1; \
  82 PC += (CALL); \
  83 nia = PC
  84
  85 #define SAVE_2 \
  86 PC = cia; \
  87 OP[0] = instruction_0 & 0x1f; \
  88 OP[1] = (instruction_0 >> 11) & 0x1f; \
  89 OP[2] = instruction_1; \
  90 OP[3] = (instruction_1 << 16) | instruction_0
  91
  92 #define COMPAT_2(CALL) \
  93 SAVE_2; \
  94 PC += (CALL); \
  95 nia = PC
  96
  97
  98 /* new */
  99 #define GR  ((CPU)->reg.regs)
 100 #define SR  ((CPU)->reg.sregs)
 101 #define VR  ((CPU)->reg.vregs)
 102 #define MPU0_SR  ((STATE_CPU (sd, 0))->reg.mpu0_sregs)
 103 #define MPU1_SR  ((STATE_CPU (sd, 0))->reg.mpu1_sregs)
 104 #define FPU_SR   ((STATE_CPU (sd, 0))->reg.fpu_sregs)
 105
 106 /* old */
 107 #define State    (STATE_CPU (simulator, 0)->reg)
 108 #define PC      (State.pc)
 109 #define SP_REGNO        3
 110 #define SP      (State.regs[SP_REGNO])
 111 #define EP      (State.regs[30])
 112
 113 #define EIPC  (State.sregs[0])
 114 #define EIPSW (State.sregs[1])
 115 #define FEPC  (State.sregs[2])
 116 #define FEPSW (State.sregs[3])
 117 #define ECR   (State.sregs[4])
 118 #define PSW   (State.sregs[5])
 119 #define PSW_REGNO   5
 120 #define EIIC  (State.sregs[13])
 121 #define FEIC  (State.sregs[14])
 122 #define DBIC  (SR[15])
 123 #define CTPC  (SR[16])
 124 #define CTPSW (SR[17])
 125 #define DBPC  (State.sregs[18])
 126 #define DBPSW (State.sregs[19])
 127 #define CTBP  (State.sregs[20])
 128 #define DIR   (SR[21])
 129 #define EIWR  (SR[28])
 130 #define FEWR  (SR[29])
 131 #define DBWR  (SR[30])
 132 #define BSEL  (SR[31])
 133
 134 #define PSW_US BIT32 (8)
 135 #define PSW_NP 0x80
 136 #define PSW_EP 0x40
 137 #define PSW_ID 0x20
 138 #define PSW_SAT 0x10
 139 #define PSW_CY 0x8
 140 #define PSW_OV 0x4
 141 #define PSW_S 0x2
 142 #define PSW_Z 0x1
 143
 144 #define PSW_NPV (1<<18)
 145 #define PSW_DMP (1<<17)
 146 #define PSW_IMP (1<<16)
 147
 148 #define ECR_EICC 0x0000ffff
 149 #define ECR_FECC 0xffff0000
 150
 151 /* FPU */
 152
 153 #define FPSR  (FPU_SR[6])
 154 #define FPSR_REGNO 6
 155 #define FPEPC (FPU_SR[7])
 156 #define FPST  (FPU_SR[8])
 157 #define FPST_REGNO 8
 158 #define FPCC  (FPU_SR[9])
 159 #define FPCFG (FPU_SR[10])
 160 #define FPCFG_REGNO 10
 161
 162 #define FPSR_DEM  0x00200000
 163 #define FPSR_SEM  0x00100000
 164 #define FPSR_RM   0x000c0000
 165 #define FPSR_RN   0x00000000
 166 #define FPSR_FS   0x00020000
 167 #define FPSR_PR   0x00010000
 168
 169 #define FPSR_XC   0x0000fc00
 170 #define FPSR_XCE  0x00008000
 171 #define FPSR_XCV  0x00004000
 172 #define FPSR_XCZ  0x00002000
 173 #define FPSR_XCO  0x00001000
 174 #define FPSR_XCU  0x00000800
 175 #define FPSR_XCI  0x00000400
 176
 177 #define FPSR_XE   0x000003e0
 178 #define FPSR_XEV  0x00000200
 179 #define FPSR_XEZ  0x00000100
 180 #define FPSR_XEO  0x00000080
 181 #define FPSR_XEU  0x00000040
 182 #define FPSR_XEI  0x00000020
 183
 184 #define FPSR_XP   0x0000001f
 185 #define FPSR_XPV  0x00000010
 186 #define FPSR_XPZ  0x00000008
 187 #define FPSR_XPO  0x00000004
 188 #define FPSR_XPU  0x00000002
 189 #define FPSR_XPI  0x00000001
 190
 191 #define FPST_PR   0x00008000
 192 #define FPST_XCE  0x00002000
 193 #define FPST_XCV  0x00001000
 194 #define FPST_XCZ  0x00000800
 195 #define FPST_XCO  0x00000400
 196 #define FPST_XCU  0x00000200
 197 #define FPST_XCI  0x00000100
 198
 199 #define FPST_XPV  0x00000010
 200 #define FPST_XPZ  0x00000008
 201 #define FPST_XPO  0x00000004
 202 #define FPST_XPU  0x00000002
 203 #define FPST_XPI  0x00000001
 204
 205 #define FPCFG_RM   0x00000180
 206 #define FPCFG_XEV  0x00000010
 207 #define FPCFG_XEZ  0x00000008
 208 #define FPCFG_XEO  0x00000004
 209 #define FPCFG_XEU  0x00000002
 210 #define FPCFG_XEI  0x00000001
 211
 212 #define GET_FPCC()\
 213  ((FPSR >> 24) &0xf)
 214
 215 #define CLEAR_FPCC(bbb)\
 216   (FPSR &= ~(1 << (bbb+24)))
 217
 218 #define SET_FPCC(bbb)\
 219  (FPSR |= 1 << (bbb+24))
 220
 221 #define TEST_FPCC(bbb)\
 222   ((FPSR & (1 << (bbb+24))) != 0)
 223
 224 #define FPSR_GET_ROUND()                                        \
 225   (((FPSR & FPSR_RM) == FPSR_RN) ? sim_fpu_round_near           \
 226    : ((FPSR & FPSR_RM) == 0x00040000) ? sim_fpu_round_up        \
 227    : ((FPSR & FPSR_RM) == 0x00080000) ? sim_fpu_round_down      \
 228    : sim_fpu_round_zero)
 229
 230
 231 enum FPU_COMPARE {
 232   FPU_CMP_F = 0,
 233   FPU_CMP_UN,
 234   FPU_CMP_EQ,
 235   FPU_CMP_UEQ,
 236   FPU_CMP_OLT,
 237   FPU_CMP_ULT,
 238   FPU_CMP_OLE,
 239   FPU_CMP_ULE,
 240   FPU_CMP_SF,
 241   FPU_CMP_NGLE,
 242   FPU_CMP_SEQ,
 243   FPU_CMP_NGL,
 244   FPU_CMP_LT,
 245   FPU_CMP_NGE,
 246   FPU_CMP_LE,
 247   FPU_CMP_NGT
 248 };
 249
 250
 251 /* MPU */
 252 #define MPM     (MPU1_SR[0])
 253 #define MPC     (MPU1_SR[1])
 254 #define MPC_REGNO 1
 255 #define TID     (MPU1_SR[2])
 256 #define PPA     (MPU1_SR[3])
 257 #define PPM     (MPU1_SR[4])
 258 #define PPC     (MPU1_SR[5])
 259 #define DCC     (MPU1_SR[6])
 260 #define DCV0    (MPU1_SR[7])
 261 #define DCV1    (MPU1_SR[8])
 262 #define SPAL    (MPU1_SR[10])
 263 #define SPAU    (MPU1_SR[11])
 264 #define IPA0L   (MPU1_SR[12])
 265 #define IPA0U   (MPU1_SR[13])
 266 #define IPA1L   (MPU1_SR[14])
 267 #define IPA1U   (MPU1_SR[15])
 268 #define IPA2L   (MPU1_SR[16])
 269 #define IPA2U   (MPU1_SR[17])
 270 #define IPA3L   (MPU1_SR[18])
 271 #define IPA3U   (MPU1_SR[19])
 272 #define DPA0L   (MPU1_SR[20])
 273 #define DPA0U   (MPU1_SR[21])
 274 #define DPA1L   (MPU1_SR[22])
 275 #define DPA1U   (MPU1_SR[23])
 276 #define DPA2L   (MPU1_SR[24])
 277 #define DPA2U   (MPU1_SR[25])
 278 #define DPA3L   (MPU1_SR[26])
 279 #define DPA3U   (MPU1_SR[27])
 280
 281 #define PPC_PPE 0x1
 282 #define SPAL_SPE 0x1
 283 #define SPAL_SPS 0x10
 284
 285 #define VIP     (MPU0_SR[0])
 286 #define VMECR   (MPU0_SR[4])
 287 #define VMTID   (MPU0_SR[5])
 288 #define VMADR   (MPU0_SR[6])
 289 #define VPECR   (MPU0_SR[8])
 290 #define VPTID   (MPU0_SR[9])
 291 #define VPADR   (MPU0_SR[10])
 292 #define VDECR   (MPU0_SR[12])
 293 #define VDTID   (MPU0_SR[13])
 294
 295 #define MPM_AUE 0x2
 296 #define MPM_MPE 0x1
 297
 298 #define VMECR_VMX   0x2
 299 #define VMECR_VMR   0x4
 300 #define VMECR_VMW   0x8
 301 #define VMECR_VMS   0x10
 302 #define VMECR_VMRMW 0x20
 303 #define VMECR_VMMS  0x40
 304
 305 #define IPA2ADDR(IPA)   ((IPA) & 0x1fffff80)
 306 #define IPA_IPE 0x1
 307 #define IPA_IPX 0x2
 308 #define IPA_IPR 0x4
 309 #define IPE0    (IPA0L & IPA_IPE)
 310 #define IPE1    (IPA1L & IPA_IPE)
 311 #define IPE2    (IPA2L & IPA_IPE)
 312 #define IPE3    (IPA3L & IPA_IPE)
 313 #define IPX0    (IPA0L & IPA_IPX)
 314 #define IPX1    (IPA1L & IPA_IPX)
 315 #define IPX2    (IPA2L & IPA_IPX)
 316 #define IPX3    (IPA3L & IPA_IPX)
 317 #define IPR0    (IPA0L & IPA_IPR)
 318 #define IPR1    (IPA1L & IPA_IPR)
 319 #define IPR2    (IPA2L & IPA_IPR)
 320 #define IPR3    (IPA3L & IPA_IPR)
 321
 322 #define DPA2ADDR(DPA)   ((DPA) & 0x1fffff80)
 323 #define DPA_DPE 0x1
 324 #define DPA_DPR 0x4
 325 #define DPA_DPW 0x8
 326 #define DPE0    (DPA0L & DPA_DPE)
 327 #define DPE1    (DPA1L & DPA_DPE)
 328 #define DPE2    (DPA2L & DPA_DPE)
 329 #define DPE3    (DPA3L & DPA_DPE)
 330 #define DPR0    (DPA0L & DPA_DPR)
 331 #define DPR1    (DPA1L & DPA_DPR)
 332 #define DPR2    (DPA2L & DPA_DPR)
 333 #define DPR3    (DPA3L & DPA_DPR)
 334 #define DPW0    (DPA0L & DPA_DPW)
 335 #define DPW1    (DPA1L & DPA_DPW)
 336 #define DPW2    (DPA2L & DPA_DPW)
 337 #define DPW3    (DPA3L & DPA_DPW)
 338
 339 #define DCC_DCE0 0x1
 340 #define DCC_DCE1 0x10000
 341
 342 #define PPA2ADDR(PPA)   ((PPA) & 0x1fffff80)
 343 #define PPC_PPC 0xfffffffe
 344 #define PPC_PPE 0x1
 345 #define PPC_PPM 0x0000fff8
 346
 347
 348 #define SEXT3(x)        ((((x)&0x7)^(~0x3))+0x4)
 349
 350 /* sign-extend a 4-bit number */
 351 #define SEXT4(x)        ((((x)&0xf)^(~0x7))+0x8)
 352
 353 /* sign-extend a 5-bit number */
 354 #define SEXT5(x)        ((((x)&0x1f)^(~0xf))+0x10)
 355
 356 /* sign-extend a 9-bit number */
 357 #define SEXT9(x)        ((((x)&0x1ff)^(~0xff))+0x100)
 358
 359 /* sign-extend a 22-bit number */
 360 #define SEXT22(x)       ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
 361
 362 /* sign extend a 40 bit number */
 363 #define SEXT40(x)       ((((x) & UNSIGNED64 (0xffffffffff)) \
 364                           ^ (~UNSIGNED64 (0x7fffffffff))) \
 365                          + UNSIGNED64 (0x8000000000))
 366
 367 /* sign extend a 44 bit number */
 368 #define SEXT44(x)       ((((x) & UNSIGNED64 (0xfffffffffff)) \
 369                           ^ (~ UNSIGNED64 (0x7ffffffffff))) \
 370                          + UNSIGNED64 (0x80000000000))
 371
 372 /* sign extend a 60 bit number */
 373 #define SEXT60(x)       ((((x) & UNSIGNED64 (0xfffffffffffffff)) \
 374                           ^ (~ UNSIGNED64 (0x7ffffffffffffff))) \
 375                          + UNSIGNED64 (0x800000000000000))
 376
 377 /* No sign extension */
 378 #define NOP(x)          (x)
 379
 380 #define INC_ADDR(x,i)   x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
 381
 382 #define RLW(x) load_mem (x, 4)
 383
 384 /* Function declarations.  */
 385
 386 #define IMEM16(EA) \
 387 sim_core_read_aligned_2 (CPU, PC, exec_map, (EA))
 388
 389 #define IMEM16_IMMED(EA,N) \
 390 sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
 391                          PC, exec_map, (EA) + (N) * 2)
 392
 393 #define load_mem(ADDR,LEN) \
 394 sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \
 395                                PC, read_map, (ADDR))
 396
 397 #define store_mem(ADDR,LEN,DATA) \
 398 sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
 399                                 PC, write_map, (ADDR), (DATA))
 400
 401
 402 /* compare cccc field against PSW */
 403 int condition_met (unsigned code);
 404
 405
 406 /* Debug/tracing calls */
 407
 408 enum op_types
 409 {
 410   OP_UNKNOWN,
 411   OP_NONE,
 412   OP_TRAP,
 413   OP_REG,
 414   OP_REG_REG,
 415   OP_REG_REG_CMP,
 416   OP_REG_REG_MOVE,
 417   OP_IMM_REG,
 418   OP_IMM_REG_CMP,
 419   OP_IMM_REG_MOVE,
 420   OP_COND_BR,
 421   OP_LOAD16,
 422   OP_STORE16,
 423   OP_LOAD32,
 424   OP_STORE32,
 425   OP_JUMP,
 426   OP_IMM_REG_REG,
 427   OP_UIMM_REG_REG,
 428   OP_IMM16_REG_REG,
 429   OP_UIMM16_REG_REG,
 430   OP_BIT,
 431   OP_EX1,
 432   OP_EX2,
 433   OP_LDSR,
 434   OP_STSR,
 435   OP_BIT_CHANGE,
 436   OP_REG_REG_REG,
 437   OP_REG_REG3,
 438   OP_IMM_REG_REG_REG,
 439   OP_PUSHPOP1,
 440   OP_PUSHPOP2,
 441   OP_PUSHPOP3,
 442 };
 443
 444 #ifdef DEBUG
 445 void trace_input (char *name, enum op_types type, int size);
 446 void trace_output (enum op_types result);
 447 void trace_result (int has_result, unsigned32 result);
 448
 449 extern int trace_num_values;
 450 extern unsigned32 trace_values[];
 451 extern unsigned32 trace_pc;
 452 extern const char *trace_name;
 453 extern int trace_module;
 454
 455 #define TRACE_BRANCH0() \
 456 do { \
 457   if (TRACE_BRANCH_P (CPU)) { \
 458     trace_module = TRACE_BRANCH_IDX; \
 459     trace_pc = cia; \
 460     trace_name = itable[MY_INDEX].name; \
 461     trace_num_values = 0; \
 462     trace_result (1, (nia)); \
 463   } \
 464 } while (0)
 465
 466 #define TRACE_BRANCH1(IN1) \
 467 do { \
 468   if (TRACE_BRANCH_P (CPU)) { \
 469     trace_module = TRACE_BRANCH_IDX; \
 470     trace_pc = cia; \
 471     trace_name = itable[MY_INDEX].name; \
 472     trace_values[0] = (IN1); \
 473     trace_num_values = 1; \
 474     trace_result (1, (nia)); \
 475   } \
 476 } while (0)
 477
 478 #define TRACE_BRANCH2(IN1, IN2) \
 479 do { \
 480   if (TRACE_BRANCH_P (CPU)) { \
 481     trace_module = TRACE_BRANCH_IDX; \
 482     trace_pc = cia; \
 483     trace_name = itable[MY_INDEX].name; \
 484     trace_values[0] = (IN1); \
 485     trace_values[1] = (IN2); \
 486     trace_num_values = 2; \
 487     trace_result (1, (nia)); \
 488   } \
 489 } while (0)
 490
 491 #define TRACE_BRANCH3(IN1, IN2, IN3) \
 492 do { \
 493   if (TRACE_BRANCH_P (CPU)) { \
 494     trace_module = TRACE_BRANCH_IDX; \
 495     trace_pc = cia; \
 496     trace_name = itable[MY_INDEX].name; \
 497     trace_values[0] = (IN1); \
 498     trace_values[1] = (IN2); \
 499     trace_values[2] = (IN3); \
 500     trace_num_values = 3; \
 501     trace_result (1, (nia)); \
 502   } \
 503 } while (0)
 504
 505 #define TRACE_LD(ADDR,RESULT) \
 506 do { \
 507   if (TRACE_MEMORY_P (CPU)) { \
 508     trace_module = TRACE_MEMORY_IDX; \
 509     trace_pc = cia; \
 510     trace_name = itable[MY_INDEX].name; \
 511     trace_values[0] = (ADDR); \
 512     trace_num_values = 1; \
 513     trace_result (1, (RESULT)); \
 514   } \
 515 } while (0)
 516
 517 #define TRACE_LD_NAME(NAME, ADDR,RESULT) \
 518 do { \
 519   if (TRACE_MEMORY_P (CPU)) { \
 520     trace_module = TRACE_MEMORY_IDX; \
 521     trace_pc = cia; \
 522     trace_name = (NAME); \
 523     trace_values[0] = (ADDR); \
 524     trace_num_values = 1; \
 525     trace_result (1, (RESULT)); \
 526   } \
 527 } while (0)
 528
 529 #define TRACE_ST(ADDR,RESULT) \
 530 do { \
 531   if (TRACE_MEMORY_P (CPU)) { \
 532     trace_module = TRACE_MEMORY_IDX; \
 533     trace_pc = cia; \
 534     trace_name = itable[MY_INDEX].name; \
 535     trace_values[0] = (ADDR); \
 536     trace_num_values = 1; \
 537     trace_result (1, (RESULT)); \
 538   } \
 539 } while (0)
 540
 541 #define TRACE_FP_INPUT_FPU1(V0) \
 542 do { \
 543   if (TRACE_FPU_P (CPU)) \
 544     { \
 545       unsigned64 f0; \
 546       sim_fpu_to64 (&f0, (V0)); \
 547       trace_input_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
 548     } \
 549 } while (0)
 550
 551 #define TRACE_FP_INPUT_FPU2(V0, V1) \
 552 do { \
 553   if (TRACE_FPU_P (CPU)) \
 554     { \
 555       unsigned64 f0, f1; \
 556       sim_fpu_to64 (&f0, (V0)); \
 557       sim_fpu_to64 (&f1, (V1)); \
 558       trace_input_fp2 (SD, CPU, TRACE_FPU_IDX, f0, f1); \
 559     } \
 560 } while (0)
 561
 562 #define TRACE_FP_INPUT_FPU3(V0, V1, V2) \
 563 do { \
 564   if (TRACE_FPU_P (CPU)) \
 565     { \
 566       unsigned64 f0, f1, f2; \
 567       sim_fpu_to64 (&f0, (V0)); \
 568       sim_fpu_to64 (&f1, (V1)); \
 569       sim_fpu_to64 (&f2, (V2)); \
 570       trace_input_fp3 (SD, CPU, TRACE_FPU_IDX, f0, f1, f2); \
 571     } \
 572 } while (0)
 573
 574 #define TRACE_FP_INPUT_BOOL1_FPU2(V0, V1, V2) \
 575 do { \
 576   if (TRACE_FPU_P (CPU)) \
 577     { \
 578       int d0 = (V0); \
 579       unsigned64 f1, f2; \
 580       TRACE_DATA *data = CPU_TRACE_DATA (CPU); \
 581       TRACE_IDX (data) = TRACE_FPU_IDX; \
 582       sim_fpu_to64 (&f1, (V1)); \
 583       sim_fpu_to64 (&f2, (V2)); \
 584       save_data (SD, data, trace_fmt_bool, sizeof (d0), &d0); \
 585       save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f1); \
 586       save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f2); \
 587     } \
 588 } while (0)
 589
 590 #define TRACE_FP_INPUT_WORD2(V0, V1) \
 591 do { \
 592   if (TRACE_FPU_P (CPU)) \
 593     trace_input_word2 (SD, CPU, TRACE_FPU_IDX, (V0), (V1)); \
 594 } while (0)
 595
 596 #define TRACE_FP_RESULT_FPU1(R0) \
 597 do { \
 598   if (TRACE_FPU_P (CPU)) \
 599     { \
 600       unsigned64 f0; \
 601       sim_fpu_to64 (&f0, (R0)); \
 602       trace_result_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
 603     } \
 604 } while (0)
 605
 606 #define TRACE_FP_RESULT_WORD1(R0) TRACE_FP_RESULT_WORD(R0)
 607
 608 #define TRACE_FP_RESULT_WORD2(R0, R1) \
 609 do { \
 610   if (TRACE_FPU_P (CPU)) \
 611     trace_result_word2 (SD, CPU, TRACE_FPU_IDX, (R0), (R1)); \
 612 } while (0)
 613
 614 #else
 615 #define trace_input(NAME, IN1, IN2)
 616 #define trace_output(RESULT)
 617 #define trace_result(HAS_RESULT, RESULT)
 618
 619 #define TRACE_ALU_INPUT0()
 620 #define TRACE_ALU_INPUT1(IN0)
 621 #define TRACE_ALU_INPUT2(IN0, IN1)
 622 #define TRACE_ALU_INPUT2(IN0, IN1)
 623 #define TRACE_ALU_INPUT2(IN0, IN1 INS2)
 624 #define TRACE_ALU_RESULT(RESULT)
 625
 626 #define TRACE_BRANCH0()
 627 #define TRACE_BRANCH1(IN1)
 628 #define TRACE_BRANCH2(IN1, IN2)
 629 #define TRACE_BRANCH2(IN1, IN2, IN3)
 630
 631 #define TRACE_LD(ADDR,RESULT)
 632 #define TRACE_ST(ADDR,RESULT)
 633
 634 #endif
 635
 636 #define GPR_SET(N, VAL) (State.regs[(N)] = (VAL))
 637 #define GPR_CLEAR(N)    (State.regs[(N)] = 0)
 638
 639 extern void divun ( unsigned int       N,
 640                     unsigned long int  als,
 641                     unsigned long int  sfi,
 642                     unsigned32 /*unsigned long int*/ *  quotient_ptr,
 643                     unsigned32 /*unsigned long int*/ *  remainder_ptr,
 644                     int *overflow_ptr
 645                     );
 646 extern void divn ( unsigned int       N,
 647                    unsigned long int  als,
 648                    unsigned long int  sfi,
 649                    signed32 /*signed long int*/ *  quotient_ptr,
 650                    signed32 /*signed long int*/ *  remainder_ptr,
 651                    int *overflow_ptr
 652                    );
 653 extern int type1_regs[];
 654 extern int type2_regs[];
 655 extern int type3_regs[];
 656
 657 #define SESR_OV   (1 << 0)
 658 #define SESR_SOV  (1 << 1)
 659
 660 #define SESR      (State.sregs[12])
 661
 662 #define ROUND_Q62_Q31(X) ((((X) + (1 << 30)) >> 31) & 0xffffffff)
 663 #define ROUND_Q62_Q15(X) ((((X) + (1 << 30)) >> 47) & 0xffff)
 664 #define ROUND_Q31_Q15(X) ((((X) + (1 << 15)) >> 15) & 0xffff)
 665 #define ROUND_Q30_Q15(X) ((((X) + (1 << 14)) >> 15) & 0xffff)
 666
 667 #define SAT16(X)                        \
 668   do                                    \
 669     {                                   \
 670       signed64 z = (X);                 \
 671       if (z > 0x7fff)                   \
 672         {                               \
 673           SESR |= SESR_OV | SESR_SOV;   \
 674           z = 0x7fff;                   \
 675         }                               \
 676       else if (z < -0x8000)             \
 677         {                               \
 678           SESR |= SESR_OV | SESR_SOV;   \
 679           z = - 0x8000;                 \
 680         }                               \
 681       (X) = z;                          \
 682     }                                   \
 683   while (0)
 684
 685 #define SAT32(X)                        \
 686   do                                    \
 687     {                                   \
 688       signed64 z = (X);                 \
 689       if (z > 0x7fffffff)               \
 690         {                               \
 691           SESR |= SESR_OV | SESR_SOV;   \
 692           z = 0x7fffffff;               \
 693         }                               \
 694       else if (z < -0x80000000)         \
 695         {                               \
 696           SESR |= SESR_OV | SESR_SOV;   \
 697           z = - 0x80000000;             \
 698         }                               \
 699       (X) = z;                          \
 700     }                                   \
 701   while (0)
 702
 703 #define ABS16(X)                        \
 704   do                                    \
 705     {                                   \
 706       signed64 z = (X) & 0xffff;        \
 707       if (z == 0x8000)                  \
 708         {                               \
 709           SESR |= SESR_OV | SESR_SOV;   \
 710           z = 0x7fff;                   \
 711         }                               \
 712       else if (z & 0x8000)              \
 713         {                               \
 714           z = (- z) & 0xffff;           \
 715         }                               \
 716       (X) = z;                          \
 717     }                                   \
 718   while (0)
 719
 720 #define ABS32(X)                        \
 721   do                                    \
 722     {                                   \
 723       signed64 z = (X) & 0xffffffff;    \
 724       if (z == 0x80000000)              \
 725         {                               \
 726           SESR |= SESR_OV | SESR_SOV;   \
 727           z = 0x7fffffff;               \
 728         }                               \
 729       else if (z & 0x80000000)          \
 730         {                               \
 731           z = (- z) & 0xffffffff;       \
 732         }                               \
 733       (X) = z;                          \
 734     }                                   \
 735   while (0)
 736
 737 #endif