sim/v850/sim-main.h

   1 #define WITH_CORE
   2 #define WITH_MODULO_MEMORY 1
   3 #define WITH_WATCHPOINTS 1
   4 #define WITH_TARGET_WORD_MSB 31
   5
   6 #include "sim-basics.h"
   7
   8 #include <signal.h>
   9 typedef address_word sim_cia;
  10
  11
  12 /* This simulator doesn't cache state */
  13 #define SIM_ENGINE_HALT_HOOK(sd,last_cpu,cia) while (0)
  14 #define SIM_ENGINE_RESTART_HOOK(sd,last_cpu,cia) while (0)
  15
  16 /* Get the number of instructions.  FIXME: must be a more elegant way
  17    of doing this.  */
  18 #include "itable.h"
  19 #define MAX_INSNS (nr_itable_entries)
  20 #define INSN_NAME(i) itable[(i)].name
  21
  22 #include "sim-base.h"
  23
  24 #include "simops.h"
  25 #include "bfd.h"
  26
  27
  28 typedef signed8 int8;
  29 typedef unsigned8 uint8;
  30 typedef signed16 int16;
  31 typedef unsigned16 uint16;
  32 typedef signed32 int32;
  33 typedef unsigned32 uint32;
  34 typedef unsigned32 reg_t;
  35
  36
  37 /* The current state of the processor; registers, memory, etc.  */
  38
  39 typedef struct _v850_regs {
  40   reg_t regs[32];               /* general-purpose registers */
  41   reg_t sregs[32];              /* system registers, including psw */
  42   reg_t pc;
  43   int dummy_mem;                /* where invalid accesses go */
  44 } v850_regs;
  45
  46 struct _sim_cpu
  47 {
  48   /* ... simulator specific members ... */
  49   v850_regs reg;
  50   reg_t psw_mask;               /* only allow non-reserved bits to be set */
  51   sim_event *pending_nmi;
  52   /* ... base type ... */
  53   sim_cpu_base base;
  54 };
  55
  56 #define CPU_CIA(CPU) ((CPU)->reg.pc)
  57
  58 struct sim_state {
  59   sim_cpu cpu[MAX_NR_PROCESSORS];
  60 #if (WITH_SMP)
  61 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
  62 #else
  63 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
  64 #endif
  65 #if 0
  66   SIM_ADDR rom_size;
  67   SIM_ADDR low_end;
  68   SIM_ADDR high_start;
  69   SIM_ADDR high_base;
  70   void *mem;
  71 #endif
  72   sim_state_base base;
  73 };
  74
  75 /* For compatibility, until all functions converted to passing
  76    SIM_DESC as an argument */
  77 extern SIM_DESC simulator;
  78
  79
  80 #define V850_ROM_SIZE 0x8000
  81 #define V850_LOW_END 0x200000
  82 #define V850_HIGH_START 0xffe000
  83
  84
  85 #define SIG_V850_EXIT   -1      /* indication of a normal exit */
  86
  87
  88 /* Because we are still using the old semantic table, provide compat
  89    macro's that store the instruction where the old simops expects
  90    it. */
  91
  92 extern uint32 OP[4];
  93 #if 0
  94 OP[0] = inst & 0x1f;           /* RRRRR -> reg1 */
  95 OP[1] = (inst >> 11) & 0x1f;   /* rrrrr -> reg2 */
  96 OP[2] = (inst >> 16) & 0xffff; /* wwwww -> reg3 OR imm16 */
  97 OP[3] = inst;
  98 #endif
  99
 100 #define SAVE_1 \
 101 PC = cia; \
 102 OP[0] = instruction_0 & 0x1f; \
 103 OP[1] = (instruction_0 >> 11) & 0x1f; \
 104 OP[2] = 0; \
 105 OP[3] = instruction_0
 106
 107 #define COMPAT_1(CALL) \
 108 SAVE_1; \
 109 PC += (CALL); \
 110 nia = PC
 111
 112 #define SAVE_2 \
 113 PC = cia; \
 114 OP[0] = instruction_0 & 0x1f; \
 115 OP[1] = (instruction_0 >> 11) & 0x1f; \
 116 OP[2] = instruction_1; \
 117 OP[3] = (instruction_1 << 16) | instruction_0
 118
 119 #define COMPAT_2(CALL) \
 120 SAVE_2; \
 121 PC += (CALL); \
 122 nia = PC
 123
 124
 125 /* new */
 126 #define GR  ((CPU)->reg.regs)
 127 #define SR  ((CPU)->reg.sregs)
 128
 129 /* old */
 130 #define State    (STATE_CPU (simulator, 0)->reg)
 131 #define PC      (State.pc)
 132 #define SP      (State.regs[3])
 133 #define EP      (State.regs[30])
 134
 135 #define EIPC  (State.sregs[0])
 136 #define EIPSW (State.sregs[1])
 137 #define FEPC  (State.sregs[2])
 138 #define FEPSW (State.sregs[3])
 139 #define ECR   (State.sregs[4])
 140 #define PSW   (State.sregs[5])
 141 /* start-sanitize-v850e */
 142 #define CTPC  (SR[16])
 143 #define CTPSW (SR[17])
 144 /* end-sanitize-v850e */
 145 #define DBPC  (State.sregs[18])
 146 #define DBPSW (State.sregs[19])
 147 /* start-sanitize-v850e */
 148 #define CTBP  (State.sregs[20])
 149 /* end-sanitize-v850e */
 150
 151 /* start-sanitize-v850eq */
 152 #define PSW_US BIT32 (8)
 153 /* end-sanitize-v850eq */
 154 #define PSW_NP 0x80
 155 #define PSW_EP 0x40
 156 #define PSW_ID 0x20
 157 #define PSW_SAT 0x10
 158 #define PSW_CY 0x8
 159 #define PSW_OV 0x4
 160 #define PSW_S 0x2
 161 #define PSW_Z 0x1
 162
 163 #define SEXT3(x)        ((((x)&0x7)^(~0x3))+0x4)
 164
 165 /* sign-extend a 4-bit number */
 166 #define SEXT4(x)        ((((x)&0xf)^(~0x7))+0x8)
 167
 168 /* sign-extend a 5-bit number */
 169 #define SEXT5(x)        ((((x)&0x1f)^(~0xf))+0x10)
 170
 171 /* sign-extend a 9-bit number */
 172 #define SEXT9(x)        ((((x)&0x1ff)^(~0xff))+0x100)
 173
 174 /* sign-extend a 22-bit number */
 175 #define SEXT22(x)       ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
 176
 177 /* sign extend a 40 bit number */
 178 #define SEXT40(x)       ((((x) & UNSIGNED64 (0xffffffffff)) \
 179                           ^ (~UNSIGNED64 (0x7fffffffff))) \
 180                          + UNSIGNED64 (0x8000000000))
 181
 182 /* sign extend a 44 bit number */
 183 #define SEXT44(x)       ((((x) & UNSIGNED64 (0xfffffffffff)) \
 184                           ^ (~ UNSIGNED64 (0x7ffffffffff))) \
 185                          + UNSIGNED64 (0x80000000000))
 186
 187 /* sign extend a 60 bit number */
 188 #define SEXT60(x)       ((((x) & UNSIGNED64 (0xfffffffffffffff)) \
 189                           ^ (~ UNSIGNED64 (0x7ffffffffffffff))) \
 190                          + UNSIGNED64 (0x800000000000000))
 191
 192 /* No sign extension */
 193 #define NOP(x)          (x)
 194
 195 #define INC_ADDR(x,i)   x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
 196
 197 #define RLW(x) load_mem (x, 4)
 198
 199 #ifdef _WIN32
 200 #ifndef SIGTRAP
 201 #define SIGTRAP 5
 202 #endif
 203 #ifndef SIGQUIT
 204 #define SIGQUIT 3
 205 #endif
 206 #endif
 207
 208 /* Function declarations.  */
 209
 210 #define IMEM(EA) \
 211 sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
 212                          PC, sim_core_execute_map, (EA))
 213
 214 #define IMEM_IMMED(EA,N) \
 215 sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
 216                          PC, sim_core_execute_map, (EA) + (N) * 2)
 217
 218 #define load_mem(ADDR,LEN) \
 219 sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \
 220                                PC, sim_core_read_map, (ADDR))
 221
 222 #define store_mem(ADDR,LEN,DATA) \
 223 sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
 224                                 PC, sim_core_write_map, (ADDR), (DATA))
 225
 226
 227 /* compare cccc field against PSW */
 228 unsigned int condition_met (unsigned code);
 229
 230
 231 /* Debug/tracing calls */
 232
 233 enum op_types
 234 {
 235   OP_UNKNOWN,
 236   OP_NONE,
 237   OP_TRAP,
 238   OP_REG,
 239   OP_REG_REG,
 240   OP_REG_REG_CMP,
 241   OP_REG_REG_MOVE,
 242   OP_IMM_REG,
 243   OP_IMM_REG_CMP,
 244   OP_IMM_REG_MOVE,
 245   OP_COND_BR,
 246   OP_LOAD16,
 247   OP_STORE16,
 248   OP_LOAD32,
 249   OP_STORE32,
 250   OP_JUMP,
 251   OP_IMM_REG_REG,
 252   OP_UIMM_REG_REG,
 253   OP_IMM16_REG_REG,
 254   OP_UIMM16_REG_REG,
 255   OP_BIT,
 256   OP_EX1,
 257   OP_EX2,
 258   OP_LDSR,
 259   OP_STSR,
 260 /* start-sanitize-v850e */
 261   OP_BIT_CHANGE,
 262   OP_REG_REG_REG,
 263   OP_REG_REG3,
 264 /* end-sanitize-v850e */
 265 /* start-sanitize-v850eq */
 266   OP_IMM_REG_REG_REG,
 267   OP_PUSHPOP1,
 268   OP_PUSHPOP2,
 269   OP_PUSHPOP3,
 270 /* end-sanitize-v850eq */
 271 };
 272
 273 #ifdef DEBUG
 274 void trace_input PARAMS ((char *name, enum op_types type, int size));
 275 void trace_output PARAMS ((enum op_types result));
 276 void trace_result PARAMS ((int has_result, unsigned32 result));
 277
 278 extern int trace_num_values;
 279 extern unsigned32 trace_values[];
 280 extern unsigned32 trace_pc;
 281 extern const char *trace_name;
 282 extern const char *trace_module;
 283
 284 #define TRACE_ALU_INPUT0() \
 285 do { \
 286   if (TRACE_ALU_P (CPU)) { \
 287     trace_module = "alu"; \
 288     trace_pc = cia; \
 289     trace_name = itable[MY_INDEX].name; \
 290     trace_num_values = 0; \
 291   } \
 292 } while (0)
 293
 294 #define TRACE_ALU_INPUT1(IN1) \
 295 do { \
 296   if (TRACE_ALU_P (CPU)) { \
 297     trace_module = "alu"; \
 298     trace_pc = cia; \
 299     trace_name = itable[MY_INDEX].name; \
 300     trace_values[0] = (IN1); \
 301     trace_num_values = 1; \
 302   } \
 303 } while (0)
 304
 305 #define TRACE_ALU_INPUT2(IN1, IN2) \
 306 do { \
 307   if (TRACE_ALU_P (CPU)) { \
 308     trace_module = "alu"; \
 309     trace_pc = cia; \
 310     trace_name = itable[MY_INDEX].name; \
 311     trace_values[0] = (IN1); \
 312     trace_values[1] = (IN2); \
 313     trace_num_values = 2; \
 314   } \
 315 } while (0)
 316
 317 #define TRACE_ALU_INPUT3(IN0, IN1, IN2) \
 318 do { \
 319   if (TRACE_ALU_P (CPU)) { \
 320     trace_module = "alu"; \
 321     trace_pc = cia; \
 322     trace_name = itable[MY_INDEX].name; \
 323     trace_values[0] = (IN0); \
 324     trace_values[1] = (IN1); \
 325     trace_values[2] = (IN2); \
 326     trace_num_values = 3; \
 327   } \
 328 } while (0)
 329
 330 #define TRACE_ALU_RESULT(RESULT) \
 331 do { \
 332   if (TRACE_ALU_P (CPU)) { \
 333     trace_result (1, (RESULT)); \
 334   } \
 335 } while (0)
 336
 337 #define TRACE_BRANCH1(IN1) \
 338 do { \
 339   if (TRACE_BRANCH_P (CPU)) { \
 340     trace_module = "branch"; \
 341     trace_pc = cia; \
 342     trace_name = itable[MY_INDEX].name; \
 343     trace_values[0] = (IN1); \
 344     trace_num_values = 1; \
 345     trace_result (1, (nia)); \
 346   } \
 347 } while (0)
 348
 349 #define TRACE_BRANCH2(IN1, IN2) \
 350 do { \
 351   if (TRACE_BRANCH_P (CPU)) { \
 352     trace_module = "branch"; \
 353     trace_pc = cia; \
 354     trace_name = itable[MY_INDEX].name; \
 355     trace_values[0] = (IN1); \
 356     trace_values[1] = (IN2); \
 357     trace_num_values = 2; \
 358     trace_result (1, (nia)); \
 359   } \
 360 } while (0)
 361
 362 #define TRACE_BRANCH3(IN1, IN2, IN3) \
 363 do { \
 364   if (TRACE_BRANCH_P (CPU)) { \
 365     trace_module = "branch"; \
 366     trace_pc = cia; \
 367     trace_name = itable[MY_INDEX].name; \
 368     trace_values[0] = (IN1); \
 369     trace_values[1] = (IN2); \
 370     trace_values[2] = (IN3); \
 371     trace_num_values = 3; \
 372     trace_result (1, (nia)); \
 373   } \
 374 } while (0)
 375
 376
 377 #else
 378 #define trace_input(NAME, IN1, IN2)
 379 #define trace_output(RESULT)
 380 #define trace_result(HAS_RESULT, RESULT)
 381
 382 #define TRACE_ALU_INPUT0()
 383 #define TRACE_ALU_INPUT1(IN1)
 384 #define TRACE_ALU_INPUT2(IN1, IN2)
 385 #define TRACE_ALU_RESULT(RESULT)
 386
 387 #define TRACE_BRANCH1(IN1)
 388 #define TRACE_BRANCH2(IN1, IN2)
 389 #define TRACE_BRANCH2(IN1, IN2, IN3)
 390 #endif
 391
 392
 393 /* start-sanitize-v850eq */
 394 extern void divun ( unsigned int       N,
 395                     unsigned long int  als,
 396                     unsigned long int  sfi,
 397                     unsigned long int *  quotient_ptr,
 398                     unsigned long int *  remainder_ptr,
 399                     boolean *          overflow_ptr
 400                     );
 401 extern void divn ( unsigned int       N,
 402                    unsigned long int  als,
 403                    unsigned long int  sfi,
 404                    signed long int *  quotient_ptr,
 405                    signed long int *  remainder_ptr,
 406                    boolean *          overflow_ptr
 407                    );
 408 /* end-sanitize-v850eq */
 409 /* start-sanitize-v850e */
 410 extern int type1_regs[];
 411 extern int type2_regs[];
 412 /* end-sanitize-v850e */
 413 /* start-sanitize-v850eq */
 414 extern int type3_regs[];
 415 /* end-sanitize-v850eq */