sim/v850/sim-main.h

   1 #ifndef SIM_MAIN_H
   2 #define SIM_MAIN_H
   3
   4 /* General config options */
   5
   6 #define WITH_CORE
   7 #define WITH_MODULO_MEMORY 1
   8 #define WITH_WATCHPOINTS 1
   9
  10
  11 /* The v850 has 32bit words, numbered 31 (MSB) to 0 (LSB) */
  12
  13 #define WITH_TARGET_WORD_MSB 31
  14
  15 #include "config.h"
  16 #include "sim-basics.h"
  17 #include "sim-signal.h"
  18 #include "sim-fpu.h"
  19
  20 typedef struct _sim_cpu SIM_CPU;
  21
  22 #include "sim-base.h"
  23
  24 #include "simops.h"
  25 #include "bfd.h"
  26
  27
  28 typedef signed8 int8;
  29 typedef unsigned8 uint8;
  30 typedef signed16 int16;
  31 typedef unsigned16 uint16;
  32 typedef signed32 int32;
  33 typedef unsigned32 uint32;
  34 typedef unsigned32 reg_t;
  35 typedef unsigned64 reg64_t;
  36
  37
  38 /* The current state of the processor; registers, memory, etc.  */
  39
  40 typedef struct _v850_regs {
  41   reg_t regs[32];               /* general-purpose registers */
  42   reg_t sregs[32];              /* system registers, including psw */
  43   reg_t pc;
  44   int dummy_mem;                /* where invalid accesses go */
  45   reg_t mpu0_sregs[28];         /* mpu0 system registers */
  46   reg_t mpu1_sregs[28];         /* mpu1 system registers */
  47   reg_t fpu_sregs[28];          /* fpu system registers */
  48   reg_t selID_sregs[7][32];     /* system registers, selID 1 thru selID 7 */
  49   reg64_t vregs[32];            /* vector registers.  */
  50 } v850_regs;
  51
  52 struct _sim_cpu
  53 {
  54   /* ... simulator specific members ... */
  55   v850_regs reg;
  56   reg_t psw_mask;               /* only allow non-reserved bits to be set */
  57   sim_event *pending_nmi;
  58   /* ... base type ... */
  59   sim_cpu_base base;
  60 };
  61
  62 struct sim_state {
  63   sim_cpu *cpu[MAX_NR_PROCESSORS];
  64 #if 0
  65   SIM_ADDR rom_size;
  66   SIM_ADDR low_end;
  67   SIM_ADDR high_start;
  68   SIM_ADDR high_base;
  69   void *mem;
  70 #endif
  71   sim_state_base base;
  72 };
  73
  74 /* For compatibility, until all functions converted to passing
  75    SIM_DESC as an argument */
  76 extern SIM_DESC simulator;
  77
  78
  79 #define V850_ROM_SIZE 0x8000
  80 #define V850_LOW_END 0x200000
  81 #define V850_HIGH_START 0xffe000
  82
  83
  84 /* Because we are still using the old semantic table, provide compat
  85    macro's that store the instruction where the old simops expects
  86    it. */
  87
  88 extern uint32 OP[4];
  89 #if 0
  90 OP[0] = inst & 0x1f;           /* RRRRR -> reg1 */
  91 OP[1] = (inst >> 11) & 0x1f;   /* rrrrr -> reg2 */
  92 OP[2] = (inst >> 16) & 0xffff; /* wwwww -> reg3 OR imm16 */
  93 OP[3] = inst;
  94 #endif
  95
  96 #define SAVE_1 \
  97 PC = cia; \
  98 OP[0] = instruction_0 & 0x1f; \
  99 OP[1] = (instruction_0 >> 11) & 0x1f; \
 100 OP[2] = 0; \
 101 OP[3] = instruction_0
 102
 103 #define COMPAT_1(CALL) \
 104 SAVE_1; \
 105 PC += (CALL); \
 106 nia = PC
 107
 108 #define SAVE_2 \
 109 PC = cia; \
 110 OP[0] = instruction_0 & 0x1f; \
 111 OP[1] = (instruction_0 >> 11) & 0x1f; \
 112 OP[2] = instruction_1; \
 113 OP[3] = (instruction_1 << 16) | instruction_0
 114
 115 #define COMPAT_2(CALL) \
 116 SAVE_2; \
 117 PC += (CALL); \
 118 nia = PC
 119
 120
 121 /* new */
 122 #define GR  ((CPU)->reg.regs)
 123 #define SR  ((CPU)->reg.sregs)
 124 #define VR  ((CPU)->reg.vregs)
 125 #define MPU0_SR  ((STATE_CPU (sd, 0))->reg.mpu0_sregs)
 126 #define MPU1_SR  ((STATE_CPU (sd, 0))->reg.mpu1_sregs)
 127 #define FPU_SR   ((STATE_CPU (sd, 0))->reg.fpu_sregs)
 128
 129 /* old */
 130 #define State    (STATE_CPU (simulator, 0)->reg)
 131 #define PC      (State.pc)
 132 #define SP_REGNO        3
 133 #define SP      (State.regs[SP_REGNO])
 134 #define EP      (State.regs[30])
 135
 136 #define EIPC  (State.sregs[0])
 137 #define EIPSW (State.sregs[1])
 138 #define FEPC  (State.sregs[2])
 139 #define FEPSW (State.sregs[3])
 140 #define ECR   (State.sregs[4])
 141 #define PSW   (State.sregs[5])
 142 #define PSW_REGNO   5
 143 #define EIIC  (State.sregs[13])
 144 #define FEIC  (State.sregs[14])
 145 #define DBIC  (SR[15])
 146 #define CTPC  (SR[16])
 147 #define CTPSW (SR[17])
 148 #define DBPC  (State.sregs[18])
 149 #define DBPSW (State.sregs[19])
 150 #define CTBP  (State.sregs[20])
 151 #define DIR   (SR[21])
 152 #define EIWR  (SR[28])
 153 #define FEWR  (SR[29])
 154 #define DBWR  (SR[30])
 155 #define BSEL  (SR[31])
 156
 157 #define PSW_US BIT32 (8)
 158 #define PSW_NP 0x80
 159 #define PSW_EP 0x40
 160 #define PSW_ID 0x20
 161 #define PSW_SAT 0x10
 162 #define PSW_CY 0x8
 163 #define PSW_OV 0x4
 164 #define PSW_S 0x2
 165 #define PSW_Z 0x1
 166
 167 #define PSW_NPV (1<<18)
 168 #define PSW_DMP (1<<17)
 169 #define PSW_IMP (1<<16)
 170
 171 #define ECR_EICC 0x0000ffff
 172 #define ECR_FECC 0xffff0000
 173
 174 /* FPU */
 175
 176 #define FPSR  (FPU_SR[6])
 177 #define FPSR_REGNO 6
 178 #define FPEPC (FPU_SR[7])
 179 #define FPST  (FPU_SR[8])
 180 #define FPST_REGNO 8
 181 #define FPCC  (FPU_SR[9])
 182 #define FPCFG (FPU_SR[10])
 183 #define FPCFG_REGNO 10
 184
 185 #define FPSR_DEM  0x00200000
 186 #define FPSR_SEM  0x00100000
 187 #define FPSR_RM   0x000c0000
 188 #define FPSR_RN   0x00000000
 189 #define FPSR_FS   0x00020000
 190 #define FPSR_PR   0x00010000
 191
 192 #define FPSR_XC   0x0000fc00
 193 #define FPSR_XCE  0x00008000
 194 #define FPSR_XCV  0x00004000
 195 #define FPSR_XCZ  0x00002000
 196 #define FPSR_XCO  0x00001000
 197 #define FPSR_XCU  0x00000800
 198 #define FPSR_XCI  0x00000400
 199
 200 #define FPSR_XE   0x000003e0
 201 #define FPSR_XEV  0x00000200
 202 #define FPSR_XEZ  0x00000100
 203 #define FPSR_XEO  0x00000080
 204 #define FPSR_XEU  0x00000040
 205 #define FPSR_XEI  0x00000020
 206
 207 #define FPSR_XP   0x0000001f
 208 #define FPSR_XPV  0x00000010
 209 #define FPSR_XPZ  0x00000008
 210 #define FPSR_XPO  0x00000004
 211 #define FPSR_XPU  0x00000002
 212 #define FPSR_XPI  0x00000001
 213
 214 #define FPST_PR   0x00008000
 215 #define FPST_XCE  0x00002000
 216 #define FPST_XCV  0x00001000
 217 #define FPST_XCZ  0x00000800
 218 #define FPST_XCO  0x00000400
 219 #define FPST_XCU  0x00000200
 220 #define FPST_XCI  0x00000100
 221
 222 #define FPST_XPV  0x00000010
 223 #define FPST_XPZ  0x00000008
 224 #define FPST_XPO  0x00000004
 225 #define FPST_XPU  0x00000002
 226 #define FPST_XPI  0x00000001
 227
 228 #define FPCFG_RM   0x00000180
 229 #define FPCFG_XEV  0x00000010
 230 #define FPCFG_XEZ  0x00000008
 231 #define FPCFG_XEO  0x00000004
 232 #define FPCFG_XEU  0x00000002
 233 #define FPCFG_XEI  0x00000001
 234
 235 #define GET_FPCC()\
 236  ((FPSR >> 24) &0xf)
 237
 238 #define CLEAR_FPCC(bbb)\
 239   (FPSR &= ~(1 << (bbb+24)))
 240
 241 #define SET_FPCC(bbb)\
 242  (FPSR |= 1 << (bbb+24))
 243
 244 #define TEST_FPCC(bbb)\
 245   ((FPSR & (1 << (bbb+24))) != 0)
 246
 247 #define FPSR_GET_ROUND()                                        \
 248   (((FPSR & FPSR_RM) == FPSR_RN) ? sim_fpu_round_near           \
 249    : ((FPSR & FPSR_RM) == 0x00040000) ? sim_fpu_round_up        \
 250    : ((FPSR & FPSR_RM) == 0x00080000) ? sim_fpu_round_down      \
 251    : sim_fpu_round_zero)
 252
 253
 254 enum FPU_COMPARE {
 255   FPU_CMP_F = 0,
 256   FPU_CMP_UN,
 257   FPU_CMP_EQ,
 258   FPU_CMP_UEQ,
 259   FPU_CMP_OLT,
 260   FPU_CMP_ULT,
 261   FPU_CMP_OLE,
 262   FPU_CMP_ULE,
 263   FPU_CMP_SF,
 264   FPU_CMP_NGLE,
 265   FPU_CMP_SEQ,
 266   FPU_CMP_NGL,
 267   FPU_CMP_LT,
 268   FPU_CMP_NGE,
 269   FPU_CMP_LE,
 270   FPU_CMP_NGT
 271 };
 272
 273
 274 /* MPU */
 275 #define MPM     (MPU1_SR[0])
 276 #define MPC     (MPU1_SR[1])
 277 #define MPC_REGNO 1
 278 #define TID     (MPU1_SR[2])
 279 #define PPA     (MPU1_SR[3])
 280 #define PPM     (MPU1_SR[4])
 281 #define PPC     (MPU1_SR[5])
 282 #define DCC     (MPU1_SR[6])
 283 #define DCV0    (MPU1_SR[7])
 284 #define DCV1    (MPU1_SR[8])
 285 #define SPAL    (MPU1_SR[10])
 286 #define SPAU    (MPU1_SR[11])
 287 #define IPA0L   (MPU1_SR[12])
 288 #define IPA0U   (MPU1_SR[13])
 289 #define IPA1L   (MPU1_SR[14])
 290 #define IPA1U   (MPU1_SR[15])
 291 #define IPA2L   (MPU1_SR[16])
 292 #define IPA2U   (MPU1_SR[17])
 293 #define IPA3L   (MPU1_SR[18])
 294 #define IPA3U   (MPU1_SR[19])
 295 #define DPA0L   (MPU1_SR[20])
 296 #define DPA0U   (MPU1_SR[21])
 297 #define DPA1L   (MPU1_SR[22])
 298 #define DPA1U   (MPU1_SR[23])
 299 #define DPA2L   (MPU1_SR[24])
 300 #define DPA2U   (MPU1_SR[25])
 301 #define DPA3L   (MPU1_SR[26])
 302 #define DPA3U   (MPU1_SR[27])
 303
 304 #define PPC_PPE 0x1
 305 #define SPAL_SPE 0x1
 306 #define SPAL_SPS 0x10
 307
 308 #define VIP     (MPU0_SR[0])
 309 #define VMECR   (MPU0_SR[4])
 310 #define VMTID   (MPU0_SR[5])
 311 #define VMADR   (MPU0_SR[6])
 312 #define VPECR   (MPU0_SR[8])
 313 #define VPTID   (MPU0_SR[9])
 314 #define VPADR   (MPU0_SR[10])
 315 #define VDECR   (MPU0_SR[12])
 316 #define VDTID   (MPU0_SR[13])
 317
 318 #define MPM_AUE 0x2
 319 #define MPM_MPE 0x1
 320
 321 #define VMECR_VMX   0x2
 322 #define VMECR_VMR   0x4
 323 #define VMECR_VMW   0x8
 324 #define VMECR_VMS   0x10
 325 #define VMECR_VMRMW 0x20
 326 #define VMECR_VMMS  0x40
 327
 328 #define IPA2ADDR(IPA)   ((IPA) & 0x1fffff80)
 329 #define IPA_IPE 0x1
 330 #define IPA_IPX 0x2
 331 #define IPA_IPR 0x4
 332 #define IPE0    (IPA0L & IPA_IPE)
 333 #define IPE1    (IPA1L & IPA_IPE)
 334 #define IPE2    (IPA2L & IPA_IPE)
 335 #define IPE3    (IPA3L & IPA_IPE)
 336 #define IPX0    (IPA0L & IPA_IPX)
 337 #define IPX1    (IPA1L & IPA_IPX)
 338 #define IPX2    (IPA2L & IPA_IPX)
 339 #define IPX3    (IPA3L & IPA_IPX)
 340 #define IPR0    (IPA0L & IPA_IPR)
 341 #define IPR1    (IPA1L & IPA_IPR)
 342 #define IPR2    (IPA2L & IPA_IPR)
 343 #define IPR3    (IPA3L & IPA_IPR)
 344
 345 #define DPA2ADDR(DPA)   ((DPA) & 0x1fffff80)
 346 #define DPA_DPE 0x1
 347 #define DPA_DPR 0x4
 348 #define DPA_DPW 0x8
 349 #define DPE0    (DPA0L & DPA_DPE)
 350 #define DPE1    (DPA1L & DPA_DPE)
 351 #define DPE2    (DPA2L & DPA_DPE)
 352 #define DPE3    (DPA3L & DPA_DPE)
 353 #define DPR0    (DPA0L & DPA_DPR)
 354 #define DPR1    (DPA1L & DPA_DPR)
 355 #define DPR2    (DPA2L & DPA_DPR)
 356 #define DPR3    (DPA3L & DPA_DPR)
 357 #define DPW0    (DPA0L & DPA_DPW)
 358 #define DPW1    (DPA1L & DPA_DPW)
 359 #define DPW2    (DPA2L & DPA_DPW)
 360 #define DPW3    (DPA3L & DPA_DPW)
 361
 362 #define DCC_DCE0 0x1
 363 #define DCC_DCE1 0x10000
 364
 365 #define PPA2ADDR(PPA)   ((PPA) & 0x1fffff80)
 366 #define PPC_PPC 0xfffffffe
 367 #define PPC_PPE 0x1
 368 #define PPC_PPM 0x0000fff8
 369
 370
 371 #define SEXT3(x)        ((((x)&0x7)^(~0x3))+0x4)
 372
 373 /* sign-extend a 4-bit number */
 374 #define SEXT4(x)        ((((x)&0xf)^(~0x7))+0x8)
 375
 376 /* sign-extend a 5-bit number */
 377 #define SEXT5(x)        ((((x)&0x1f)^(~0xf))+0x10)
 378
 379 /* sign-extend a 9-bit number */
 380 #define SEXT9(x)        ((((x)&0x1ff)^(~0xff))+0x100)
 381
 382 /* sign-extend a 22-bit number */
 383 #define SEXT22(x)       ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
 384
 385 /* sign extend a 40 bit number */
 386 #define SEXT40(x)       ((((x) & UNSIGNED64 (0xffffffffff)) \
 387                           ^ (~UNSIGNED64 (0x7fffffffff))) \
 388                          + UNSIGNED64 (0x8000000000))
 389
 390 /* sign extend a 44 bit number */
 391 #define SEXT44(x)       ((((x) & UNSIGNED64 (0xfffffffffff)) \
 392                           ^ (~ UNSIGNED64 (0x7ffffffffff))) \
 393                          + UNSIGNED64 (0x80000000000))
 394
 395 /* sign extend a 60 bit number */
 396 #define SEXT60(x)       ((((x) & UNSIGNED64 (0xfffffffffffffff)) \
 397                           ^ (~ UNSIGNED64 (0x7ffffffffffffff))) \
 398                          + UNSIGNED64 (0x800000000000000))
 399
 400 /* No sign extension */
 401 #define NOP(x)          (x)
 402
 403 #define INC_ADDR(x,i)   x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
 404
 405 #define RLW(x) load_mem (x, 4)
 406
 407 /* Function declarations.  */
 408
 409 #define IMEM16(EA) \
 410 sim_core_read_aligned_2 (CPU, PC, exec_map, (EA))
 411
 412 #define IMEM16_IMMED(EA,N) \
 413 sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
 414                          PC, exec_map, (EA) + (N) * 2)
 415
 416 #define load_mem(ADDR,LEN) \
 417 sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \
 418                                PC, read_map, (ADDR))
 419
 420 #define store_mem(ADDR,LEN,DATA) \
 421 sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
 422                                 PC, write_map, (ADDR), (DATA))
 423
 424
 425 /* compare cccc field against PSW */
 426 int condition_met (unsigned code);
 427
 428
 429 /* Debug/tracing calls */
 430
 431 enum op_types
 432 {
 433   OP_UNKNOWN,
 434   OP_NONE,
 435   OP_TRAP,
 436   OP_REG,
 437   OP_REG_REG,
 438   OP_REG_REG_CMP,
 439   OP_REG_REG_MOVE,
 440   OP_IMM_REG,
 441   OP_IMM_REG_CMP,
 442   OP_IMM_REG_MOVE,
 443   OP_COND_BR,
 444   OP_LOAD16,
 445   OP_STORE16,
 446   OP_LOAD32,
 447   OP_STORE32,
 448   OP_JUMP,
 449   OP_IMM_REG_REG,
 450   OP_UIMM_REG_REG,
 451   OP_IMM16_REG_REG,
 452   OP_UIMM16_REG_REG,
 453   OP_BIT,
 454   OP_EX1,
 455   OP_EX2,
 456   OP_LDSR,
 457   OP_STSR,
 458   OP_BIT_CHANGE,
 459   OP_REG_REG_REG,
 460   OP_REG_REG3,
 461   OP_IMM_REG_REG_REG,
 462   OP_PUSHPOP1,
 463   OP_PUSHPOP2,
 464   OP_PUSHPOP3,
 465 };
 466
 467 #ifdef DEBUG
 468 void trace_input (char *name, enum op_types type, int size);
 469 void trace_output (enum op_types result);
 470 void trace_result (int has_result, unsigned32 result);
 471
 472 extern int trace_num_values;
 473 extern unsigned32 trace_values[];
 474 extern unsigned32 trace_pc;
 475 extern const char *trace_name;
 476 extern int trace_module;
 477
 478 #define TRACE_BRANCH0() \
 479 do { \
 480   if (TRACE_BRANCH_P (CPU)) { \
 481     trace_module = TRACE_BRANCH_IDX; \
 482     trace_pc = cia; \
 483     trace_name = itable[MY_INDEX].name; \
 484     trace_num_values = 0; \
 485     trace_result (1, (nia)); \
 486   } \
 487 } while (0)
 488
 489 #define TRACE_BRANCH1(IN1) \
 490 do { \
 491   if (TRACE_BRANCH_P (CPU)) { \
 492     trace_module = TRACE_BRANCH_IDX; \
 493     trace_pc = cia; \
 494     trace_name = itable[MY_INDEX].name; \
 495     trace_values[0] = (IN1); \
 496     trace_num_values = 1; \
 497     trace_result (1, (nia)); \
 498   } \
 499 } while (0)
 500
 501 #define TRACE_BRANCH2(IN1, IN2) \
 502 do { \
 503   if (TRACE_BRANCH_P (CPU)) { \
 504     trace_module = TRACE_BRANCH_IDX; \
 505     trace_pc = cia; \
 506     trace_name = itable[MY_INDEX].name; \
 507     trace_values[0] = (IN1); \
 508     trace_values[1] = (IN2); \
 509     trace_num_values = 2; \
 510     trace_result (1, (nia)); \
 511   } \
 512 } while (0)
 513
 514 #define TRACE_BRANCH3(IN1, IN2, IN3) \
 515 do { \
 516   if (TRACE_BRANCH_P (CPU)) { \
 517     trace_module = TRACE_BRANCH_IDX; \
 518     trace_pc = cia; \
 519     trace_name = itable[MY_INDEX].name; \
 520     trace_values[0] = (IN1); \
 521     trace_values[1] = (IN2); \
 522     trace_values[2] = (IN3); \
 523     trace_num_values = 3; \
 524     trace_result (1, (nia)); \
 525   } \
 526 } while (0)
 527
 528 #define TRACE_LD(ADDR,RESULT) \
 529 do { \
 530   if (TRACE_MEMORY_P (CPU)) { \
 531     trace_module = TRACE_MEMORY_IDX; \
 532     trace_pc = cia; \
 533     trace_name = itable[MY_INDEX].name; \
 534     trace_values[0] = (ADDR); \
 535     trace_num_values = 1; \
 536     trace_result (1, (RESULT)); \
 537   } \
 538 } while (0)
 539
 540 #define TRACE_LD_NAME(NAME, ADDR,RESULT) \
 541 do { \
 542   if (TRACE_MEMORY_P (CPU)) { \
 543     trace_module = TRACE_MEMORY_IDX; \
 544     trace_pc = cia; \
 545     trace_name = (NAME); \
 546     trace_values[0] = (ADDR); \
 547     trace_num_values = 1; \
 548     trace_result (1, (RESULT)); \
 549   } \
 550 } while (0)
 551
 552 #define TRACE_ST(ADDR,RESULT) \
 553 do { \
 554   if (TRACE_MEMORY_P (CPU)) { \
 555     trace_module = TRACE_MEMORY_IDX; \
 556     trace_pc = cia; \
 557     trace_name = itable[MY_INDEX].name; \
 558     trace_values[0] = (ADDR); \
 559     trace_num_values = 1; \
 560     trace_result (1, (RESULT)); \
 561   } \
 562 } while (0)
 563
 564 #define TRACE_FP_INPUT_FPU1(V0) \
 565 do { \
 566   if (TRACE_FPU_P (CPU)) \
 567     { \
 568       unsigned64 f0; \
 569       sim_fpu_to64 (&f0, (V0)); \
 570       trace_input_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
 571     } \
 572 } while (0)
 573
 574 #define TRACE_FP_INPUT_FPU2(V0, V1) \
 575 do { \
 576   if (TRACE_FPU_P (CPU)) \
 577     { \
 578       unsigned64 f0, f1; \
 579       sim_fpu_to64 (&f0, (V0)); \
 580       sim_fpu_to64 (&f1, (V1)); \
 581       trace_input_fp2 (SD, CPU, TRACE_FPU_IDX, f0, f1); \
 582     } \
 583 } while (0)
 584
 585 #define TRACE_FP_INPUT_FPU3(V0, V1, V2) \
 586 do { \
 587   if (TRACE_FPU_P (CPU)) \
 588     { \
 589       unsigned64 f0, f1, f2; \
 590       sim_fpu_to64 (&f0, (V0)); \
 591       sim_fpu_to64 (&f1, (V1)); \
 592       sim_fpu_to64 (&f2, (V2)); \
 593       trace_input_fp3 (SD, CPU, TRACE_FPU_IDX, f0, f1, f2); \
 594     } \
 595 } while (0)
 596
 597 #define TRACE_FP_INPUT_BOOL1_FPU2(V0, V1, V2) \
 598 do { \
 599   if (TRACE_FPU_P (CPU)) \
 600     { \
 601       int d0 = (V0); \
 602       unsigned64 f1, f2; \
 603       TRACE_DATA *data = CPU_TRACE_DATA (CPU); \
 604       TRACE_IDX (data) = TRACE_FPU_IDX; \
 605       sim_fpu_to64 (&f1, (V1)); \
 606       sim_fpu_to64 (&f2, (V2)); \
 607       save_data (SD, data, trace_fmt_bool, sizeof (d0), &d0); \
 608       save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f1); \
 609       save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f2); \
 610     } \
 611 } while (0)
 612
 613 #define TRACE_FP_INPUT_WORD2(V0, V1) \
 614 do { \
 615   if (TRACE_FPU_P (CPU)) \
 616     trace_input_word2 (SD, CPU, TRACE_FPU_IDX, (V0), (V1)); \
 617 } while (0)
 618
 619 #define TRACE_FP_RESULT_FPU1(R0) \
 620 do { \
 621   if (TRACE_FPU_P (CPU)) \
 622     { \
 623       unsigned64 f0; \
 624       sim_fpu_to64 (&f0, (R0)); \
 625       trace_result_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
 626     } \
 627 } while (0)
 628
 629 #define TRACE_FP_RESULT_WORD1(R0) TRACE_FP_RESULT_WORD(R0)
 630
 631 #define TRACE_FP_RESULT_WORD2(R0, R1) \
 632 do { \
 633   if (TRACE_FPU_P (CPU)) \
 634     trace_result_word2 (SD, CPU, TRACE_FPU_IDX, (R0), (R1)); \
 635 } while (0)
 636
 637 #else
 638 #define trace_input(NAME, IN1, IN2)
 639 #define trace_output(RESULT)
 640 #define trace_result(HAS_RESULT, RESULT)
 641
 642 #define TRACE_ALU_INPUT0()
 643 #define TRACE_ALU_INPUT1(IN0)
 644 #define TRACE_ALU_INPUT2(IN0, IN1)
 645 #define TRACE_ALU_INPUT2(IN0, IN1)
 646 #define TRACE_ALU_INPUT2(IN0, IN1 INS2)
 647 #define TRACE_ALU_RESULT(RESULT)
 648
 649 #define TRACE_BRANCH0()
 650 #define TRACE_BRANCH1(IN1)
 651 #define TRACE_BRANCH2(IN1, IN2)
 652 #define TRACE_BRANCH2(IN1, IN2, IN3)
 653
 654 #define TRACE_LD(ADDR,RESULT)
 655 #define TRACE_ST(ADDR,RESULT)
 656
 657 #endif
 658
 659 #define GPR_SET(N, VAL) (State.regs[(N)] = (VAL))
 660 #define GPR_CLEAR(N)    (State.regs[(N)] = 0)
 661
 662 extern void divun ( unsigned int       N,
 663                     unsigned long int  als,
 664                     unsigned long int  sfi,
 665                     unsigned32 /*unsigned long int*/ *  quotient_ptr,
 666                     unsigned32 /*unsigned long int*/ *  remainder_ptr,
 667                     int *overflow_ptr
 668                     );
 669 extern void divn ( unsigned int       N,
 670                    unsigned long int  als,
 671                    unsigned long int  sfi,
 672                    signed32 /*signed long int*/ *  quotient_ptr,
 673                    signed32 /*signed long int*/ *  remainder_ptr,
 674                    int *overflow_ptr
 675                    );
 676 extern int type1_regs[];
 677 extern int type2_regs[];
 678 extern int type3_regs[];
 679
 680 #define SESR_OV   (1 << 0)
 681 #define SESR_SOV  (1 << 1)
 682
 683 #define SESR      (State.sregs[12])
 684
 685 #define ROUND_Q62_Q31(X) ((((X) + (1 << 30)) >> 31) & 0xffffffff)
 686 #define ROUND_Q62_Q15(X) ((((X) + (1 << 30)) >> 47) & 0xffff)
 687 #define ROUND_Q31_Q15(X) ((((X) + (1 << 15)) >> 15) & 0xffff)
 688 #define ROUND_Q30_Q15(X) ((((X) + (1 << 14)) >> 15) & 0xffff)
 689
 690 #define SAT16(X)                        \
 691   do                                    \
 692     {                                   \
 693       signed64 z = (X);                 \
 694       if (z > 0x7fff)                   \
 695         {                               \
 696           SESR |= SESR_OV | SESR_SOV;   \
 697           z = 0x7fff;                   \
 698         }                               \
 699       else if (z < -0x8000)             \
 700         {                               \
 701           SESR |= SESR_OV | SESR_SOV;   \
 702           z = - 0x8000;                 \
 703         }                               \
 704       (X) = z;                          \
 705     }                                   \
 706   while (0)
 707
 708 #define SAT32(X)                        \
 709   do                                    \
 710     {                                   \
 711       signed64 z = (X);                 \
 712       if (z > 0x7fffffff)               \
 713         {                               \
 714           SESR |= SESR_OV | SESR_SOV;   \
 715           z = 0x7fffffff;               \
 716         }                               \
 717       else if (z < -0x80000000)         \
 718         {                               \
 719           SESR |= SESR_OV | SESR_SOV;   \
 720           z = - 0x80000000;             \
 721         }                               \
 722       (X) = z;                          \
 723     }                                   \
 724   while (0)
 725
 726 #define ABS16(X)                        \
 727   do                                    \
 728     {                                   \
 729       signed64 z = (X) & 0xffff;        \
 730       if (z == 0x8000)                  \
 731         {                               \
 732           SESR |= SESR_OV | SESR_SOV;   \
 733           z = 0x7fff;                   \
 734         }                               \
 735       else if (z & 0x8000)              \
 736         {                               \
 737           z = (- z) & 0xffff;           \
 738         }                               \
 739       (X) = z;                          \
 740     }                                   \
 741   while (0)
 742
 743 #define ABS32(X)                        \
 744   do                                    \
 745     {                                   \
 746       signed64 z = (X) & 0xffffffff;    \
 747       if (z == 0x80000000)              \
 748         {                               \
 749           SESR |= SESR_OV | SESR_SOV;   \
 750           z = 0x7fffffff;               \
 751         }                               \
 752       else if (z & 0x80000000)          \
 753         {                               \
 754           z = (- z) & 0xffffffff;       \
 755         }                               \
 756       (X) = z;                          \
 757     }                                   \
 758   while (0)
 759
 760 #endif