sim/v850/sim-main.h

   1 #define WITH_CORE
   2 #define WITH_MODULO_MEMORY 1
   3 #define WITH_WATCHPOINTS 1
   4 #define WITH_TARGET_WORD_MSB 31
   5
   6 #include "sim-basics.h"
   7
   8 #include <signal.h>
   9 typedef address_word sim_cia;
  10
  11
  12 /* This simulator doesn't cache state */
  13 #define SIM_ENGINE_HALT_HOOK(sd,last_cpu,cia) while (0)
  14 #define SIM_ENGINE_RESTART_HOOK(sd,last_cpu,cia) while (0)
  15
  16 /* Get the number of instructions.  FIXME: must be a more elegant way
  17    of doing this.  */
  18 #include "itable.h"
  19 #define MAX_INSNS (nr_itable_entries)
  20 #define INSN_NAME(i) itable[(i)].name
  21
  22 #include "sim-base.h"
  23
  24 #include "simops.h"
  25 #include "bfd.h"
  26
  27
  28 typedef signed8 int8;
  29 typedef unsigned8 uint8;
  30 typedef signed16 int16;
  31 typedef unsigned16 uint16;
  32 typedef signed32 int32;
  33 typedef unsigned32 uint32;
  34 typedef unsigned32 reg_t;
  35
  36
  37 /* The current state of the processor; registers, memory, etc.  */
  38
  39 typedef struct _v850_regs {
  40   reg_t regs[32];               /* general-purpose registers */
  41   reg_t sregs[32];              /* system registers, including psw */
  42   reg_t pc;
  43   int dummy_mem;                /* where invalid accesses go */
  44   int pending_nmi;
  45 } v850_regs;
  46
  47 struct _sim_cpu
  48 {
  49   /* ... simulator specific members ... */
  50   v850_regs reg;
  51   /* ... base type ... */
  52   sim_cpu_base base;
  53 };
  54
  55 #define CPU_CIA(CPU) ((CPU)->reg.pc)
  56
  57 struct sim_state {
  58   sim_cpu cpu[MAX_NR_PROCESSORS];
  59 #if (WITH_SMP)
  60 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
  61 #else
  62 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
  63 #endif
  64 #if 0
  65   SIM_ADDR rom_size;
  66   SIM_ADDR low_end;
  67   SIM_ADDR high_start;
  68   SIM_ADDR high_base;
  69   void *mem;
  70 #endif
  71   sim_state_base base;
  72 };
  73
  74 /* For compatibility, until all functions converted to passing
  75    SIM_DESC as an argument */
  76 extern SIM_DESC simulator;
  77
  78
  79 #define V850_ROM_SIZE 0x8000
  80 #define V850_LOW_END 0x200000
  81 #define V850_HIGH_START 0xffe000
  82
  83
  84 #define SIG_V850_EXIT   -1      /* indication of a normal exit */
  85
  86 extern uint32 OP[4];
  87
  88 /* Because we are still using the old semantic table, provide compat
  89    macro's that store the instruction where the old simops expects
  90    it. */
  91
  92 #if 0
  93 OP[0] = inst & 0x1f;           /* RRRRR -> reg1 */
  94 OP[1] = (inst >> 11) & 0x1f;   /* rrrrr -> reg2 */
  95 OP[2] = (inst >> 16) & 0xffff; /* wwwww -> reg3 */
  96 OP[3] = inst;
  97 #endif
  98
  99 #define COMPAT_1(CALL) \
 100 PC = cia; \
 101 OP[0] = instruction_0 & 0x1f; \
 102 OP[1] = (instruction_0 >> 11) & 0x1f; \
 103 OP[2] = 0; \
 104 OP[3] = instruction_0 ; \
 105 PC += (CALL); \
 106 nia = PC
 107
 108 #define COMPAT_2(CALL) \
 109 PC = cia; \
 110 OP[0] = instruction_0 & 0x1f; \
 111 OP[1] = (instruction_0 >> 11) & 0x1f; \
 112 OP[2] = instruction_1; \
 113 OP[3] = (instruction_1 << 16) | instruction_0; \
 114 PC += (CALL); \
 115 nia = PC
 116
 117
 118 #if 0
 119 extern struct simops Simops[];
 120 #endif
 121
 122 #define State    (STATE_CPU (simulator, 0)->reg)
 123 #define PC      (State.pc)
 124 #define SP      (State.regs[3])
 125 #define EP      (State.regs[30])
 126
 127 #define EIPC  (State.sregs[0])
 128 #define EIPSW (State.sregs[1])
 129 #define FEPC  (State.sregs[2])
 130 #define FEPSW (State.sregs[3])
 131 #define ECR   (State.sregs[4])
 132 #define PSW   (State.sregs[5])
 133 /* start-sanitize-v850e */
 134 #define CTPC  (State.sregs[16])
 135 #define CTPSW (State.sregs[17])
 136 /* end-sanitize-v850e */
 137 #define DBPC  (State.sregs[18])
 138 #define DBPSW (State.sregs[19])
 139 /* start-sanitize-v850e */
 140 #define CTBP  (State.sregs[20])
 141 /* end-sanitize-v850e */
 142
 143 /* start-sanitize-v850eq */
 144 #define PSW_US BIT32 (8)
 145 /* end-sanitize-v850eq */
 146 #define PSW_NP 0x80
 147 #define PSW_EP 0x40
 148 #define PSW_ID 0x20
 149 #define PSW_SAT 0x10
 150 #define PSW_CY 0x8
 151 #define PSW_OV 0x4
 152 #define PSW_S 0x2
 153 #define PSW_Z 0x1
 154
 155 #define SEXT3(x)        ((((x)&0x7)^(~0x3))+0x4)
 156
 157 /* sign-extend a 4-bit number */
 158 #define SEXT4(x)        ((((x)&0xf)^(~0x7))+0x8)
 159
 160 /* sign-extend a 5-bit number */
 161 #define SEXT5(x)        ((((x)&0x1f)^(~0xf))+0x10)
 162
 163 /* sign-extend a 9-bit number */
 164 #define SEXT9(x)        ((((x)&0x1ff)^(~0xff))+0x100)
 165
 166 /* sign-extend a 22-bit number */
 167 #define SEXT22(x)       ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
 168
 169 /* sign extend a 40 bit number */
 170 #define SEXT40(x)       ((((x) & UNSIGNED64 (0xffffffffff)) \
 171                           ^ (~UNSIGNED64 (0x7fffffffff))) \
 172                          + UNSIGNED64 (0x8000000000))
 173
 174 /* sign extend a 44 bit number */
 175 #define SEXT44(x)       ((((x) & UNSIGNED64 (0xfffffffffff)) \
 176                           ^ (~ UNSIGNED64 (0x7ffffffffff))) \
 177                          + UNSIGNED64 (0x80000000000))
 178
 179 /* sign extend a 60 bit number */
 180 #define SEXT60(x)       ((((x) & UNSIGNED64 (0xfffffffffffffff)) \
 181                           ^ (~ UNSIGNED64 (0x7ffffffffffffff))) \
 182                          + UNSIGNED64 (0x800000000000000))
 183
 184 /* No sign extension */
 185 #define NOP(x)          (x)
 186
 187 #define INC_ADDR(x,i)   x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
 188
 189 #define RLW(x) load_mem (x, 4)
 190
 191 #ifdef _WIN32
 192 #ifndef SIGTRAP
 193 #define SIGTRAP 5
 194 #endif
 195 #ifndef SIGQUIT
 196 #define SIGQUIT 3
 197 #endif
 198 #endif
 199
 200 /* Function declarations.  */
 201
 202 #define IMEM(EA) \
 203 sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
 204                          PC, sim_core_execute_map, (EA))
 205
 206 #define IMEM_IMMED(EA,N) \
 207 sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
 208                          PC, sim_core_execute_map, (EA) + (N) * 2)
 209
 210 #define load_mem(ADDR,LEN) \
 211 sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \
 212                                PC, sim_core_read_map, (ADDR))
 213
 214 #define store_mem(ADDR,LEN,DATA) \
 215 sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
 216                                 PC, sim_core_write_map, (ADDR), (DATA))
 217
 218
 219 /* Debug/tracing calls */
 220
 221 enum op_types
 222 {
 223   OP_UNKNOWN,
 224   OP_NONE,
 225   OP_TRAP,
 226   OP_REG,
 227   OP_REG_REG,
 228   OP_REG_REG_CMP,
 229   OP_REG_REG_MOVE,
 230   OP_IMM_REG,
 231   OP_IMM_REG_CMP,
 232   OP_IMM_REG_MOVE,
 233   OP_COND_BR,
 234   OP_LOAD16,
 235   OP_STORE16,
 236   OP_LOAD32,
 237   OP_STORE32,
 238   OP_JUMP,
 239   OP_IMM_REG_REG,
 240   OP_UIMM_REG_REG,
 241   OP_BIT,
 242   OP_EX1,
 243   OP_EX2,
 244   OP_LDSR,
 245   OP_STSR,
 246 /* start-sanitize-v850e */
 247   OP_BIT_CHANGE,
 248   OP_REG_REG_REG,
 249   OP_REG_REG3,
 250 /* end-sanitize-v850e */
 251 /* start-sanitize-v850eq */
 252   OP_IMM_REG_REG_REG,
 253   OP_PUSHPOP1,
 254   OP_PUSHPOP2,
 255   OP_PUSHPOP3,
 256 /* end-sanitize-v850eq */
 257 };
 258
 259 #ifdef DEBUG
 260 void trace_input PARAMS ((char *name, enum op_types type, int size));
 261 void trace_output PARAMS ((enum op_types result));
 262 #else
 263 #define trace_input(NAME, IN1, IN2)
 264 #define trace_output(RESULT)
 265 #endif
 266
 267
 268 /* start-sanitize-v850eq */
 269 extern void divun ( unsigned int       N,
 270                     unsigned long int  als,
 271                     unsigned long int  sfi,
 272                     unsigned long int *  quotient_ptr,
 273                     unsigned long int *  remainder_ptr,
 274                     boolean *          overflow_ptr
 275                     );
 276 extern void divn ( unsigned int       N,
 277                    unsigned long int  als,
 278                    unsigned long int  sfi,
 279                    signed long int *  quotient_ptr,
 280                    signed long int *  remainder_ptr,
 281                    boolean *          overflow_ptr
 282                    );
 283 /* end-sanitize-v850eq */
 284 /* start-sanitize-v850e */
 285 extern int type1_regs[];
 286 extern int type2_regs[];
 287 /* end-sanitize-v850e */
 288 /* start-sanitize-v850eq */
 289 extern int type3_regs[];
 290 /* end-sanitize-v850eq */