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sim: v850: fix SMP compile
[thirdparty/binutils-gdb.git] / sim / v850 / simops.c
1 /* This must come before any other includes. */
2 #include "defs.h"
3
4 #include "sim-main.h"
5 #include "sim-signal.h"
6 #include "v850-sim.h"
7 #include "simops.h"
8
9 #include <sys/types.h>
10
11 #ifdef HAVE_UTIME_H
12 #include <utime.h>
13 #endif
14 #include <time.h>
15 #ifdef HAVE_UNISTD_H
16 #include <unistd.h>
17 #endif
18 #include <stdlib.h>
19 #include <string.h>
20
21 #include "libiberty.h"
22
23 #include <errno.h>
24 #if !defined(__GO32__) && !defined(_WIN32)
25 #include <sys/stat.h>
26 #include <sys/times.h>
27 #include <sys/time.h>
28 #endif
29
30 #include "target-newlib-syscall.h"
31
32 /* This is an array of the bit positions of registers r20 .. r31 in
33 that order in a prepare/dispose instruction. */
34 int type1_regs[12] = { 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 0, 21 };
35 /* This is an array of the bit positions of registers r16 .. r31 in
36 that order in a push/pop instruction. */
37 int type2_regs[16] = { 3, 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
38 /* This is an array of the bit positions of registers r1 .. r15 in
39 that order in a push/pop instruction. */
40 int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
41
42 #if WITH_TRACE_ANY_P
43 #ifndef SIZE_INSTRUCTION
44 #define SIZE_INSTRUCTION 18
45 #endif
46
47 #ifndef SIZE_VALUES
48 #define SIZE_VALUES 11
49 #endif
50
51 /* TODO: This file largely assumes a single CPU. */
52 #define CPU STATE_CPU (sd, 0)
53
54
55 uint32_t trace_values[3];
56 int trace_num_values;
57 uint32_t trace_pc;
58 const char * trace_name;
59 int trace_module;
60
61
62 void
63 trace_input (char *name, enum op_types type, int size)
64 {
65 if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
66 return;
67
68 trace_pc = PC;
69 trace_name = name;
70 trace_module = TRACE_ALU_IDX;
71
72 switch (type)
73 {
74 default:
75 case OP_UNKNOWN:
76 case OP_NONE:
77 case OP_TRAP:
78 trace_num_values = 0;
79 break;
80
81 case OP_REG:
82 case OP_REG_REG_MOVE:
83 trace_values[0] = State.regs[OP[0]];
84 trace_num_values = 1;
85 break;
86
87 case OP_BIT_CHANGE:
88 case OP_REG_REG:
89 case OP_REG_REG_CMP:
90 trace_values[0] = State.regs[OP[1]];
91 trace_values[1] = State.regs[OP[0]];
92 trace_num_values = 2;
93 break;
94
95 case OP_IMM_REG:
96 case OP_IMM_REG_CMP:
97 trace_values[0] = SEXT5 (OP[0]);
98 trace_values[1] = OP[1];
99 trace_num_values = 2;
100 break;
101
102 case OP_IMM_REG_MOVE:
103 trace_values[0] = SEXT5 (OP[0]);
104 trace_num_values = 1;
105 break;
106
107 case OP_COND_BR:
108 trace_values[0] = State.pc;
109 trace_values[1] = SEXT9 (OP[0]);
110 trace_values[2] = PSW;
111 trace_num_values = 3;
112 break;
113
114 case OP_LOAD16:
115 trace_values[0] = OP[1] * size;
116 trace_values[1] = State.regs[30];
117 trace_num_values = 2;
118 break;
119
120 case OP_STORE16:
121 trace_values[0] = State.regs[OP[0]];
122 trace_values[1] = OP[1] * size;
123 trace_values[2] = State.regs[30];
124 trace_num_values = 3;
125 break;
126
127 case OP_LOAD32:
128 trace_values[0] = EXTEND16 (OP[2]);
129 trace_values[1] = State.regs[OP[0]];
130 trace_num_values = 2;
131 break;
132
133 case OP_STORE32:
134 trace_values[0] = State.regs[OP[1]];
135 trace_values[1] = EXTEND16 (OP[2]);
136 trace_values[2] = State.regs[OP[0]];
137 trace_num_values = 3;
138 break;
139
140 case OP_JUMP:
141 trace_values[0] = SEXT22 (OP[0]);
142 trace_values[1] = State.pc;
143 trace_num_values = 2;
144 break;
145
146 case OP_IMM_REG_REG:
147 trace_values[0] = EXTEND16 (OP[0]) << size;
148 trace_values[1] = State.regs[OP[1]];
149 trace_num_values = 2;
150 break;
151
152 case OP_IMM16_REG_REG:
153 trace_values[0] = EXTEND16 (OP[2]) << size;
154 trace_values[1] = State.regs[OP[1]];
155 trace_num_values = 2;
156 break;
157
158 case OP_UIMM_REG_REG:
159 trace_values[0] = (OP[0] & 0xffff) << size;
160 trace_values[1] = State.regs[OP[1]];
161 trace_num_values = 2;
162 break;
163
164 case OP_UIMM16_REG_REG:
165 trace_values[0] = (OP[2]) << size;
166 trace_values[1] = State.regs[OP[1]];
167 trace_num_values = 2;
168 break;
169
170 case OP_BIT:
171 trace_num_values = 0;
172 break;
173
174 case OP_EX1:
175 trace_values[0] = PSW;
176 trace_num_values = 1;
177 break;
178
179 case OP_EX2:
180 trace_num_values = 0;
181 break;
182
183 case OP_LDSR:
184 trace_values[0] = State.regs[OP[0]];
185 trace_num_values = 1;
186 break;
187
188 case OP_STSR:
189 trace_values[0] = State.sregs[OP[1]];
190 trace_num_values = 1;
191 }
192
193 }
194
195 void
196 trace_result (int has_result, uint32_t result)
197 {
198 char buf[1000];
199 char *chp;
200
201 buf[0] = '\0';
202 chp = buf;
203
204 /* write out the values saved during the trace_input call */
205 {
206 int i;
207 for (i = 0; i < trace_num_values; i++)
208 {
209 sprintf (chp, "%*s0x%.8lx", SIZE_VALUES - 10, "",
210 (long) trace_values[i]);
211 chp = strchr (chp, '\0');
212 }
213 while (i++ < 3)
214 {
215 sprintf (chp, "%*s", SIZE_VALUES, "");
216 chp = strchr (chp, '\0');
217 }
218 }
219
220 /* append any result to the end of the buffer */
221 if (has_result)
222 sprintf (chp, " :: 0x%.8lx", (unsigned long) result);
223
224 trace_generic (simulator, STATE_CPU (simulator, 0), trace_module, "%s", buf);
225 }
226
227 void
228 trace_output (enum op_types result)
229 {
230 if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
231 return;
232
233 switch (result)
234 {
235 default:
236 case OP_UNKNOWN:
237 case OP_NONE:
238 case OP_TRAP:
239 case OP_REG:
240 case OP_REG_REG_CMP:
241 case OP_IMM_REG_CMP:
242 case OP_COND_BR:
243 case OP_STORE16:
244 case OP_STORE32:
245 case OP_BIT:
246 case OP_EX2:
247 trace_result (0, 0);
248 break;
249
250 case OP_LOAD16:
251 case OP_STSR:
252 trace_result (1, State.regs[OP[0]]);
253 break;
254
255 case OP_REG_REG:
256 case OP_REG_REG_MOVE:
257 case OP_IMM_REG:
258 case OP_IMM_REG_MOVE:
259 case OP_LOAD32:
260 case OP_EX1:
261 trace_result (1, State.regs[OP[1]]);
262 break;
263
264 case OP_IMM_REG_REG:
265 case OP_UIMM_REG_REG:
266 case OP_IMM16_REG_REG:
267 case OP_UIMM16_REG_REG:
268 trace_result (1, State.regs[OP[1]]);
269 break;
270
271 case OP_JUMP:
272 if (OP[1] != 0)
273 trace_result (1, State.regs[OP[1]]);
274 else
275 trace_result (0, 0);
276 break;
277
278 case OP_LDSR:
279 trace_result (1, State.sregs[OP[1]]);
280 break;
281 }
282 }
283 #endif
284
285 \f
286 /* Returns 1 if the specific condition is met, returns 0 otherwise. */
287 int
288 condition_met (unsigned code)
289 {
290 unsigned int psw = PSW;
291
292 switch (code & 0xf)
293 {
294 case 0x0: return ((psw & PSW_OV) != 0);
295 case 0x1: return ((psw & PSW_CY) != 0);
296 case 0x2: return ((psw & PSW_Z) != 0);
297 case 0x3: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
298 case 0x4: return ((psw & PSW_S) != 0);
299 /*case 0x5: return 1;*/
300 case 0x6: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
301 case 0x7: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) != 0);
302 case 0x8: return ((psw & PSW_OV) == 0);
303 case 0x9: return ((psw & PSW_CY) == 0);
304 case 0xa: return ((psw & PSW_Z) == 0);
305 case 0xb: return ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
306 case 0xc: return ((psw & PSW_S) == 0);
307 case 0xd: return ((psw & PSW_SAT) != 0);
308 case 0xe: return ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
309 case 0xf: return (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) || ((psw & PSW_Z) != 0)) == 0);
310 }
311
312 return 1;
313 }
314
315 unsigned long
316 Add32 (unsigned long a1, unsigned long a2, int * carry)
317 {
318 unsigned long result = (a1 + a2);
319
320 * carry = (result < a1);
321
322 return result;
323 }
324
325 static void
326 Multiply64 (int sign, unsigned long op0)
327 {
328 unsigned long op1;
329 unsigned long lo;
330 unsigned long mid1;
331 unsigned long mid2;
332 unsigned long hi;
333 unsigned long RdLo;
334 unsigned long RdHi;
335 int carry;
336
337 op1 = State.regs[ OP[1] ];
338
339 if (sign)
340 {
341 /* Compute sign of result and adjust operands if necessary. */
342
343 sign = (op0 ^ op1) & 0x80000000;
344
345 if (op0 & 0x80000000)
346 op0 = - op0;
347
348 if (op1 & 0x80000000)
349 op1 = - op1;
350 }
351
352 /* We can split the 32x32 into four 16x16 operations. This ensures
353 that we do not lose precision on 32bit only hosts: */
354 lo = ( (op0 & 0xFFFF) * (op1 & 0xFFFF));
355 mid1 = ( (op0 & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
356 mid2 = (((op0 >> 16) & 0xFFFF) * (op1 & 0xFFFF));
357 hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF));
358
359 /* We now need to add all of these results together, taking care
360 to propogate the carries from the additions: */
361 RdLo = Add32 (lo, (mid1 << 16), & carry);
362 RdHi = carry;
363 RdLo = Add32 (RdLo, (mid2 << 16), & carry);
364 RdHi += (carry + ((mid1 >> 16) & 0xFFFF) + ((mid2 >> 16) & 0xFFFF) + hi);
365
366 if (sign)
367 {
368 /* Negate result if necessary. */
369
370 RdLo = ~ RdLo;
371 RdHi = ~ RdHi;
372 if (RdLo == 0xFFFFFFFF)
373 {
374 RdLo = 0;
375 RdHi += 1;
376 }
377 else
378 RdLo += 1;
379 }
380
381 /* Don't store into register 0. */
382 if (OP[1])
383 State.regs[ OP[1] ] = RdLo;
384 if (OP[2] >> 11)
385 State.regs[ OP[2] >> 11 ] = RdHi;
386
387 return;
388 }
389
390 \f
391 /* Read a null terminated string from memory, return in a buffer. */
392
393 static char *
394 fetch_str (SIM_DESC sd, address_word addr)
395 {
396 char *buf;
397 int nr = 0;
398
399 while (sim_core_read_1 (STATE_CPU (sd, 0),
400 PC, read_map, addr + nr) != 0)
401 nr++;
402
403 buf = NZALLOC (char, nr + 1);
404 sim_read (simulator, addr, buf, nr);
405
406 return buf;
407 }
408
409 /* Read a null terminated argument vector from memory, return in a
410 buffer. */
411
412 static char **
413 fetch_argv (SIM_DESC sd, address_word addr)
414 {
415 int max_nr = 64;
416 int nr = 0;
417 char **buf = xmalloc (max_nr * sizeof (char*));
418
419 while (1)
420 {
421 uint32_t a = sim_core_read_4 (STATE_CPU (sd, 0),
422 PC, read_map, addr + nr * 4);
423 if (a == 0) break;
424 buf[nr] = fetch_str (sd, a);
425 nr ++;
426 if (nr == max_nr - 1)
427 {
428 max_nr += 50;
429 buf = xrealloc (buf, max_nr * sizeof (char*));
430 }
431 }
432 buf[nr] = 0;
433 return buf;
434 }
435
436 \f
437 /* sst.b */
438 int
439 OP_380 (void)
440 {
441 trace_input ("sst.b", OP_STORE16, 1);
442
443 store_mem (State.regs[30] + (OP[3] & 0x7f), 1, State.regs[ OP[1] ]);
444
445 trace_output (OP_STORE16);
446
447 return 2;
448 }
449
450 /* sst.h */
451 int
452 OP_480 (void)
453 {
454 trace_input ("sst.h", OP_STORE16, 2);
455
456 store_mem (State.regs[30] + ((OP[3] & 0x7f) << 1), 2, State.regs[ OP[1] ]);
457
458 trace_output (OP_STORE16);
459
460 return 2;
461 }
462
463 /* sst.w */
464 int
465 OP_501 (void)
466 {
467 trace_input ("sst.w", OP_STORE16, 4);
468
469 store_mem (State.regs[30] + ((OP[3] & 0x7e) << 1), 4, State.regs[ OP[1] ]);
470
471 trace_output (OP_STORE16);
472
473 return 2;
474 }
475
476 /* ld.b */
477 int
478 OP_700 (void)
479 {
480 int adr;
481
482 trace_input ("ld.b", OP_LOAD32, 1);
483
484 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
485
486 State.regs[ OP[1] ] = EXTEND8 (load_mem (adr, 1));
487
488 trace_output (OP_LOAD32);
489
490 return 4;
491 }
492
493 /* ld.h */
494 int
495 OP_720 (void)
496 {
497 int adr;
498
499 trace_input ("ld.h", OP_LOAD32, 2);
500
501 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
502 adr &= ~0x1;
503
504 State.regs[ OP[1] ] = EXTEND16 (load_mem (adr, 2));
505
506 trace_output (OP_LOAD32);
507
508 return 4;
509 }
510
511 /* ld.w */
512 int
513 OP_10720 (void)
514 {
515 int adr;
516
517 trace_input ("ld.w", OP_LOAD32, 4);
518
519 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
520 adr &= ~0x3;
521
522 State.regs[ OP[1] ] = load_mem (adr, 4);
523
524 trace_output (OP_LOAD32);
525
526 return 4;
527 }
528
529 /* st.b */
530 int
531 OP_740 (void)
532 {
533 trace_input ("st.b", OP_STORE32, 1);
534
535 store_mem (State.regs[ OP[0] ] + EXTEND16 (OP[2]), 1, State.regs[ OP[1] ]);
536
537 trace_output (OP_STORE32);
538
539 return 4;
540 }
541
542 /* st.h */
543 int
544 OP_760 (void)
545 {
546 int adr;
547
548 trace_input ("st.h", OP_STORE32, 2);
549
550 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
551 adr &= ~1;
552
553 store_mem (adr, 2, State.regs[ OP[1] ]);
554
555 trace_output (OP_STORE32);
556
557 return 4;
558 }
559
560 /* st.w */
561 int
562 OP_10760 (void)
563 {
564 int adr;
565
566 trace_input ("st.w", OP_STORE32, 4);
567
568 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
569 adr &= ~3;
570
571 store_mem (adr, 4, State.regs[ OP[1] ]);
572
573 trace_output (OP_STORE32);
574
575 return 4;
576 }
577
578 /* add reg, reg */
579 int
580 OP_1C0 (void)
581 {
582 unsigned int op0, op1, result, z, s, cy, ov;
583
584 trace_input ("add", OP_REG_REG, 0);
585
586 /* Compute the result. */
587
588 op0 = State.regs[ OP[0] ];
589 op1 = State.regs[ OP[1] ];
590
591 result = op0 + op1;
592
593 /* Compute the condition codes. */
594 z = (result == 0);
595 s = (result & 0x80000000);
596 cy = (result < op0 || result < op1);
597 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
598 && (op0 & 0x80000000) != (result & 0x80000000));
599
600 /* Store the result and condition codes. */
601 State.regs[OP[1]] = result;
602 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
603 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
604 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
605 trace_output (OP_REG_REG);
606
607 return 2;
608 }
609
610 /* add sign_extend(imm5), reg */
611 int
612 OP_240 (void)
613 {
614 unsigned int op0, op1, result, z, s, cy, ov;
615 int temp;
616
617 trace_input ("add", OP_IMM_REG, 0);
618
619 /* Compute the result. */
620 temp = SEXT5 (OP[0]);
621 op0 = temp;
622 op1 = State.regs[OP[1]];
623 result = op0 + op1;
624
625 /* Compute the condition codes. */
626 z = (result == 0);
627 s = (result & 0x80000000);
628 cy = (result < op0 || result < op1);
629 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
630 && (op0 & 0x80000000) != (result & 0x80000000));
631
632 /* Store the result and condition codes. */
633 State.regs[OP[1]] = result;
634 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
635 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
636 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
637 trace_output (OP_IMM_REG);
638
639 return 2;
640 }
641
642 /* addi sign_extend(imm16), reg, reg */
643 int
644 OP_600 (void)
645 {
646 unsigned int op0, op1, result, z, s, cy, ov;
647
648 trace_input ("addi", OP_IMM16_REG_REG, 0);
649
650 /* Compute the result. */
651
652 op0 = EXTEND16 (OP[2]);
653 op1 = State.regs[ OP[0] ];
654 result = op0 + op1;
655
656 /* Compute the condition codes. */
657 z = (result == 0);
658 s = (result & 0x80000000);
659 cy = (result < op0 || result < op1);
660 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
661 && (op0 & 0x80000000) != (result & 0x80000000));
662
663 /* Store the result and condition codes. */
664 State.regs[OP[1]] = result;
665 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
666 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
667 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
668 trace_output (OP_IMM16_REG_REG);
669
670 return 4;
671 }
672
673 /* sub reg1, reg2 */
674 int
675 OP_1A0 (void)
676 {
677 unsigned int op0, op1, result, z, s, cy, ov;
678
679 trace_input ("sub", OP_REG_REG, 0);
680 /* Compute the result. */
681 op0 = State.regs[ OP[0] ];
682 op1 = State.regs[ OP[1] ];
683 result = op1 - op0;
684
685 /* Compute the condition codes. */
686 z = (result == 0);
687 s = (result & 0x80000000);
688 cy = (op1 < op0);
689 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
690 && (op1 & 0x80000000) != (result & 0x80000000));
691
692 /* Store the result and condition codes. */
693 State.regs[OP[1]] = result;
694 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
695 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
696 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
697 trace_output (OP_REG_REG);
698
699 return 2;
700 }
701
702 /* subr reg1, reg2 */
703 int
704 OP_180 (void)
705 {
706 unsigned int op0, op1, result, z, s, cy, ov;
707
708 trace_input ("subr", OP_REG_REG, 0);
709 /* Compute the result. */
710 op0 = State.regs[ OP[0] ];
711 op1 = State.regs[ OP[1] ];
712 result = op0 - op1;
713
714 /* Compute the condition codes. */
715 z = (result == 0);
716 s = (result & 0x80000000);
717 cy = (op0 < op1);
718 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
719 && (op0 & 0x80000000) != (result & 0x80000000));
720
721 /* Store the result and condition codes. */
722 State.regs[OP[1]] = result;
723 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
724 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
725 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
726 trace_output (OP_REG_REG);
727
728 return 2;
729 }
730
731 /* sxh reg1 */
732 int
733 OP_E0 (void)
734 {
735 trace_input ("mulh", OP_REG_REG, 0);
736
737 State.regs[ OP[1] ] = (EXTEND16 (State.regs[ OP[1] ]) * EXTEND16 (State.regs[ OP[0] ]));
738
739 trace_output (OP_REG_REG);
740
741 return 2;
742 }
743
744 /* mulh sign_extend(imm5), reg2 */
745 int
746 OP_2E0 (void)
747 {
748 trace_input ("mulh", OP_IMM_REG, 0);
749
750 State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[1] ]) * SEXT5 (OP[0]);
751
752 trace_output (OP_IMM_REG);
753
754 return 2;
755 }
756
757 /* mulhi imm16, reg1, reg2 */
758 int
759 OP_6E0 (void)
760 {
761 trace_input ("mulhi", OP_IMM16_REG_REG, 0);
762
763 State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[0] ]) * EXTEND16 (OP[2]);
764
765 trace_output (OP_IMM16_REG_REG);
766
767 return 4;
768 }
769
770 /* cmp reg, reg */
771 int
772 OP_1E0 (void)
773 {
774 unsigned int op0, op1, result, z, s, cy, ov;
775
776 trace_input ("cmp", OP_REG_REG_CMP, 0);
777 /* Compute the result. */
778 op0 = State.regs[ OP[0] ];
779 op1 = State.regs[ OP[1] ];
780 result = op1 - op0;
781
782 /* Compute the condition codes. */
783 z = (result == 0);
784 s = (result & 0x80000000);
785 cy = (op1 < op0);
786 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
787 && (op1 & 0x80000000) != (result & 0x80000000));
788
789 /* Set condition codes. */
790 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
791 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
792 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
793 trace_output (OP_REG_REG_CMP);
794
795 return 2;
796 }
797
798 /* cmp sign_extend(imm5), reg */
799 int
800 OP_260 (void)
801 {
802 unsigned int op0, op1, result, z, s, cy, ov;
803 int temp;
804
805 /* Compute the result. */
806 trace_input ("cmp", OP_IMM_REG_CMP, 0);
807 temp = SEXT5 (OP[0]);
808 op0 = temp;
809 op1 = State.regs[OP[1]];
810 result = op1 - op0;
811
812 /* Compute the condition codes. */
813 z = (result == 0);
814 s = (result & 0x80000000);
815 cy = (op1 < op0);
816 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
817 && (op1 & 0x80000000) != (result & 0x80000000));
818
819 /* Set condition codes. */
820 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
821 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
822 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
823 trace_output (OP_IMM_REG_CMP);
824
825 return 2;
826 }
827
828 /* setf cccc,reg2 */
829 int
830 OP_7E0 (void)
831 {
832 trace_input ("setf", OP_EX1, 0);
833
834 State.regs[ OP[1] ] = condition_met (OP[0]);
835
836 trace_output (OP_EX1);
837
838 return 4;
839 }
840
841 /* satadd reg,reg */
842 int
843 OP_C0 (void)
844 {
845 unsigned int op0, op1, result, z, s, cy, ov, sat;
846
847 trace_input ("satadd", OP_REG_REG, 0);
848 /* Compute the result. */
849 op0 = State.regs[ OP[0] ];
850 op1 = State.regs[ OP[1] ];
851 result = op0 + op1;
852
853 /* Compute the condition codes. */
854 z = (result == 0);
855 s = (result & 0x80000000);
856 cy = (result < op0 || result < op1);
857 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
858 && (op0 & 0x80000000) != (result & 0x80000000));
859 sat = ov;
860
861 /* Handle saturated results. */
862 if (sat && s)
863 {
864 /* An overflow that results in a negative result implies that we
865 became too positive. */
866 result = 0x7fffffff;
867 s = 0;
868 }
869 else if (sat)
870 {
871 /* Any other overflow must have thus been too negative. */
872 result = 0x80000000;
873 s = 1;
874 z = 0;
875 }
876
877 /* Store the result and condition codes. */
878 State.regs[OP[1]] = result;
879 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
880 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
881 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
882 | (sat ? PSW_SAT : 0));
883
884 trace_output (OP_REG_REG);
885
886 return 2;
887 }
888
889 /* satadd sign_extend(imm5), reg */
890 int
891 OP_220 (void)
892 {
893 unsigned int op0, op1, result, z, s, cy, ov, sat;
894
895 int temp;
896
897 trace_input ("satadd", OP_IMM_REG, 0);
898
899 /* Compute the result. */
900 temp = SEXT5 (OP[0]);
901 op0 = temp;
902 op1 = State.regs[OP[1]];
903 result = op0 + op1;
904
905 /* Compute the condition codes. */
906 z = (result == 0);
907 s = (result & 0x80000000);
908 cy = (result < op0 || result < op1);
909 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
910 && (op0 & 0x80000000) != (result & 0x80000000));
911 sat = ov;
912
913 /* Handle saturated results. */
914 if (sat && s)
915 {
916 /* An overflow that results in a negative result implies that we
917 became too positive. */
918 result = 0x7fffffff;
919 s = 0;
920 }
921 else if (sat)
922 {
923 /* Any other overflow must have thus been too negative. */
924 result = 0x80000000;
925 s = 1;
926 z = 0;
927 }
928
929 /* Store the result and condition codes. */
930 State.regs[OP[1]] = result;
931 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
932 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
933 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
934 | (sat ? PSW_SAT : 0));
935 trace_output (OP_IMM_REG);
936
937 return 2;
938 }
939
940 /* satsub reg1, reg2 */
941 int
942 OP_A0 (void)
943 {
944 unsigned int op0, op1, result, z, s, cy, ov, sat;
945
946 trace_input ("satsub", OP_REG_REG, 0);
947
948 /* Compute the result. */
949 op0 = State.regs[ OP[0] ];
950 op1 = State.regs[ OP[1] ];
951 result = op1 - op0;
952
953 /* Compute the condition codes. */
954 z = (result == 0);
955 s = (result & 0x80000000);
956 cy = (op1 < op0);
957 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
958 && (op1 & 0x80000000) != (result & 0x80000000));
959 sat = ov;
960
961 /* Handle saturated results. */
962 if (sat && s)
963 {
964 /* An overflow that results in a negative result implies that we
965 became too positive. */
966 result = 0x7fffffff;
967 s = 0;
968 }
969 else if (sat)
970 {
971 /* Any other overflow must have thus been too negative. */
972 result = 0x80000000;
973 s = 1;
974 z = 0;
975 }
976
977 /* Store the result and condition codes. */
978 State.regs[OP[1]] = result;
979 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
980 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
981 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
982 | (sat ? PSW_SAT : 0));
983
984 trace_output (OP_REG_REG);
985 return 2;
986 }
987
988 /* satsubi sign_extend(imm16), reg */
989 int
990 OP_660 (void)
991 {
992 unsigned int op0, op1, result, z, s, cy, ov, sat;
993 int temp;
994
995 trace_input ("satsubi", OP_IMM_REG, 0);
996
997 /* Compute the result. */
998 temp = EXTEND16 (OP[2]);
999 op0 = temp;
1000 op1 = State.regs[ OP[0] ];
1001 result = op1 - op0;
1002
1003 /* Compute the condition codes. */
1004 z = (result == 0);
1005 s = (result & 0x80000000);
1006 cy = (op1 < op0);
1007 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1008 && (op1 & 0x80000000) != (result & 0x80000000));
1009 sat = ov;
1010
1011 /* Handle saturated results. */
1012 if (sat && s)
1013 {
1014 /* An overflow that results in a negative result implies that we
1015 became too positive. */
1016 result = 0x7fffffff;
1017 s = 0;
1018 }
1019 else if (sat)
1020 {
1021 /* Any other overflow must have thus been too negative. */
1022 result = 0x80000000;
1023 s = 1;
1024 z = 0;
1025 }
1026
1027 /* Store the result and condition codes. */
1028 State.regs[OP[1]] = result;
1029 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1030 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1031 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1032 | (sat ? PSW_SAT : 0));
1033
1034 trace_output (OP_IMM_REG);
1035
1036 return 4;
1037 }
1038
1039 /* satsubr reg,reg */
1040 int
1041 OP_80 (void)
1042 {
1043 unsigned int op0, op1, result, z, s, cy, ov, sat;
1044
1045 trace_input ("satsubr", OP_REG_REG, 0);
1046
1047 /* Compute the result. */
1048 op0 = State.regs[ OP[0] ];
1049 op1 = State.regs[ OP[1] ];
1050 result = op0 - op1;
1051
1052 /* Compute the condition codes. */
1053 z = (result == 0);
1054 s = (result & 0x80000000);
1055 cy = (op0 < op1);
1056 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
1057 && (op0 & 0x80000000) != (result & 0x80000000));
1058 sat = ov;
1059
1060 /* Handle saturated results. */
1061 if (sat && s)
1062 {
1063 /* An overflow that results in a negative result implies that we
1064 became too positive. */
1065 result = 0x7fffffff;
1066 s = 0;
1067 }
1068 else if (sat)
1069 {
1070 /* Any other overflow must have thus been too negative. */
1071 result = 0x80000000;
1072 s = 1;
1073 z = 0;
1074 }
1075
1076 /* Store the result and condition codes. */
1077 State.regs[OP[1]] = result;
1078 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1079 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1080 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1081 | (sat ? PSW_SAT : 0));
1082
1083 trace_output (OP_REG_REG);
1084
1085 return 2;
1086 }
1087
1088 /* tst reg,reg */
1089 int
1090 OP_160 (void)
1091 {
1092 unsigned int op0, op1, result, z, s;
1093
1094 trace_input ("tst", OP_REG_REG_CMP, 0);
1095
1096 /* Compute the result. */
1097 op0 = State.regs[ OP[0] ];
1098 op1 = State.regs[ OP[1] ];
1099 result = op0 & op1;
1100
1101 /* Compute the condition codes. */
1102 z = (result == 0);
1103 s = (result & 0x80000000);
1104
1105 /* Store the condition codes. */
1106 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1107 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1108 trace_output (OP_REG_REG_CMP);
1109
1110 return 2;
1111 }
1112
1113 /* mov sign_extend(imm5), reg */
1114 int
1115 OP_200 (void)
1116 {
1117 int value = SEXT5 (OP[0]);
1118
1119 trace_input ("mov", OP_IMM_REG_MOVE, 0);
1120
1121 State.regs[ OP[1] ] = value;
1122
1123 trace_output (OP_IMM_REG_MOVE);
1124
1125 return 2;
1126 }
1127
1128 /* movhi imm16, reg, reg */
1129 int
1130 OP_640 (void)
1131 {
1132 trace_input ("movhi", OP_UIMM16_REG_REG, 16);
1133
1134 State.regs[ OP[1] ] = State.regs[ OP[0] ] + (OP[2] << 16);
1135
1136 trace_output (OP_UIMM16_REG_REG);
1137
1138 return 4;
1139 }
1140
1141 /* sar zero_extend(imm5),reg1 */
1142 int
1143 OP_2A0 (void)
1144 {
1145 unsigned int op0, op1, result, z, s, cy;
1146
1147 trace_input ("sar", OP_IMM_REG, 0);
1148 op0 = OP[0];
1149 op1 = State.regs[ OP[1] ];
1150 result = (signed)op1 >> op0;
1151
1152 /* Compute the condition codes. */
1153 z = (result == 0);
1154 s = (result & 0x80000000);
1155 cy = op0 ? (op1 & (1 << (op0 - 1))) : 0;
1156
1157 /* Store the result and condition codes. */
1158 State.regs[ OP[1] ] = result;
1159 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1160 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1161 | (cy ? PSW_CY : 0));
1162 trace_output (OP_IMM_REG);
1163
1164 return 2;
1165 }
1166
1167 /* sar reg1, reg2 */
1168 int
1169 OP_A007E0 (void)
1170 {
1171 unsigned int op0, op1, result, z, s, cy;
1172
1173 trace_input ("sar", OP_REG_REG, 0);
1174
1175 op0 = State.regs[ OP[0] ] & 0x1f;
1176 op1 = State.regs[ OP[1] ];
1177 result = (signed)op1 >> op0;
1178
1179 /* Compute the condition codes. */
1180 z = (result == 0);
1181 s = (result & 0x80000000);
1182 cy = op0 ? (op1 & (1 << (op0 - 1))) : 0;
1183
1184 /* Store the result and condition codes. */
1185 State.regs[OP[1]] = result;
1186 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1187 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1188 | (cy ? PSW_CY : 0));
1189 trace_output (OP_REG_REG);
1190
1191 return 4;
1192 }
1193
1194 /* shl zero_extend(imm5),reg1 */
1195 int
1196 OP_2C0 (void)
1197 {
1198 unsigned int op0, op1, result, z, s, cy;
1199
1200 trace_input ("shl", OP_IMM_REG, 0);
1201 op0 = OP[0];
1202 op1 = State.regs[ OP[1] ];
1203 result = op1 << op0;
1204
1205 /* Compute the condition codes. */
1206 z = (result == 0);
1207 s = (result & 0x80000000);
1208 cy = op0 ? (op1 & (1 << (32 - op0))) : 0;
1209
1210 /* Store the result and condition codes. */
1211 State.regs[OP[1]] = result;
1212 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1213 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1214 | (cy ? PSW_CY : 0));
1215 trace_output (OP_IMM_REG);
1216
1217 return 2;
1218 }
1219
1220 /* shl reg1, reg2 */
1221 int
1222 OP_C007E0 (void)
1223 {
1224 unsigned int op0, op1, result, z, s, cy;
1225
1226 trace_input ("shl", OP_REG_REG, 0);
1227 op0 = State.regs[ OP[0] ] & 0x1f;
1228 op1 = State.regs[ OP[1] ];
1229 result = op1 << op0;
1230
1231 /* Compute the condition codes. */
1232 z = (result == 0);
1233 s = (result & 0x80000000);
1234 cy = op0 ? (op1 & (1 << (32 - op0))) : 0;
1235
1236 /* Store the result and condition codes. */
1237 State.regs[OP[1]] = result;
1238 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1239 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1240 | (cy ? PSW_CY : 0));
1241 trace_output (OP_REG_REG);
1242
1243 return 4;
1244 }
1245
1246 /* shr zero_extend(imm5),reg1 */
1247 int
1248 OP_280 (void)
1249 {
1250 unsigned int op0, op1, result, z, s, cy;
1251
1252 trace_input ("shr", OP_IMM_REG, 0);
1253 op0 = OP[0];
1254 op1 = State.regs[ OP[1] ];
1255 result = op1 >> op0;
1256
1257 /* Compute the condition codes. */
1258 z = (result == 0);
1259 s = (result & 0x80000000);
1260 cy = op0 ? (op1 & (1 << (op0 - 1))) : 0;
1261
1262 /* Store the result and condition codes. */
1263 State.regs[OP[1]] = result;
1264 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1265 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1266 | (cy ? PSW_CY : 0));
1267 trace_output (OP_IMM_REG);
1268
1269 return 2;
1270 }
1271
1272 /* shr reg1, reg2 */
1273 int
1274 OP_8007E0 (void)
1275 {
1276 unsigned int op0, op1, result, z, s, cy;
1277
1278 trace_input ("shr", OP_REG_REG, 0);
1279 op0 = State.regs[ OP[0] ] & 0x1f;
1280 op1 = State.regs[ OP[1] ];
1281 result = op1 >> op0;
1282
1283 /* Compute the condition codes. */
1284 z = (result == 0);
1285 s = (result & 0x80000000);
1286 cy = op0 ? (op1 & (1 << (op0 - 1))) : 0;
1287
1288 /* Store the result and condition codes. */
1289 State.regs[OP[1]] = result;
1290 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1291 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1292 | (cy ? PSW_CY : 0));
1293 trace_output (OP_REG_REG);
1294
1295 return 4;
1296 }
1297
1298 /* or reg, reg */
1299 int
1300 OP_100 (void)
1301 {
1302 unsigned int op0, op1, result, z, s;
1303
1304 trace_input ("or", OP_REG_REG, 0);
1305
1306 /* Compute the result. */
1307 op0 = State.regs[ OP[0] ];
1308 op1 = State.regs[ OP[1] ];
1309 result = op0 | op1;
1310
1311 /* Compute the condition codes. */
1312 z = (result == 0);
1313 s = (result & 0x80000000);
1314
1315 /* Store the result and condition codes. */
1316 State.regs[OP[1]] = result;
1317 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1318 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1319 trace_output (OP_REG_REG);
1320
1321 return 2;
1322 }
1323
1324 /* ori zero_extend(imm16), reg, reg */
1325 int
1326 OP_680 (void)
1327 {
1328 unsigned int op0, op1, result, z, s;
1329
1330 trace_input ("ori", OP_UIMM16_REG_REG, 0);
1331 op0 = OP[2];
1332 op1 = State.regs[ OP[0] ];
1333 result = op0 | op1;
1334
1335 /* Compute the condition codes. */
1336 z = (result == 0);
1337 s = (result & 0x80000000);
1338
1339 /* Store the result and condition codes. */
1340 State.regs[OP[1]] = result;
1341 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1342 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1343 trace_output (OP_UIMM16_REG_REG);
1344
1345 return 4;
1346 }
1347
1348 /* and reg, reg */
1349 int
1350 OP_140 (void)
1351 {
1352 unsigned int op0, op1, result, z, s;
1353
1354 trace_input ("and", OP_REG_REG, 0);
1355
1356 /* Compute the result. */
1357 op0 = State.regs[ OP[0] ];
1358 op1 = State.regs[ OP[1] ];
1359 result = op0 & op1;
1360
1361 /* Compute the condition codes. */
1362 z = (result == 0);
1363 s = (result & 0x80000000);
1364
1365 /* Store the result and condition codes. */
1366 State.regs[OP[1]] = result;
1367 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1368 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1369 trace_output (OP_REG_REG);
1370
1371 return 2;
1372 }
1373
1374 /* andi zero_extend(imm16), reg, reg */
1375 int
1376 OP_6C0 (void)
1377 {
1378 unsigned int result, z;
1379
1380 trace_input ("andi", OP_UIMM16_REG_REG, 0);
1381
1382 result = OP[2] & State.regs[ OP[0] ];
1383
1384 /* Compute the condition codes. */
1385 z = (result == 0);
1386
1387 /* Store the result and condition codes. */
1388 State.regs[ OP[1] ] = result;
1389
1390 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1391 PSW |= (z ? PSW_Z : 0);
1392
1393 trace_output (OP_UIMM16_REG_REG);
1394
1395 return 4;
1396 }
1397
1398 /* xor reg, reg */
1399 int
1400 OP_120 (void)
1401 {
1402 unsigned int op0, op1, result, z, s;
1403
1404 trace_input ("xor", OP_REG_REG, 0);
1405
1406 /* Compute the result. */
1407 op0 = State.regs[ OP[0] ];
1408 op1 = State.regs[ OP[1] ];
1409 result = op0 ^ op1;
1410
1411 /* Compute the condition codes. */
1412 z = (result == 0);
1413 s = (result & 0x80000000);
1414
1415 /* Store the result and condition codes. */
1416 State.regs[OP[1]] = result;
1417 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1418 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1419 trace_output (OP_REG_REG);
1420
1421 return 2;
1422 }
1423
1424 /* xori zero_extend(imm16), reg, reg */
1425 int
1426 OP_6A0 (void)
1427 {
1428 unsigned int op0, op1, result, z, s;
1429
1430 trace_input ("xori", OP_UIMM16_REG_REG, 0);
1431 op0 = OP[2];
1432 op1 = State.regs[ OP[0] ];
1433 result = op0 ^ op1;
1434
1435 /* Compute the condition codes. */
1436 z = (result == 0);
1437 s = (result & 0x80000000);
1438
1439 /* Store the result and condition codes. */
1440 State.regs[OP[1]] = result;
1441 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1442 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1443 trace_output (OP_UIMM16_REG_REG);
1444
1445 return 4;
1446 }
1447
1448 /* not reg1, reg2 */
1449 int
1450 OP_20 (void)
1451 {
1452 unsigned int op0, result, z, s;
1453
1454 trace_input ("not", OP_REG_REG_MOVE, 0);
1455 /* Compute the result. */
1456 op0 = State.regs[ OP[0] ];
1457 result = ~op0;
1458
1459 /* Compute the condition codes. */
1460 z = (result == 0);
1461 s = (result & 0x80000000);
1462
1463 /* Store the result and condition codes. */
1464 State.regs[OP[1]] = result;
1465 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1466 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1467 trace_output (OP_REG_REG_MOVE);
1468
1469 return 2;
1470 }
1471
1472 /* set1 */
1473 int
1474 OP_7C0 (void)
1475 {
1476 unsigned int op0, op1, op2;
1477 int temp;
1478
1479 trace_input ("set1", OP_BIT, 0);
1480 op0 = State.regs[ OP[0] ];
1481 op1 = OP[1] & 0x7;
1482 temp = EXTEND16 (OP[2]);
1483 op2 = temp;
1484 temp = load_mem (op0 + op2, 1);
1485 PSW &= ~PSW_Z;
1486 if ((temp & (1 << op1)) == 0)
1487 PSW |= PSW_Z;
1488 temp |= (1 << op1);
1489 store_mem (op0 + op2, 1, temp);
1490 trace_output (OP_BIT);
1491
1492 return 4;
1493 }
1494
1495 /* not1 */
1496 int
1497 OP_47C0 (void)
1498 {
1499 unsigned int op0, op1, op2;
1500 int temp;
1501
1502 trace_input ("not1", OP_BIT, 0);
1503 op0 = State.regs[ OP[0] ];
1504 op1 = OP[1] & 0x7;
1505 temp = EXTEND16 (OP[2]);
1506 op2 = temp;
1507 temp = load_mem (op0 + op2, 1);
1508 PSW &= ~PSW_Z;
1509 if ((temp & (1 << op1)) == 0)
1510 PSW |= PSW_Z;
1511 temp ^= (1 << op1);
1512 store_mem (op0 + op2, 1, temp);
1513 trace_output (OP_BIT);
1514
1515 return 4;
1516 }
1517
1518 /* clr1 */
1519 int
1520 OP_87C0 (void)
1521 {
1522 unsigned int op0, op1, op2;
1523 int temp;
1524
1525 trace_input ("clr1", OP_BIT, 0);
1526 op0 = State.regs[ OP[0] ];
1527 op1 = OP[1] & 0x7;
1528 temp = EXTEND16 (OP[2]);
1529 op2 = temp;
1530 temp = load_mem (op0 + op2, 1);
1531 PSW &= ~PSW_Z;
1532 if ((temp & (1 << op1)) == 0)
1533 PSW |= PSW_Z;
1534 temp &= ~(1 << op1);
1535 store_mem (op0 + op2, 1, temp);
1536 trace_output (OP_BIT);
1537
1538 return 4;
1539 }
1540
1541 /* tst1 */
1542 int
1543 OP_C7C0 (void)
1544 {
1545 unsigned int op0, op1, op2;
1546 int temp;
1547
1548 trace_input ("tst1", OP_BIT, 0);
1549 op0 = State.regs[ OP[0] ];
1550 op1 = OP[1] & 0x7;
1551 temp = EXTEND16 (OP[2]);
1552 op2 = temp;
1553 temp = load_mem (op0 + op2, 1);
1554 PSW &= ~PSW_Z;
1555 if ((temp & (1 << op1)) == 0)
1556 PSW |= PSW_Z;
1557 trace_output (OP_BIT);
1558
1559 return 4;
1560 }
1561
1562 /* di */
1563 int
1564 OP_16007E0 (void)
1565 {
1566 trace_input ("di", OP_NONE, 0);
1567 PSW |= PSW_ID;
1568 trace_output (OP_NONE);
1569
1570 return 4;
1571 }
1572
1573 /* ei */
1574 int
1575 OP_16087E0 (void)
1576 {
1577 trace_input ("ei", OP_NONE, 0);
1578 PSW &= ~PSW_ID;
1579 trace_output (OP_NONE);
1580
1581 return 4;
1582 }
1583
1584 /* halt */
1585 int
1586 OP_12007E0 (void)
1587 {
1588 trace_input ("halt", OP_NONE, 0);
1589 /* FIXME this should put processor into a mode where NMI still handled */
1590 trace_output (OP_NONE);
1591 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1592 sim_stopped, SIM_SIGTRAP);
1593 return 0;
1594 }
1595
1596 /* trap */
1597 int
1598 OP_10007E0 (void)
1599 {
1600 trace_input ("trap", OP_TRAP, 0);
1601 trace_output (OP_TRAP);
1602
1603 /* Trap 31 is used for simulating OS I/O functions */
1604
1605 if (OP[0] == 31)
1606 {
1607 int save_errno = errno;
1608 errno = 0;
1609
1610 /* Registers passed to trap 0 */
1611
1612 #define FUNC State.regs[6] /* function number, return value */
1613 #define PARM1 State.regs[7] /* optional parm 1 */
1614 #define PARM2 State.regs[8] /* optional parm 2 */
1615 #define PARM3 State.regs[9] /* optional parm 3 */
1616
1617 /* Registers set by trap 0 */
1618
1619 #define RETVAL State.regs[10] /* return value */
1620 #define RETERR State.regs[11] /* return error code */
1621
1622 /* Turn a pointer in a register into a pointer into real memory. */
1623
1624 #define MEMPTR(x) (map (x))
1625
1626 RETERR = 0;
1627
1628 switch (FUNC)
1629 {
1630
1631 #ifdef HAVE_FORK
1632 case TARGET_NEWLIB_V850_SYS_fork:
1633 RETVAL = fork ();
1634 RETERR = errno;
1635 break;
1636 #endif
1637
1638 #ifdef HAVE_EXECVE
1639 case TARGET_NEWLIB_V850_SYS_execve:
1640 {
1641 char *path = fetch_str (simulator, PARM1);
1642 char **argv = fetch_argv (simulator, PARM2);
1643 char **envp = fetch_argv (simulator, PARM3);
1644 RETVAL = execve (path, (void *)argv, (void *)envp);
1645 free (path);
1646 freeargv (argv);
1647 freeargv (envp);
1648 RETERR = errno;
1649 break;
1650 }
1651 #endif
1652
1653 #if HAVE_EXECV
1654 case TARGET_NEWLIB_V850_SYS_execv:
1655 {
1656 char *path = fetch_str (simulator, PARM1);
1657 char **argv = fetch_argv (simulator, PARM2);
1658 RETVAL = execv (path, (void *)argv);
1659 free (path);
1660 freeargv (argv);
1661 RETERR = errno;
1662 break;
1663 }
1664 #endif
1665
1666 #if 0
1667 case TARGET_NEWLIB_V850_SYS_pipe:
1668 {
1669 reg_t buf;
1670 int host_fd[2];
1671
1672 buf = PARM1;
1673 RETVAL = pipe (host_fd);
1674 SW (buf, host_fd[0]);
1675 buf += sizeof (uint16_t);
1676 SW (buf, host_fd[1]);
1677 RETERR = errno;
1678 }
1679 break;
1680 #endif
1681
1682 #if 0
1683 case TARGET_NEWLIB_V850_SYS_wait:
1684 {
1685 int status;
1686
1687 RETVAL = wait (&status);
1688 SW (PARM1, status);
1689 RETERR = errno;
1690 }
1691 break;
1692 #endif
1693
1694 case TARGET_NEWLIB_V850_SYS_read:
1695 {
1696 char *buf = zalloc (PARM3);
1697 RETVAL = sim_io_read (simulator, PARM1, buf, PARM3);
1698 sim_write (simulator, PARM2, buf, PARM3);
1699 free (buf);
1700 if ((int) RETVAL < 0)
1701 RETERR = sim_io_get_errno (simulator);
1702 break;
1703 }
1704
1705 case TARGET_NEWLIB_V850_SYS_write:
1706 {
1707 char *buf = zalloc (PARM3);
1708 sim_read (simulator, PARM2, buf, PARM3);
1709 if (PARM1 == 1)
1710 RETVAL = sim_io_write_stdout (simulator, buf, PARM3);
1711 else
1712 RETVAL = sim_io_write (simulator, PARM1, buf, PARM3);
1713 free (buf);
1714 if ((int) RETVAL < 0)
1715 RETERR = sim_io_get_errno (simulator);
1716 break;
1717 }
1718
1719 case TARGET_NEWLIB_V850_SYS_lseek:
1720 RETVAL = sim_io_lseek (simulator, PARM1, PARM2, PARM3);
1721 if ((int) RETVAL < 0)
1722 RETERR = sim_io_get_errno (simulator);
1723 break;
1724
1725 case TARGET_NEWLIB_V850_SYS_close:
1726 RETVAL = sim_io_close (simulator, PARM1);
1727 if ((int) RETVAL < 0)
1728 RETERR = sim_io_get_errno (simulator);
1729 break;
1730
1731 case TARGET_NEWLIB_V850_SYS_open:
1732 {
1733 char *buf = fetch_str (simulator, PARM1);
1734 RETVAL = sim_io_open (simulator, buf, PARM2);
1735 free (buf);
1736 if ((int) RETVAL < 0)
1737 RETERR = sim_io_get_errno (simulator);
1738 break;
1739 }
1740
1741 case TARGET_NEWLIB_V850_SYS_exit:
1742 if ((PARM1 & 0xffff0000) == 0xdead0000 && (PARM1 & 0xffff) != 0)
1743 /* get signal encoded by kill */
1744 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1745 sim_signalled, PARM1 & 0xffff);
1746 else if (PARM1 == 0xdead)
1747 /* old libraries */
1748 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1749 sim_stopped, SIM_SIGABRT);
1750 else
1751 /* PARM1 has exit status */
1752 sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
1753 sim_exited, PARM1);
1754 break;
1755
1756 case TARGET_NEWLIB_V850_SYS_stat: /* added at hmsi */
1757 /* stat system call */
1758 {
1759 struct stat host_stat;
1760 reg_t buf;
1761 char *path = fetch_str (simulator, PARM1);
1762
1763 RETVAL = sim_io_stat (simulator, path, &host_stat);
1764
1765 free (path);
1766 buf = PARM2;
1767
1768 /* Just wild-assed guesses. */
1769 store_mem (buf, 2, host_stat.st_dev);
1770 store_mem (buf + 2, 2, host_stat.st_ino);
1771 store_mem (buf + 4, 4, host_stat.st_mode);
1772 store_mem (buf + 8, 2, host_stat.st_nlink);
1773 store_mem (buf + 10, 2, host_stat.st_uid);
1774 store_mem (buf + 12, 2, host_stat.st_gid);
1775 store_mem (buf + 14, 2, host_stat.st_rdev);
1776 store_mem (buf + 16, 4, host_stat.st_size);
1777 store_mem (buf + 20, 4, host_stat.st_atime);
1778 store_mem (buf + 28, 4, host_stat.st_mtime);
1779 store_mem (buf + 36, 4, host_stat.st_ctime);
1780
1781 if ((int) RETVAL < 0)
1782 RETERR = sim_io_get_errno (simulator);
1783 }
1784 break;
1785
1786 case TARGET_NEWLIB_V850_SYS_fstat:
1787 /* fstat system call */
1788 {
1789 struct stat host_stat;
1790 reg_t buf;
1791
1792 RETVAL = sim_io_fstat (simulator, PARM1, &host_stat);
1793
1794 buf = PARM2;
1795
1796 /* Just wild-assed guesses. */
1797 store_mem (buf, 2, host_stat.st_dev);
1798 store_mem (buf + 2, 2, host_stat.st_ino);
1799 store_mem (buf + 4, 4, host_stat.st_mode);
1800 store_mem (buf + 8, 2, host_stat.st_nlink);
1801 store_mem (buf + 10, 2, host_stat.st_uid);
1802 store_mem (buf + 12, 2, host_stat.st_gid);
1803 store_mem (buf + 14, 2, host_stat.st_rdev);
1804 store_mem (buf + 16, 4, host_stat.st_size);
1805 store_mem (buf + 20, 4, host_stat.st_atime);
1806 store_mem (buf + 28, 4, host_stat.st_mtime);
1807 store_mem (buf + 36, 4, host_stat.st_ctime);
1808
1809 if ((int) RETVAL < 0)
1810 RETERR = sim_io_get_errno (simulator);
1811 }
1812 break;
1813
1814 case TARGET_NEWLIB_V850_SYS_rename:
1815 {
1816 char *oldpath = fetch_str (simulator, PARM1);
1817 char *newpath = fetch_str (simulator, PARM2);
1818 RETVAL = sim_io_rename (simulator, oldpath, newpath);
1819 free (oldpath);
1820 free (newpath);
1821 if ((int) RETVAL < 0)
1822 RETERR = sim_io_get_errno (simulator);
1823 }
1824 break;
1825
1826 case TARGET_NEWLIB_V850_SYS_unlink:
1827 {
1828 char *path = fetch_str (simulator, PARM1);
1829 RETVAL = sim_io_unlink (simulator, path);
1830 free (path);
1831 if ((int) RETVAL < 0)
1832 RETERR = sim_io_get_errno (simulator);
1833 }
1834 break;
1835
1836 case TARGET_NEWLIB_V850_SYS_chown:
1837 {
1838 char *path = fetch_str (simulator, PARM1);
1839 RETVAL = chown (path, PARM2, PARM3);
1840 free (path);
1841 RETERR = errno;
1842 }
1843 break;
1844
1845 #if HAVE_CHMOD
1846 case TARGET_NEWLIB_V850_SYS_chmod:
1847 {
1848 char *path = fetch_str (simulator, PARM1);
1849 RETVAL = chmod (path, PARM2);
1850 free (path);
1851 RETERR = errno;
1852 }
1853 break;
1854 #endif
1855
1856 #if HAVE_TIME
1857 case TARGET_NEWLIB_V850_SYS_time:
1858 {
1859 time_t now;
1860 RETVAL = time (&now);
1861 store_mem (PARM1, 4, now);
1862 RETERR = errno;
1863 }
1864 break;
1865 #endif
1866
1867 #if !defined(__GO32__) && !defined(_WIN32)
1868 case TARGET_NEWLIB_V850_SYS_times:
1869 {
1870 struct tms tms;
1871 RETVAL = times (&tms);
1872 store_mem (PARM1, 4, tms.tms_utime);
1873 store_mem (PARM1 + 4, 4, tms.tms_stime);
1874 store_mem (PARM1 + 8, 4, tms.tms_cutime);
1875 store_mem (PARM1 + 12, 4, tms.tms_cstime);
1876 RETERR = errno;
1877 break;
1878 }
1879 #endif
1880
1881 #if !defined(__GO32__) && !defined(_WIN32)
1882 case TARGET_NEWLIB_V850_SYS_gettimeofday:
1883 {
1884 struct timeval t;
1885 struct timezone tz;
1886 RETVAL = gettimeofday (&t, &tz);
1887 store_mem (PARM1, 4, t.tv_sec);
1888 store_mem (PARM1 + 4, 4, t.tv_usec);
1889 store_mem (PARM2, 4, tz.tz_minuteswest);
1890 store_mem (PARM2 + 4, 4, tz.tz_dsttime);
1891 RETERR = errno;
1892 break;
1893 }
1894 #endif
1895
1896 #if HAVE_UTIME
1897 case TARGET_NEWLIB_V850_SYS_utime:
1898 {
1899 /* Cast the second argument to void *, to avoid type mismatch
1900 if a prototype is present. */
1901 sim_io_error (simulator, "Utime not supported");
1902 /* RETVAL = utime (path, (void *) MEMPTR (PARM2)); */
1903 }
1904 break;
1905 #endif
1906
1907 default:
1908 abort ();
1909 }
1910 errno = save_errno;
1911
1912 return 4;
1913 }
1914 else
1915 { /* Trap 0 -> 30 */
1916 EIPC = PC + 4;
1917 EIPSW = PSW;
1918 /* Mask out EICC */
1919 ECR &= 0xffff0000;
1920 ECR |= 0x40 + OP[0];
1921 /* Flag that we are now doing exception processing. */
1922 PSW |= PSW_EP | PSW_ID;
1923 PC = (OP[0] < 0x10) ? 0x40 : 0x50;
1924
1925 return 0;
1926 }
1927 }
1928
1929 /* tst1 reg2, [reg1] */
1930 int
1931 OP_E607E0 (void)
1932 {
1933 int temp;
1934
1935 trace_input ("tst1", OP_BIT, 1);
1936
1937 temp = load_mem (State.regs[ OP[0] ], 1);
1938
1939 PSW &= ~PSW_Z;
1940 if ((temp & (1 << (State.regs[ OP[1] ] & 0x7))) == 0)
1941 PSW |= PSW_Z;
1942
1943 trace_output (OP_BIT);
1944
1945 return 4;
1946 }
1947
1948 /* mulu reg1, reg2, reg3 */
1949 int
1950 OP_22207E0 (void)
1951 {
1952 trace_input ("mulu", OP_REG_REG_REG, 0);
1953
1954 Multiply64 (0, State.regs[ OP[0] ]);
1955
1956 trace_output (OP_REG_REG_REG);
1957
1958 return 4;
1959 }
1960
1961 #define BIT_CHANGE_OP( name, binop ) \
1962 unsigned int bit; \
1963 unsigned int temp; \
1964 \
1965 trace_input (name, OP_BIT_CHANGE, 0); \
1966 \
1967 bit = 1 << (State.regs[ OP[1] ] & 0x7); \
1968 temp = load_mem (State.regs[ OP[0] ], 1); \
1969 \
1970 PSW &= ~PSW_Z; \
1971 if ((temp & bit) == 0) \
1972 PSW |= PSW_Z; \
1973 temp binop bit; \
1974 \
1975 store_mem (State.regs[ OP[0] ], 1, temp); \
1976 \
1977 trace_output (OP_BIT_CHANGE); \
1978 \
1979 return 4;
1980
1981 /* clr1 reg2, [reg1] */
1982 int
1983 OP_E407E0 (void)
1984 {
1985 BIT_CHANGE_OP ("clr1", &= ~ );
1986 }
1987
1988 /* not1 reg2, [reg1] */
1989 int
1990 OP_E207E0 (void)
1991 {
1992 BIT_CHANGE_OP ("not1", ^= );
1993 }
1994
1995 /* set1 */
1996 int
1997 OP_E007E0 (void)
1998 {
1999 BIT_CHANGE_OP ("set1", |= );
2000 }
2001
2002 /* sasf */
2003 int
2004 OP_20007E0 (void)
2005 {
2006 trace_input ("sasf", OP_EX1, 0);
2007
2008 State.regs[ OP[1] ] = (State.regs[ OP[1] ] << 1) | condition_met (OP[0]);
2009
2010 trace_output (OP_EX1);
2011
2012 return 4;
2013 }
2014
2015 /* This function is courtesy of Sugimoto at NEC, via Seow Tan
2016 (Soew_Tan@el.nec.com) */
2017 void
2018 divun
2019 (
2020 unsigned int N,
2021 unsigned long int als,
2022 unsigned long int sfi,
2023 uint32_t /*unsigned long int*/ * quotient_ptr,
2024 uint32_t /*unsigned long int*/ * remainder_ptr,
2025 int * overflow_ptr
2026 )
2027 {
2028 unsigned long ald = sfi >> (N - 1);
2029 unsigned long alo = als;
2030 unsigned int Q = 1;
2031 unsigned int C;
2032 unsigned int S = 0;
2033 unsigned int i;
2034 unsigned int R1 = 1;
2035 unsigned int DBZ = (als == 0) ? 1 : 0;
2036 unsigned long alt = Q ? ~als : als;
2037
2038 /* 1st Loop */
2039 alo = ald + alt + Q;
2040 C = (((alt >> 31) & (ald >> 31))
2041 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2042 C = C ^ Q;
2043 Q = ~(C ^ S) & 1;
2044 R1 = (alo == 0) ? 0 : (R1 & Q);
2045 if ((S ^ (alo>>31)) && !C)
2046 {
2047 DBZ = 1;
2048 }
2049 S = alo >> 31;
2050 sfi = (sfi << (32-N+1)) | Q;
2051 ald = (alo << 1) | (sfi >> 31);
2052
2053 /* 2nd - N-1th Loop */
2054 for (i = 2; i < N; i++)
2055 {
2056 alt = Q ? ~als : als;
2057 alo = ald + alt + Q;
2058 C = (((alt >> 31) & (ald >> 31))
2059 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2060 C = C ^ Q;
2061 Q = ~(C ^ S) & 1;
2062 R1 = (alo == 0) ? 0 : (R1 & Q);
2063 if ((S ^ (alo>>31)) && !C && !DBZ)
2064 {
2065 DBZ = 1;
2066 }
2067 S = alo >> 31;
2068 sfi = (sfi << 1) | Q;
2069 ald = (alo << 1) | (sfi >> 31);
2070 }
2071
2072 /* Nth Loop */
2073 alt = Q ? ~als : als;
2074 alo = ald + alt + Q;
2075 C = (((alt >> 31) & (ald >> 31))
2076 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2077 C = C ^ Q;
2078 Q = ~(C ^ S) & 1;
2079 R1 = (alo == 0) ? 0 : (R1 & Q);
2080 if ((S ^ (alo>>31)) && !C)
2081 {
2082 DBZ = 1;
2083 }
2084
2085 * quotient_ptr = (sfi << 1) | Q;
2086 * remainder_ptr = Q ? alo : (alo + als);
2087 * overflow_ptr = DBZ | R1;
2088 }
2089
2090 /* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
2091 void
2092 divn
2093 (
2094 unsigned int N,
2095 unsigned long int als,
2096 unsigned long int sfi,
2097 int32_t /*signed long int*/ * quotient_ptr,
2098 int32_t /*signed long int*/ * remainder_ptr,
2099 int * overflow_ptr
2100 )
2101 {
2102 unsigned long ald = (signed long) sfi >> (N - 1);
2103 unsigned long alo = als;
2104 unsigned int SS = als >> 31;
2105 unsigned int SD = sfi >> 31;
2106 unsigned int R1 = 1;
2107 unsigned int OV;
2108 unsigned int DBZ = als == 0 ? 1 : 0;
2109 unsigned int Q = ~(SS ^ SD) & 1;
2110 unsigned int C;
2111 unsigned int S;
2112 unsigned int i;
2113 unsigned long alt = Q ? ~als : als;
2114
2115
2116 /* 1st Loop */
2117
2118 alo = ald + alt + Q;
2119 C = (((alt >> 31) & (ald >> 31))
2120 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2121 Q = C ^ SS;
2122 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2123 S = alo >> 31;
2124 sfi = (sfi << (32-N+1)) | Q;
2125 ald = (alo << 1) | (sfi >> 31);
2126 if ((alo >> 31) ^ (ald >> 31))
2127 {
2128 DBZ = 1;
2129 }
2130
2131 /* 2nd - N-1th Loop */
2132
2133 for (i = 2; i < N; i++)
2134 {
2135 alt = Q ? ~als : als;
2136 alo = ald + alt + Q;
2137 C = (((alt >> 31) & (ald >> 31))
2138 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2139 Q = C ^ SS;
2140 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2141 S = alo >> 31;
2142 sfi = (sfi << 1) | Q;
2143 ald = (alo << 1) | (sfi >> 31);
2144 if ((alo >> 31) ^ (ald >> 31))
2145 {
2146 DBZ = 1;
2147 }
2148 }
2149
2150 /* Nth Loop */
2151 alt = Q ? ~als : als;
2152 alo = ald + alt + Q;
2153 C = (((alt >> 31) & (ald >> 31))
2154 | (((alt >> 31) ^ (ald >> 31)) & (~alo >> 31)));
2155 Q = C ^ SS;
2156 R1 = (alo == 0) ? 0 : (R1 & (Q ^ (SS ^ SD)));
2157 sfi = (sfi << (32-N+1));
2158 ald = alo;
2159
2160 /* End */
2161 if (alo != 0)
2162 {
2163 alt = Q ? ~als : als;
2164 alo = ald + alt + Q;
2165 }
2166 R1 = R1 & ((~alo >> 31) ^ SD);
2167 if ((alo != 0) && ((Q ^ (SS ^ SD)) ^ R1)) alo = ald;
2168 if (N != 32)
2169 ald = sfi = (long) ((sfi >> 1) | (SS ^ SD) << 31) >> (32-N-1) | Q;
2170 else
2171 ald = sfi = sfi | Q;
2172
2173 OV = DBZ | ((alo == 0) ? 0 : R1);
2174
2175 * remainder_ptr = alo;
2176
2177 /* Adj */
2178 if (((alo != 0) && ((SS ^ SD) ^ R1))
2179 || ((alo == 0) && (SS ^ R1)))
2180 alo = ald + 1;
2181 else
2182 alo = ald;
2183
2184 OV = (DBZ | R1) ? OV : ((alo >> 31) & (~ald >> 31));
2185
2186 * quotient_ptr = alo;
2187 * overflow_ptr = OV;
2188 }
2189
2190 /* sdivun imm5, reg1, reg2, reg3 */
2191 int
2192 OP_1C207E0 (void)
2193 {
2194 uint32_t /*unsigned long int*/ quotient;
2195 uint32_t /*unsigned long int*/ remainder;
2196 unsigned long int divide_by;
2197 unsigned long int divide_this;
2198 int overflow = 0;
2199 unsigned int imm5;
2200
2201 trace_input ("sdivun", OP_IMM_REG_REG_REG, 0);
2202
2203 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2204
2205 divide_by = State.regs[ OP[0] ];
2206 divide_this = State.regs[ OP[1] ] << imm5;
2207
2208 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2209
2210 State.regs[ OP[1] ] = quotient;
2211 State.regs[ OP[2] >> 11 ] = remainder;
2212
2213 /* Set condition codes. */
2214 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2215
2216 if (overflow) PSW |= PSW_OV;
2217 if (quotient == 0) PSW |= PSW_Z;
2218 if (quotient & 0x80000000) PSW |= PSW_S;
2219
2220 trace_output (OP_IMM_REG_REG_REG);
2221
2222 return 4;
2223 }
2224
2225 /* sdivn imm5, reg1, reg2, reg3 */
2226 int
2227 OP_1C007E0 (void)
2228 {
2229 int32_t /*signed long int*/ quotient;
2230 int32_t /*signed long int*/ remainder;
2231 signed long int divide_by;
2232 signed long int divide_this;
2233 int overflow = 0;
2234 unsigned int imm5;
2235
2236 trace_input ("sdivn", OP_IMM_REG_REG_REG, 0);
2237
2238 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2239
2240 divide_by = (int32_t) State.regs[ OP[0] ];
2241 divide_this = (int32_t) (State.regs[ OP[1] ] << imm5);
2242
2243 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2244
2245 State.regs[ OP[1] ] = quotient;
2246 State.regs[ OP[2] >> 11 ] = remainder;
2247
2248 /* Set condition codes. */
2249 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2250
2251 if (overflow) PSW |= PSW_OV;
2252 if (quotient == 0) PSW |= PSW_Z;
2253 if (quotient < 0) PSW |= PSW_S;
2254
2255 trace_output (OP_IMM_REG_REG_REG);
2256
2257 return 4;
2258 }
2259
2260 /* sdivhun imm5, reg1, reg2, reg3 */
2261 int
2262 OP_18207E0 (void)
2263 {
2264 uint32_t /*unsigned long int*/ quotient;
2265 uint32_t /*unsigned long int*/ remainder;
2266 unsigned long int divide_by;
2267 unsigned long int divide_this;
2268 int overflow = 0;
2269 unsigned int imm5;
2270
2271 trace_input ("sdivhun", OP_IMM_REG_REG_REG, 0);
2272
2273 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2274
2275 divide_by = State.regs[ OP[0] ] & 0xffff;
2276 divide_this = State.regs[ OP[1] ] << imm5;
2277
2278 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2279
2280 State.regs[ OP[1] ] = quotient;
2281 State.regs[ OP[2] >> 11 ] = remainder;
2282
2283 /* Set condition codes. */
2284 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2285
2286 if (overflow) PSW |= PSW_OV;
2287 if (quotient == 0) PSW |= PSW_Z;
2288 if (quotient & 0x80000000) PSW |= PSW_S;
2289
2290 trace_output (OP_IMM_REG_REG_REG);
2291
2292 return 4;
2293 }
2294
2295 /* sdivhn imm5, reg1, reg2, reg3 */
2296 int
2297 OP_18007E0 (void)
2298 {
2299 int32_t /*signed long int*/ quotient;
2300 int32_t /*signed long int*/ remainder;
2301 signed long int divide_by;
2302 signed long int divide_this;
2303 int overflow = 0;
2304 unsigned int imm5;
2305
2306 trace_input ("sdivhn", OP_IMM_REG_REG_REG, 0);
2307
2308 imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
2309
2310 divide_by = EXTEND16 (State.regs[ OP[0] ]);
2311 divide_this = (int32_t) (State.regs[ OP[1] ] << imm5);
2312
2313 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
2314
2315 State.regs[ OP[1] ] = quotient;
2316 State.regs[ OP[2] >> 11 ] = remainder;
2317
2318 /* Set condition codes. */
2319 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2320
2321 if (overflow) PSW |= PSW_OV;
2322 if (quotient == 0) PSW |= PSW_Z;
2323 if (quotient < 0) PSW |= PSW_S;
2324
2325 trace_output (OP_IMM_REG_REG_REG);
2326
2327 return 4;
2328 }
2329
2330 /* divu reg1, reg2, reg3 */
2331 int
2332 OP_2C207E0 (void)
2333 {
2334 unsigned long int quotient;
2335 unsigned long int remainder;
2336 unsigned long int divide_by;
2337 unsigned long int divide_this;
2338 int overflow = 0;
2339
2340 trace_input ("divu", OP_REG_REG_REG, 0);
2341
2342 /* Compute the result. */
2343
2344 divide_by = State.regs[ OP[0] ];
2345 divide_this = State.regs[ OP[1] ];
2346
2347 if (divide_by == 0)
2348 {
2349 PSW |= PSW_OV;
2350 }
2351 else
2352 {
2353 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2354 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2355
2356 /* Set condition codes. */
2357 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2358
2359 if (overflow) PSW |= PSW_OV;
2360 if (quotient == 0) PSW |= PSW_Z;
2361 if (quotient & 0x80000000) PSW |= PSW_S;
2362 }
2363
2364 trace_output (OP_REG_REG_REG);
2365
2366 return 4;
2367 }
2368
2369 /* div reg1, reg2, reg3 */
2370 int
2371 OP_2C007E0 (void)
2372 {
2373 signed long int quotient;
2374 signed long int remainder;
2375 signed long int divide_by;
2376 signed long int divide_this;
2377
2378 trace_input ("div", OP_REG_REG_REG, 0);
2379
2380 /* Compute the result. */
2381
2382 divide_by = (int32_t) State.regs[ OP[0] ];
2383 divide_this = State.regs[ OP[1] ];
2384
2385 if (divide_by == 0)
2386 {
2387 PSW |= PSW_OV;
2388 }
2389 else if (divide_by == -1 && divide_this == (1L << 31))
2390 {
2391 PSW &= ~PSW_Z;
2392 PSW |= PSW_OV | PSW_S;
2393 State.regs[ OP[1] ] = (1 << 31);
2394 State.regs[ OP[2] >> 11 ] = 0;
2395 }
2396 else
2397 {
2398 divide_this = (int32_t) divide_this;
2399 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2400 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2401
2402 /* Set condition codes. */
2403 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2404
2405 if (quotient == 0) PSW |= PSW_Z;
2406 if (quotient < 0) PSW |= PSW_S;
2407 }
2408
2409 trace_output (OP_REG_REG_REG);
2410
2411 return 4;
2412 }
2413
2414 /* divhu reg1, reg2, reg3 */
2415 int
2416 OP_28207E0 (void)
2417 {
2418 unsigned long int quotient;
2419 unsigned long int remainder;
2420 unsigned long int divide_by;
2421 unsigned long int divide_this;
2422 int overflow = 0;
2423
2424 trace_input ("divhu", OP_REG_REG_REG, 0);
2425
2426 /* Compute the result. */
2427
2428 divide_by = State.regs[ OP[0] ] & 0xffff;
2429 divide_this = State.regs[ OP[1] ];
2430
2431 if (divide_by == 0)
2432 {
2433 PSW |= PSW_OV;
2434 }
2435 else
2436 {
2437 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2438 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2439
2440 /* Set condition codes. */
2441 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2442
2443 if (overflow) PSW |= PSW_OV;
2444 if (quotient == 0) PSW |= PSW_Z;
2445 if (quotient & 0x80000000) PSW |= PSW_S;
2446 }
2447
2448 trace_output (OP_REG_REG_REG);
2449
2450 return 4;
2451 }
2452
2453 /* divh reg1, reg2, reg3 */
2454 int
2455 OP_28007E0 (void)
2456 {
2457 signed long int quotient;
2458 signed long int remainder;
2459 signed long int divide_by;
2460 signed long int divide_this;
2461 int overflow = 0;
2462
2463 trace_input ("divh", OP_REG_REG_REG, 0);
2464
2465 /* Compute the result. */
2466
2467 divide_by = EXTEND16 (State.regs[ OP[0] ]);
2468 divide_this = State.regs[ OP[1] ];
2469
2470 if (divide_by == 0)
2471 {
2472 PSW |= PSW_OV;
2473 }
2474 else if (divide_by == -1 && divide_this == (1L << 31))
2475 {
2476 PSW &= ~PSW_Z;
2477 PSW |= PSW_OV | PSW_S;
2478 State.regs[ OP[1] ] = (1 << 31);
2479 State.regs[ OP[2] >> 11 ] = 0;
2480 }
2481 else
2482 {
2483 divide_this = (int32_t) divide_this;
2484 State.regs[ OP[1] ] = quotient = divide_this / divide_by;
2485 State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
2486
2487 /* Set condition codes. */
2488 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
2489
2490 if (quotient == 0) PSW |= PSW_Z;
2491 if (quotient < 0) PSW |= PSW_S;
2492 }
2493
2494 trace_output (OP_REG_REG_REG);
2495
2496 return 4;
2497 }
2498
2499 /* mulu imm9, reg2, reg3 */
2500 int
2501 OP_24207E0 (void)
2502 {
2503 trace_input ("mulu", OP_IMM_REG_REG, 0);
2504
2505 Multiply64 (0, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
2506
2507 trace_output (OP_IMM_REG_REG);
2508
2509 return 4;
2510 }
2511
2512 /* mul imm9, reg2, reg3 */
2513 int
2514 OP_24007E0 (void)
2515 {
2516 trace_input ("mul", OP_IMM_REG_REG, 0);
2517
2518 Multiply64 (1, SEXT9 ((OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0)));
2519
2520 trace_output (OP_IMM_REG_REG);
2521
2522 return 4;
2523 }
2524
2525 /* ld.hu */
2526 int
2527 OP_107E0 (void)
2528 {
2529 int adr;
2530
2531 trace_input ("ld.hu", OP_LOAD32, 2);
2532
2533 adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
2534 adr &= ~0x1;
2535
2536 State.regs[ OP[1] ] = load_mem (adr, 2);
2537
2538 trace_output (OP_LOAD32);
2539
2540 return 4;
2541 }
2542
2543
2544 /* ld.bu */
2545 int
2546 OP_10780 (void)
2547 {
2548 int adr;
2549
2550 trace_input ("ld.bu", OP_LOAD32, 1);
2551
2552 adr = (State.regs[ OP[0] ]
2553 + (EXTEND16 (OP[2] & ~1) | ((OP[3] >> 5) & 1)));
2554
2555 State.regs[ OP[1] ] = load_mem (adr, 1);
2556
2557 trace_output (OP_LOAD32);
2558
2559 return 4;
2560 }
2561
2562 /* prepare list12, imm5, imm32 */
2563 int
2564 OP_1B0780 (void)
2565 {
2566 int i;
2567
2568 trace_input ("prepare", OP_PUSHPOP1, 0);
2569
2570 /* Store the registers with lower number registers being placed at higher addresses. */
2571 for (i = 0; i < 12; i++)
2572 if ((OP[3] & (1 << type1_regs[ i ])))
2573 {
2574 SP -= 4;
2575 store_mem (SP, 4, State.regs[ 20 + i ]);
2576 }
2577
2578 SP -= (OP[3] & 0x3e) << 1;
2579
2580 EP = load_mem (PC + 4, 4);
2581
2582 trace_output (OP_PUSHPOP1);
2583
2584 return 8;
2585 }
2586
2587 /* prepare list12, imm5, imm16-32 */
2588 int
2589 OP_130780 (void)
2590 {
2591 int i;
2592
2593 trace_input ("prepare", OP_PUSHPOP1, 0);
2594
2595 /* Store the registers with lower number registers being placed at higher addresses. */
2596 for (i = 0; i < 12; i++)
2597 if ((OP[3] & (1 << type1_regs[ i ])))
2598 {
2599 SP -= 4;
2600 store_mem (SP, 4, State.regs[ 20 + i ]);
2601 }
2602
2603 SP -= (OP[3] & 0x3e) << 1;
2604
2605 EP = load_mem (PC + 4, 2) << 16;
2606
2607 trace_output (OP_PUSHPOP1);
2608
2609 return 6;
2610 }
2611
2612 /* prepare list12, imm5, imm16 */
2613 int
2614 OP_B0780 (void)
2615 {
2616 int i;
2617
2618 trace_input ("prepare", OP_PUSHPOP1, 0);
2619
2620 /* Store the registers with lower number registers being placed at higher addresses. */
2621 for (i = 0; i < 12; i++)
2622 if ((OP[3] & (1 << type1_regs[ i ])))
2623 {
2624 SP -= 4;
2625 store_mem (SP, 4, State.regs[ 20 + i ]);
2626 }
2627
2628 SP -= (OP[3] & 0x3e) << 1;
2629
2630 EP = EXTEND16 (load_mem (PC + 4, 2));
2631
2632 trace_output (OP_PUSHPOP1);
2633
2634 return 6;
2635 }
2636
2637 /* prepare list12, imm5, sp */
2638 int
2639 OP_30780 (void)
2640 {
2641 int i;
2642
2643 trace_input ("prepare", OP_PUSHPOP1, 0);
2644
2645 /* Store the registers with lower number registers being placed at higher addresses. */
2646 for (i = 0; i < 12; i++)
2647 if ((OP[3] & (1 << type1_regs[ i ])))
2648 {
2649 SP -= 4;
2650 store_mem (SP, 4, State.regs[ 20 + i ]);
2651 }
2652
2653 SP -= (OP[3] & 0x3e) << 1;
2654
2655 EP = SP;
2656
2657 trace_output (OP_PUSHPOP1);
2658
2659 return 4;
2660 }
2661
2662 /* mul reg1, reg2, reg3 */
2663 int
2664 OP_22007E0 (void)
2665 {
2666 trace_input ("mul", OP_REG_REG_REG, 0);
2667
2668 Multiply64 (1, State.regs[ OP[0] ]);
2669
2670 trace_output (OP_REG_REG_REG);
2671
2672 return 4;
2673 }
2674
2675 /* popmh list18 */
2676 int
2677 OP_307F0 (void)
2678 {
2679 int i;
2680
2681 trace_input ("popmh", OP_PUSHPOP2, 0);
2682
2683 if (OP[3] & (1 << 19))
2684 {
2685 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2686 {
2687 FEPSW = load_mem ( SP & ~ 3, 4);
2688 FEPC = load_mem ((SP + 4) & ~ 3, 4);
2689 }
2690 else
2691 {
2692 EIPSW = load_mem ( SP & ~ 3, 4);
2693 EIPC = load_mem ((SP + 4) & ~ 3, 4);
2694 }
2695
2696 SP += 8;
2697 }
2698
2699 /* Load the registers with lower number registers being retrieved from higher addresses. */
2700 for (i = 16; i--;)
2701 if ((OP[3] & (1 << type2_regs[ i ])))
2702 {
2703 State.regs[ i + 16 ] = load_mem (SP & ~ 3, 4);
2704 SP += 4;
2705 }
2706
2707 trace_output (OP_PUSHPOP2);
2708
2709 return 4;
2710 }
2711
2712 /* popml lsit18 */
2713 int
2714 OP_107F0 (void)
2715 {
2716 int i;
2717
2718 trace_input ("popml", OP_PUSHPOP3, 0);
2719
2720 if (OP[3] & (1 << 19))
2721 {
2722 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2723 {
2724 FEPSW = load_mem ( SP & ~ 3, 4);
2725 FEPC = load_mem ((SP + 4) & ~ 3, 4);
2726 }
2727 else
2728 {
2729 EIPSW = load_mem ( SP & ~ 3, 4);
2730 EIPC = load_mem ((SP + 4) & ~ 3, 4);
2731 }
2732
2733 SP += 8;
2734 }
2735
2736 if (OP[3] & (1 << 3))
2737 {
2738 PSW = load_mem (SP & ~ 3, 4);
2739 SP += 4;
2740 }
2741
2742 /* Load the registers with lower number registers being retrieved from higher addresses. */
2743 for (i = 15; i--;)
2744 if ((OP[3] & (1 << type3_regs[ i ])))
2745 {
2746 State.regs[ i + 1 ] = load_mem (SP & ~ 3, 4);
2747 SP += 4;
2748 }
2749
2750 trace_output (OP_PUSHPOP2);
2751
2752 return 4;
2753 }
2754
2755 /* pushmh list18 */
2756 int
2757 OP_307E0 (void)
2758 {
2759 int i;
2760
2761 trace_input ("pushmh", OP_PUSHPOP2, 0);
2762
2763 /* Store the registers with lower number registers being placed at higher addresses. */
2764 for (i = 0; i < 16; i++)
2765 if ((OP[3] & (1 << type2_regs[ i ])))
2766 {
2767 SP -= 4;
2768 store_mem (SP & ~ 3, 4, State.regs[ i + 16 ]);
2769 }
2770
2771 if (OP[3] & (1 << 19))
2772 {
2773 SP -= 8;
2774
2775 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
2776 {
2777 store_mem ((SP + 4) & ~ 3, 4, FEPC);
2778 store_mem ( SP & ~ 3, 4, FEPSW);
2779 }
2780 else
2781 {
2782 store_mem ((SP + 4) & ~ 3, 4, EIPC);
2783 store_mem ( SP & ~ 3, 4, EIPSW);
2784 }
2785 }
2786
2787 trace_output (OP_PUSHPOP2);
2788
2789 return 4;
2790 }
2791
2792 /* V850E2R FPU functions */
2793 /*
2794 sim_fpu_status_invalid_snan = 1, -V--- (sim spec.)
2795 sim_fpu_status_invalid_qnan = 2, ----- (sim spec.)
2796 sim_fpu_status_invalid_isi = 4, (inf - inf) -V---
2797 sim_fpu_status_invalid_idi = 8, (inf / inf) -V---
2798 sim_fpu_status_invalid_zdz = 16, (0 / 0) -V---
2799 sim_fpu_status_invalid_imz = 32, (inf * 0) -V---
2800 sim_fpu_status_invalid_cvi = 64, convert to integer -V---
2801 sim_fpu_status_invalid_div0 = 128, (X / 0) --Z--
2802 sim_fpu_status_invalid_cmp = 256, compare ----- (sim spec.)
2803 sim_fpu_status_invalid_sqrt = 512, -V---
2804 sim_fpu_status_rounded = 1024, I----
2805 sim_fpu_status_inexact = 2048, I---- (sim spec.)
2806 sim_fpu_status_overflow = 4096, I--O-
2807 sim_fpu_status_underflow = 8192, I---U
2808 sim_fpu_status_denorm = 16384, ----U (sim spec.)
2809 */
2810
2811 void
2812 update_fpsr (SIM_DESC sd, sim_fpu_status status, unsigned int mask, unsigned int double_op_p)
2813 {
2814 unsigned int fpsr = FPSR & mask;
2815
2816 unsigned int flags = 0;
2817
2818 if (fpsr & FPSR_XEI
2819 && ((status & (sim_fpu_status_rounded
2820 | sim_fpu_status_overflow
2821 | sim_fpu_status_inexact))
2822 || (status & sim_fpu_status_underflow
2823 && (fpsr & (FPSR_XEU | FPSR_XEI)) == 0
2824 && fpsr & FPSR_FS)))
2825 {
2826 flags |= FPSR_XCI | FPSR_XPI;
2827 }
2828
2829 if (fpsr & FPSR_XEV
2830 && (status & (sim_fpu_status_invalid_isi
2831 | sim_fpu_status_invalid_imz
2832 | sim_fpu_status_invalid_zdz
2833 | sim_fpu_status_invalid_idi
2834 | sim_fpu_status_invalid_cvi
2835 | sim_fpu_status_invalid_sqrt
2836 | sim_fpu_status_invalid_snan)))
2837 {
2838 flags |= FPSR_XCV | FPSR_XPV;
2839 }
2840
2841 if (fpsr & FPSR_XEZ
2842 && (status & sim_fpu_status_invalid_div0))
2843 {
2844 flags |= FPSR_XCV | FPSR_XPV;
2845 }
2846
2847 if (fpsr & FPSR_XEO
2848 && (status & sim_fpu_status_overflow))
2849 {
2850 flags |= FPSR_XCO | FPSR_XPO;
2851 }
2852
2853 if (((fpsr & FPSR_XEU) || (fpsr & FPSR_FS) == 0)
2854 && (status & (sim_fpu_status_underflow
2855 | sim_fpu_status_denorm)))
2856 {
2857 flags |= FPSR_XCU | FPSR_XPU;
2858 }
2859
2860 if (flags)
2861 {
2862 FPSR &= ~FPSR_XC;
2863 FPSR |= flags;
2864
2865 SignalExceptionFPE (sd, double_op_p);
2866 }
2867 }
2868
2869 /* Exception. */
2870
2871 void
2872 SignalException (SIM_DESC sd)
2873 {
2874 if (MPM & MPM_AUE)
2875 {
2876 PSW = PSW & ~(PSW_NPV | PSW_DMP | PSW_IMP);
2877 }
2878 }
2879
2880 void
2881 SignalExceptionFPE (SIM_DESC sd, unsigned int double_op_p)
2882 {
2883 if (((PSW & (PSW_NP|PSW_ID)) == 0)
2884 || !(FPSR & (double_op_p ? FPSR_DEM : FPSR_SEM)))
2885 {
2886 EIPC = PC;
2887 EIPSW = PSW;
2888 EIIC = (FPSR & (double_op_p ? FPSR_DEM : FPSR_SEM))
2889 ? 0x71 : 0x72;
2890 PSW |= (PSW_EP | PSW_ID);
2891 PC = 0x70;
2892
2893 SignalException (sd);
2894 }
2895 }
2896
2897 void
2898 check_invalid_snan (SIM_DESC sd, sim_fpu_status status, unsigned int double_op_p)
2899 {
2900 if ((FPSR & FPSR_XEI)
2901 && (status & sim_fpu_status_invalid_snan))
2902 {
2903 FPSR &= ~FPSR_XC;
2904 FPSR |= FPSR_XCV;
2905 FPSR |= FPSR_XPV;
2906 SignalExceptionFPE (sd, double_op_p);
2907 }
2908 }
2909
2910 int
2911 v850_float_compare (SIM_DESC sd, int cmp, sim_fpu wop1, sim_fpu wop2, int double_op_p)
2912 {
2913 int result = -1;
2914
2915 if (sim_fpu_is_nan (&wop1) || sim_fpu_is_nan (&wop2))
2916 {
2917 if (cmp & 0x8)
2918 {
2919 if (FPSR & FPSR_XEV)
2920 {
2921 FPSR |= FPSR_XCV | FPSR_XPV;
2922 SignalExceptionFPE (sd, double_op_p);
2923 }
2924 }
2925
2926 switch (cmp)
2927 {
2928 case FPU_CMP_F:
2929 result = 0;
2930 break;
2931 case FPU_CMP_UN:
2932 result = 1;
2933 break;
2934 case FPU_CMP_EQ:
2935 result = 0;
2936 break;
2937 case FPU_CMP_UEQ:
2938 result = 1;
2939 break;
2940 case FPU_CMP_OLT:
2941 result = 0;
2942 break;
2943 case FPU_CMP_ULT:
2944 result = 1;
2945 break;
2946 case FPU_CMP_OLE:
2947 result = 0;
2948 break;
2949 case FPU_CMP_ULE:
2950 result = 1;
2951 break;
2952 case FPU_CMP_SF:
2953 result = 0;
2954 break;
2955 case FPU_CMP_NGLE:
2956 result = 1;
2957 break;
2958 case FPU_CMP_SEQ:
2959 result = 0;
2960 break;
2961 case FPU_CMP_NGL:
2962 result = 1;
2963 break;
2964 case FPU_CMP_LT:
2965 result = 0;
2966 break;
2967 case FPU_CMP_NGE:
2968 result = 1;
2969 break;
2970 case FPU_CMP_LE:
2971 result = 0;
2972 break;
2973 case FPU_CMP_NGT:
2974 result = 1;
2975 break;
2976 default:
2977 abort ();
2978 }
2979 }
2980 else if (sim_fpu_is_infinity (&wop1) && sim_fpu_is_infinity (&wop2)
2981 && sim_fpu_sign (&wop1) == sim_fpu_sign (&wop2))
2982 {
2983 switch (cmp)
2984 {
2985 case FPU_CMP_F:
2986 result = 0;
2987 break;
2988 case FPU_CMP_UN:
2989 result = 0;
2990 break;
2991 case FPU_CMP_EQ:
2992 result = 1;
2993 break;
2994 case FPU_CMP_UEQ:
2995 result = 1;
2996 break;
2997 case FPU_CMP_OLT:
2998 result = 0;
2999 break;
3000 case FPU_CMP_ULT:
3001 result = 0;
3002 break;
3003 case FPU_CMP_OLE:
3004 result = 1;
3005 break;
3006 case FPU_CMP_ULE:
3007 result = 1;
3008 break;
3009 case FPU_CMP_SF:
3010 result = 0;
3011 break;
3012 case FPU_CMP_NGLE:
3013 result = 0;
3014 break;
3015 case FPU_CMP_SEQ:
3016 result = 1;
3017 break;
3018 case FPU_CMP_NGL:
3019 result = 1;
3020 break;
3021 case FPU_CMP_LT:
3022 result = 0;
3023 break;
3024 case FPU_CMP_NGE:
3025 result = 0;
3026 break;
3027 case FPU_CMP_LE:
3028 result = 1;
3029 break;
3030 case FPU_CMP_NGT:
3031 result = 1;
3032 break;
3033 default:
3034 abort ();
3035 }
3036 }
3037 else
3038 {
3039 int gt = 0,lt = 0,eq = 0, status;
3040
3041 status = sim_fpu_cmp (&wop1, &wop2);
3042
3043 switch (status)
3044 {
3045 case SIM_FPU_IS_SNAN:
3046 case SIM_FPU_IS_QNAN:
3047 abort ();
3048 break;
3049
3050 case SIM_FPU_IS_NINF:
3051 lt = 1;
3052 break;
3053 case SIM_FPU_IS_PINF:
3054 gt = 1;
3055 break;
3056 case SIM_FPU_IS_NNUMBER:
3057 lt = 1;
3058 break;
3059 case SIM_FPU_IS_PNUMBER:
3060 gt = 1;
3061 break;
3062 case SIM_FPU_IS_NDENORM:
3063 lt = 1;
3064 break;
3065 case SIM_FPU_IS_PDENORM:
3066 gt = 1;
3067 break;
3068 case SIM_FPU_IS_NZERO:
3069 case SIM_FPU_IS_PZERO:
3070 eq = 1;
3071 break;
3072 }
3073
3074 switch (cmp)
3075 {
3076 case FPU_CMP_F:
3077 result = 0;
3078 break;
3079 case FPU_CMP_UN:
3080 result = 0;
3081 break;
3082 case FPU_CMP_EQ:
3083 result = eq;
3084 break;
3085 case FPU_CMP_UEQ:
3086 result = eq;
3087 break;
3088 case FPU_CMP_OLT:
3089 result = lt;
3090 break;
3091 case FPU_CMP_ULT:
3092 result = lt;
3093 break;
3094 case FPU_CMP_OLE:
3095 result = lt || eq;
3096 break;
3097 case FPU_CMP_ULE:
3098 result = lt || eq;
3099 break;
3100 case FPU_CMP_SF:
3101 result = 0;
3102 break;
3103 case FPU_CMP_NGLE:
3104 result = 0;
3105 break;
3106 case FPU_CMP_SEQ:
3107 result = eq;
3108 break;
3109 case FPU_CMP_NGL:
3110 result = eq;
3111 break;
3112 case FPU_CMP_LT:
3113 result = lt;
3114 break;
3115 case FPU_CMP_NGE:
3116 result = lt;
3117 break;
3118 case FPU_CMP_LE:
3119 result = lt || eq;
3120 break;
3121 case FPU_CMP_NGT:
3122 result = lt || eq;
3123 break;
3124 }
3125 }
3126
3127 ASSERT (result != -1);
3128 return result;
3129 }
3130
3131 void
3132 v850_div (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p, unsigned int *op3p)
3133 {
3134 signed long int quotient;
3135 signed long int remainder;
3136 signed long int divide_by;
3137 signed long int divide_this;
3138 bfd_boolean overflow = FALSE;
3139
3140 /* Compute the result. */
3141 divide_by = (int32_t)op0;
3142 divide_this = (int32_t)op1;
3143
3144 if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
3145 {
3146 overflow = TRUE;
3147 divide_by = 1;
3148 }
3149
3150 quotient = divide_this / divide_by;
3151 remainder = divide_this % divide_by;
3152
3153 /* Set condition codes. */
3154 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3155
3156 if (overflow) PSW |= PSW_OV;
3157 if (quotient == 0) PSW |= PSW_Z;
3158 if (quotient < 0) PSW |= PSW_S;
3159
3160 *op2p = quotient;
3161 *op3p = remainder;
3162 }
3163
3164 void
3165 v850_divu (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p, unsigned int *op3p)
3166 {
3167 unsigned long int quotient;
3168 unsigned long int remainder;
3169 unsigned long int divide_by;
3170 unsigned long int divide_this;
3171 bfd_boolean overflow = FALSE;
3172
3173 /* Compute the result. */
3174
3175 divide_by = op0;
3176 divide_this = op1;
3177
3178 if (divide_by == 0)
3179 {
3180 overflow = TRUE;
3181 divide_by = 1;
3182 }
3183
3184 quotient = divide_this / divide_by;
3185 remainder = divide_this % divide_by;
3186
3187 /* Set condition codes. */
3188 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
3189
3190 if (overflow) PSW |= PSW_OV;
3191 if (quotient == 0) PSW |= PSW_Z;
3192 if (quotient & 0x80000000) PSW |= PSW_S;
3193
3194 *op2p = quotient;
3195 *op3p = remainder;
3196 }
3197
3198 void
3199 v850_sar (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
3200 {
3201 unsigned int result, z, s, cy;
3202
3203 op0 &= 0x1f;
3204 result = (signed)op1 >> op0;
3205
3206 /* Compute the condition codes. */
3207 z = (result == 0);
3208 s = (result & 0x80000000);
3209 cy = (op1 & (1 << (op0 - 1)));
3210
3211 /* Store the result and condition codes. */
3212 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
3213 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3214 | (cy ? PSW_CY : 0));
3215
3216 *op2p = result;
3217 }
3218
3219 void
3220 v850_shl (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
3221 {
3222 unsigned int result, z, s, cy;
3223
3224 op0 &= 0x1f;
3225 result = op1 << op0;
3226
3227 /* Compute the condition codes. */
3228 z = (result == 0);
3229 s = (result & 0x80000000);
3230 cy = (op1 & (1 << (32 - op0)));
3231
3232 /* Store the result and condition codes. */
3233 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
3234 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3235 | (cy ? PSW_CY : 0));
3236
3237 *op2p = result;
3238 }
3239
3240 void
3241 v850_rotl (SIM_DESC sd, unsigned int amount, unsigned int src, unsigned int * dest)
3242 {
3243 unsigned int result, z, s, cy;
3244
3245 amount &= 0x1f;
3246 result = src << amount;
3247 result |= src >> (32 - amount);
3248
3249 /* Compute the condition codes. */
3250 z = (result == 0);
3251 s = (result & 0x80000000);
3252 cy = ! (result & 1);
3253
3254 /* Store the result and condition codes. */
3255 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
3256 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3257 | (cy ? PSW_CY : 0));
3258
3259 * dest = result;
3260 }
3261
3262 void
3263 v850_bins (SIM_DESC sd, unsigned int source, unsigned int lsb, unsigned int msb,
3264 unsigned int * dest)
3265 {
3266 unsigned int mask;
3267 unsigned int result, pos, width;
3268 unsigned int z, s;
3269
3270 pos = lsb;
3271 width = (msb - lsb) + 1;
3272
3273 /* A width of 32 exhibits undefined behavior on the shift. The easiest
3274 way to make this code safe is to just avoid that case and set the mask
3275 to the right value. */
3276 if (width >= 32)
3277 mask = 0xffffffff;
3278 else
3279 mask = ~ (-(1 << width));
3280
3281 source &= mask;
3282 mask <<= pos;
3283 result = (* dest) & ~ mask;
3284 result |= source << pos;
3285
3286 /* Compute the condition codes. */
3287 z = (result == 0);
3288 s = result & 0x80000000;
3289
3290 /* Store the result and condition codes. */
3291 PSW &= ~(PSW_Z | PSW_S | PSW_OV );
3292 PSW |= (z ? PSW_Z : 0) | (s ? PSW_S : 0);
3293
3294 * dest = result;
3295 }
3296
3297 void
3298 v850_shr (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
3299 {
3300 unsigned int result, z, s, cy;
3301
3302 op0 &= 0x1f;
3303 result = op1 >> op0;
3304
3305 /* Compute the condition codes. */
3306 z = (result == 0);
3307 s = (result & 0x80000000);
3308 cy = (op1 & (1 << (op0 - 1)));
3309
3310 /* Store the result and condition codes. */
3311 PSW &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
3312 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3313 | (cy ? PSW_CY : 0));
3314
3315 *op2p = result;
3316 }
3317
3318 void
3319 v850_satadd (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
3320 {
3321 unsigned int result, z, s, cy, ov, sat;
3322
3323 result = op0 + op1;
3324
3325 /* Compute the condition codes. */
3326 z = (result == 0);
3327 s = (result & 0x80000000);
3328 cy = (result < op0 || result < op1);
3329 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
3330 && (op0 & 0x80000000) != (result & 0x80000000));
3331 sat = ov;
3332
3333 /* Store the result and condition codes. */
3334 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
3335 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3336 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
3337 | (sat ? PSW_SAT : 0));
3338
3339 /* Handle saturated results. */
3340 if (sat && s)
3341 {
3342 result = 0x7fffffff;
3343 PSW &= ~PSW_S;
3344 }
3345 else if (sat)
3346 {
3347 result = 0x80000000;
3348 PSW |= PSW_S;
3349 }
3350
3351 *op2p = result;
3352 }
3353
3354 void
3355 v850_satsub (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
3356 {
3357 unsigned int result, z, s, cy, ov, sat;
3358
3359 /* Compute the result. */
3360 result = op1 - op0;
3361
3362 /* Compute the condition codes. */
3363 z = (result == 0);
3364 s = (result & 0x80000000);
3365 cy = (op1 < op0);
3366 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
3367 && (op1 & 0x80000000) != (result & 0x80000000));
3368 sat = ov;
3369
3370 /* Store the result and condition codes. */
3371 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
3372 PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
3373 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
3374 | (sat ? PSW_SAT : 0));
3375
3376 /* Handle saturated results. */
3377 if (sat && s)
3378 {
3379 result = 0x7fffffff;
3380 PSW &= ~PSW_S;
3381 }
3382 else if (sat)
3383 {
3384 result = 0x80000000;
3385 PSW |= PSW_S;
3386 }
3387
3388 *op2p = result;
3389 }
3390
3391 uint32_t
3392 load_data_mem (SIM_DESC sd,
3393 address_word addr,
3394 int len)
3395 {
3396 uint32_t data;
3397
3398 switch (len)
3399 {
3400 case 1:
3401 data = sim_core_read_unaligned_1 (STATE_CPU (sd, 0),
3402 PC, read_map, addr);
3403 break;
3404 case 2:
3405 data = sim_core_read_unaligned_2 (STATE_CPU (sd, 0),
3406 PC, read_map, addr);
3407 break;
3408 case 4:
3409 data = sim_core_read_unaligned_4 (STATE_CPU (sd, 0),
3410 PC, read_map, addr);
3411 break;
3412 default:
3413 abort ();
3414 }
3415 return data;
3416 }
3417
3418 void
3419 store_data_mem (SIM_DESC sd,
3420 address_word addr,
3421 int len,
3422 uint32_t data)
3423 {
3424 switch (len)
3425 {
3426 case 1:
3427 store_mem (addr, 1, data);
3428 break;
3429 case 2:
3430 store_mem (addr, 2, data);
3431 break;
3432 case 4:
3433 store_mem (addr, 4, data);
3434 break;
3435 default:
3436 abort ();
3437 }
3438 }
3439
3440 int
3441 mpu_load_mem_test (SIM_DESC sd, unsigned int addr, int size, int base_reg)
3442 {
3443 int result = 1;
3444
3445 if (PSW & PSW_DMP)
3446 {
3447 if (IPE0 && addr >= IPA2ADDR (IPA0L) && addr <= IPA2ADDR (IPA0L) && IPR0)
3448 {
3449 /* text area */
3450 }
3451 else if (IPE1 && addr >= IPA2ADDR (IPA1L) && addr <= IPA2ADDR (IPA1L) && IPR1)
3452 {
3453 /* text area */
3454 }
3455 else if (IPE2 && addr >= IPA2ADDR (IPA2L) && addr <= IPA2ADDR (IPA2L) && IPR2)
3456 {
3457 /* text area */
3458 }
3459 else if (IPE3 && addr >= IPA2ADDR (IPA3L) && addr <= IPA2ADDR (IPA3L) && IPR3)
3460 {
3461 /* text area */
3462 }
3463 else if (addr >= PPA2ADDR (PPA & ~PPM) && addr <= DPA2ADDR (PPA | PPM))
3464 {
3465 /* preifarallel area */
3466 }
3467 else if (addr >= PPA2ADDR (SPAL) && addr <= DPA2ADDR (SPAU))
3468 {
3469 /* stack area */
3470 }
3471 else if (DPE0 && addr >= DPA2ADDR (DPA0L) && addr <= DPA2ADDR (DPA0L) && DPR0
3472 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3473 {
3474 /* data area */
3475 }
3476 else if (DPE1 && addr >= DPA2ADDR (DPA1L) && addr <= DPA2ADDR (DPA1L) && DPR1
3477 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3478 {
3479 /* data area */
3480 }
3481 else if (DPE2 && addr >= DPA2ADDR (DPA2L) && addr <= DPA2ADDR (DPA2L) && DPR2
3482 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3483 {
3484 /* data area */
3485 }
3486 else if (DPE3 && addr >= DPA2ADDR (DPA3L) && addr <= DPA2ADDR (DPA3L) && DPR3
3487 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3488 {
3489 /* data area */
3490 }
3491 else
3492 {
3493 VMECR &= ~(VMECR_VMW | VMECR_VMX);
3494 VMECR |= VMECR_VMR;
3495 VMADR = addr;
3496 VMTID = TID;
3497 FEIC = 0x431;
3498
3499 PC = 0x30;
3500
3501 SignalException (sd);
3502 result = 0;
3503 }
3504 }
3505
3506 return result;
3507 }
3508
3509 int
3510 mpu_store_mem_test (SIM_DESC sd, unsigned int addr, int size, int base_reg)
3511 {
3512 int result = 1;
3513
3514 if (PSW & PSW_DMP)
3515 {
3516 if (addr >= PPA2ADDR (PPA & ~PPM) && addr <= DPA2ADDR (PPA | PPM))
3517 {
3518 /* preifarallel area */
3519 }
3520 else if (addr >= PPA2ADDR (SPAL) && addr <= DPA2ADDR (SPAU))
3521 {
3522 /* stack area */
3523 }
3524 else if (DPE0 && addr >= DPA2ADDR (DPA0L) && addr <= DPA2ADDR (DPA0L) && DPW0
3525 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3526 {
3527 /* data area */
3528 }
3529 else if (DPE1 && addr >= DPA2ADDR (DPA1L) && addr <= DPA2ADDR (DPA1L) && DPW1
3530 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3531 {
3532 /* data area */
3533 }
3534 else if (DPE2 && addr >= DPA2ADDR (DPA2L) && addr <= DPA2ADDR (DPA2L) && DPW2
3535 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3536 {
3537 /* data area */
3538 }
3539 else if (DPE3 && addr >= DPA2ADDR (DPA3L) && addr <= DPA2ADDR (DPA3L) && DPW3
3540 && ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
3541 {
3542 /* data area */
3543 }
3544 else
3545 {
3546 if (addr >= PPA2ADDR (PPA & ~PPM) && addr <= DPA2ADDR (PPA | PPM))
3547 {
3548 FEIC = 0x432;
3549 VPTID = TID;
3550 VPADR = PC;
3551 #ifdef NOT_YET
3552 VIP_PP;
3553 VPECR;
3554 #endif
3555 }
3556 else
3557 {
3558 FEIC = 0x431;
3559 VMTID = TID;
3560 VMADR = VMECR;
3561 VMECR &= ~(VMECR_VMW | VMECR_VMX);
3562 VMECR |= VMECR_VMR;
3563 PC = 0x30;
3564 }
3565 result = 0;
3566 }
3567 }
3568
3569 return result;
3570 }
3571
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