sim/v850/simops.c

   1 #include <signal.h>
   2 #include "v850_sim.h"
   3 #include "simops.h"
   4
   5 void
   6 OP_220 ()
   7 {
   8 }
   9
  10 void
  11 OP_10760 ()
  12 {
  13 }
  14
  15 void
  16 OP_C7C0 ()
  17 {
  18 }
  19
  20 void
  21 OP_760 ()
  22 {
  23 }
  24
  25 void
  26 OP_580 ()
  27 {
  28 }
  29
  30 void
  31 OP_700 ()
  32 {
  33 }
  34
  35 void
  36 OP_581 ()
  37 {
  38 }
  39
  40 void
  41 OP_582 ()
  42 {
  43 }
  44
  45 void
  46 OP_583 ()
  47 {
  48 }
  49
  50 void
  51 OP_584 ()
  52 {
  53 }
  54
  55 void
  56 OP_585 ()
  57 {
  58 }
  59
  60 void
  61 OP_586 ()
  62 {
  63 }
  64
  65 void
  66 OP_587 ()
  67 {
  68 }
  69
  70 void
  71 OP_588 ()
  72 {
  73 }
  74
  75 void
  76 OP_589 ()
  77 {
  78 }
  79
  80 void
  81 OP_58A ()
  82 {
  83 }
  84
  85 void
  86 OP_58B ()
  87 {
  88 }
  89
  90 void
  91 OP_58C ()
  92 {
  93 }
  94
  95 void
  96 OP_400 ()
  97 {
  98 }
  99
 100 void
 101 OP_160 ()
 102 {
 103 }
 104
 105 void
 106 OP_58D ()
 107 {
 108 }
 109
 110 void
 111 OP_58E ()
 112 {
 113 }
 114
 115 void
 116 OP_58F ()
 117 {
 118 }
 119
 120 void
 121 OP_660 ()
 122 {
 123 }
 124
 125
 126 /* add reg, reg */
 127 void
 128 OP_1C0 ()
 129 {
 130   unsigned int op0, op1, result, z, s, cy, ov;
 131
 132   /* Compute the result.  */
 133   op0 = State.regs[OP[0]];
 134   op1 = State.regs[OP[1]];
 135   result = op0 + op1;
 136
 137   /* Compute the condition codes.  */
 138   z = (result == 0);
 139   s = (result & 0x80000000);
 140   cy = (result < op0 || result < op1);
 141   ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
 142         && (op0 & 0x80000000) != (result & 0x80000000));
 143
 144   /* Store the result and condition codes.  */
 145   State.regs[OP[1]] = result;
 146   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 147   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 148                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 149 }
 150
 151 /* add sign_extend(imm5), reg */
 152 void
 153 OP_240 ()
 154 {
 155   unsigned int op0, op1, result, z, s, cy, ov;
 156   int temp;
 157
 158   /* Compute the result.  */
 159   temp = (OP[0] & 0x1f);
 160   temp = (temp << 27) >> 27;
 161   op0 = temp;
 162   op1 = State.regs[OP[1]];
 163   result = op0 + op1;
 164
 165   /* Compute the condition codes.  */
 166   z = (result == 0);
 167   s = (result & 0x80000000);
 168   cy = (result < op0 || result < op1);
 169   ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
 170         && (op0 & 0x80000000) != (result & 0x80000000));
 171
 172   /* Store the result and condition codes.  */
 173   State.regs[OP[1]] = result;
 174   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 175   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 176                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 177 }
 178
 179 /* addi sign_extend(imm16), reg, reg */
 180 void
 181 OP_600 ()
 182 {
 183   unsigned int op0, op1, result, z, s, cy, ov;
 184   int temp;
 185
 186   /* Compute the result.  */
 187   temp = (OP[0] & 0xffff);
 188   temp = (temp << 16) >> 16;
 189   op0 = temp;
 190   op1 = State.regs[OP[1]];
 191   result = op0 + op1;
 192
 193   /* Compute the condition codes.  */
 194   z = (result == 0);
 195   s = (result & 0x80000000);
 196   cy = (result < op0 || result < op1);
 197   ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
 198         && (op0 & 0x80000000) != (result & 0x80000000));
 199
 200   /* Store the result and condition codes.  */
 201   State.regs[OP[2]] = result;
 202   State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
 203   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
 204                 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
 205 }
 206
 207 /* sub reg1, reg2
 208
 209    XXX condition codes  */
 210 void
 211 OP_1A0 ()
 212 {
 213   State.regs[OP[1]] -= State.regs[OP[0]];
 214 }
 215
 216 /* subr reg1, reg2
 217
 218    XXX condition codes */
 219 void
 220 OP_180 ()
 221 {
 222   State.regs[OP[1]] = State.regs[OP[0]] - State.regs[OP[1]];
 223 }
 224
 225 /* mulh reg1, reg2
 226
 227    XXX condition codes */
 228 void
 229 OP_E0 ()
 230 {
 231   State.regs[OP[1]] = ((State.regs[OP[1]] & 0xffff)
 232                        * (State.regs[OP[0]] & 0xffff));
 233 }
 234
 235 /* mulh sign_extend(imm5), reg2
 236
 237    Condition codes */
 238 void
 239 OP_2E0 ()
 240 {
 241   int value = OP[0];
 242
 243   value = (value << 27) >> 27;
 244
 245   State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value;
 246 }
 247
 248 /* mulhi imm16, reg1, reg2
 249
 250    XXX condition codes */
 251 void
 252 OP_6E0 ()
 253 {
 254   int value = OP[0];
 255
 256   value = value & 0xffff;
 257
 258   State.regs[OP[2]] = (State.regs[OP[1]] & 0xffff) * value;
 259 }
 260
 261 /* divh reg1, reg2
 262
 263    XXX condition codes.
 264    XXX Is this signed or unsigned?  */
 265 void
 266 OP_40 ()
 267 {
 268   State.regs[OP[1]] /= (State.regs[OP[0]] & 0xffff);
 269 }
 270
 271 void
 272 OP_10720 ()
 273 {
 274 }
 275
 276 void
 277 OP_780 ()
 278 {
 279 }
 280
 281 void
 282 OP_720 ()
 283 {
 284 }
 285
 286 void
 287 OP_60 ()
 288 {
 289 }
 290
 291 void
 292 OP_87C0 ()
 293 {
 294 }
 295
 296 void
 297 OP_300 ()
 298 {
 299 }
 300
 301 /* mov reg, reg */
 302 void
 303 OP_0 ()
 304 {
 305   State.regs[OP[1]] = State.regs[OP[0]];
 306 }
 307
 308 /* mov sign_extend(imm5), reg */
 309 void
 310 OP_200 ()
 311 {
 312   int value = OP[0];
 313
 314   value = (value << 27) >> 27;
 315   State.regs[OP[1]] = value;
 316 }
 317
 318 /* movea sign_extend(imm16), reg, reg  */
 319
 320 void
 321 OP_620 ()
 322 {
 323   int value = OP[0];
 324
 325   value = (value << 16) >> 16;
 326
 327   State.regs[OP[2]] = State.regs[OP[1]] + value;
 328 }
 329
 330 /* movhi imm16, reg, reg */
 331 void
 332 OP_640 ()
 333 {
 334   int value = OP[0];
 335
 336   value = (value & 0xffff) << 16;
 337
 338   State.regs[OP[2]] = State.regs[OP[1]] + value;
 339 }
 340
 341 void
 342 OP_7C0 ()
 343 {
 344 }
 345
 346 void
 347 OP_1687E0 ()
 348 {
 349 }
 350
 351 void
 352 OP_1E0 ()
 353 {
 354 }
 355
 356 void
 357 OP_A0 ()
 358 {
 359 }
 360
 361 void
 362 OP_260 ()
 363 {
 364 }
 365
 366 void
 367 OP_740 ()
 368 {
 369 }
 370
 371 void
 372 OP_80 ()
 373 {
 374 }
 375
 376 /* sar zero_extend(imm5),reg1
 377
 378    XXX condition codes.  */
 379 void
 380 OP_2A0 ()
 381 {
 382   int temp = State.regs[OP[1]];
 383
 384   temp >>= (OP[0] & 0x1f);
 385
 386   State.regs[OP[1]] = temp;
 387 }
 388
 389 /* sar reg1, reg2
 390
 391    XXX condition codes.  */
 392 void
 393 OP_A007E0 ()
 394 {
 395   int temp = State.regs[OP[1]];
 396
 397   temp >>= (State.regs[OP[0]] & 0x1f);
 398
 399   State.regs[OP[1]] = temp;
 400 }
 401
 402 /* shl zero_extend(imm5),reg1
 403
 404    XXX condition codes.  */
 405 void
 406 OP_2C0 ()
 407 {
 408   State.regs[OP[1]] <<= (OP[0] & 0x1f);
 409 }
 410
 411 /* shl reg1, reg2
 412
 413    XXX condition codes.  */
 414 void
 415 OP_C007E0 ()
 416 {
 417   State.regs[OP[1]] <<= (State.regs[OP[0]] & 0x1f);
 418 }
 419
 420 /* shr zero_extend(imm5),reg1
 421
 422    XXX condition codes.  */
 423 void
 424 OP_280 ()
 425 {
 426   State.regs[OP[1]] >>= (OP[0] & 0x1f);
 427 }
 428
 429 /* shr reg1, reg2
 430
 431    XXX condition codes.  */
 432 void
 433 OP_8007E0 ()
 434 {
 435   State.regs[OP[1]] >>= (State.regs[OP[0]] & 0x1f);
 436 }
 437
 438 void
 439 OP_500 ()
 440 {
 441 }
 442
 443 void
 444 OP_47C0 ()
 445 {
 446 }
 447
 448 void
 449 OP_7E0 ()
 450 {
 451 }
 452
 453 /* or reg, reg */
 454 void
 455 OP_100 ()
 456 {
 457   unsigned int op0, op1, result, z, s, cy, ov;
 458
 459   /* Compute the result.  */
 460   op0 = State.regs[OP[0]];
 461   op1 = State.regs[OP[1]];
 462   result = op0 | op1;
 463
 464   /* Compute the condition codes.  */
 465   z = (result == 0);
 466   s = (result & 0x80000000);
 467
 468   /* Store the result and condition codes.  */
 469   State.regs[OP[1]] = result;
 470   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
 471   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
 472 }
 473
 474 /* ori zero_extend(imm16), reg, reg */
 475 void
 476 OP_680 ()
 477 {
 478   unsigned int op0, op1, result, z, s, cy, ov;
 479
 480   op0 = OP[0] & 0xffff;
 481   op1 = State.regs[OP[1]];
 482   result = op0 | op1;
 483
 484   /* Compute the condition codes.  */
 485   z = (result == 0);
 486   s = (result & 0x80000000);
 487
 488   /* Store the result and condition codes.  */
 489   State.regs[OP[2]] = result;
 490   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
 491   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
 492   State.psw |= (z ? PSW_Z : 0);
 493 }
 494
 495 /* and reg, reg */
 496 void
 497 OP_140 ()
 498 {
 499   unsigned int op0, op1, result, z, s, cy, ov;
 500
 501   /* Compute the result.  */
 502   op0 = State.regs[OP[0]];
 503   op1 = State.regs[OP[1]];
 504   result = op0 & op1;
 505
 506   /* Compute the condition codes.  */
 507   z = (result == 0);
 508   s = (result & 0x80000000);
 509
 510   /* Store the result and condition codes.  */
 511   State.regs[OP[1]] = result;
 512   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
 513   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
 514 }
 515
 516 /* andi zero_extend(imm16), reg, reg */
 517 void
 518 OP_6C0 ()
 519 {
 520   unsigned int op0, op1, result, z, s, cy, ov;
 521
 522   op0 = OP[0] & 0xffff;
 523   op1 = State.regs[OP[1]];
 524   result = op0 & op1;
 525
 526   /* Compute the condition codes.  */
 527   z = (result == 0);
 528
 529   /* Store the result and condition codes.  */
 530   State.regs[OP[2]] = result;
 531   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
 532   State.psw |= (z ? PSW_Z : 0);
 533 }
 534
 535 /* xor reg, reg */
 536 void
 537 OP_120 ()
 538 {
 539   unsigned int op0, op1, result, z, s, cy, ov;
 540
 541   /* Compute the result.  */
 542   op0 = State.regs[OP[0]];
 543   op1 = State.regs[OP[1]];
 544   result = op0 ^ op1;
 545
 546   /* Compute the condition codes.  */
 547   z = (result == 0);
 548   s = (result & 0x80000000);
 549
 550   /* Store the result and condition codes.  */
 551   State.regs[OP[1]] = result;
 552   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
 553   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
 554 }
 555
 556 /* xori zero_extend(imm16), reg, reg */
 557 void
 558 OP_6A0 ()
 559 {
 560   unsigned int op0, op1, result, z, s, cy, ov;
 561
 562   op0 = OP[0] & 0xffff;
 563   op1 = State.regs[OP[1]];
 564   result = op0 ^ op1;
 565
 566   /* Compute the condition codes.  */
 567   z = (result == 0);
 568   s = (result & 0x80000000);
 569
 570   /* Store the result and condition codes.  */
 571   State.regs[OP[2]] = result;
 572   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
 573   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
 574   State.psw |= (z ? PSW_Z : 0);
 575 }
 576
 577 /* not reg1, reg2 */
 578 void
 579 OP_20 ()
 580 {
 581   unsigned int op0, result, z, s, cy, ov;
 582
 583   /* Compute the result.  */
 584   op0 = State.regs[OP[0]];
 585   result = ~op0;
 586
 587   /* Compute the condition codes.  */
 588   z = (result == 0);
 589   s = (result & 0x80000000);
 590
 591   /* Store the result and condition codes.  */
 592   State.regs[OP[1]] = result;
 593   State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
 594   State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
 595 }
 596
 597 void
 598 OP_C0 ()
 599 {
 600 }
 601
 602 void
 603 OP_480 ()
 604 {
 605 }
 606
 607 void
 608 OP_380 ()
 609 {
 610 }
 611
 612 void
 613 OP_501 ()
 614 {
 615 }
 616
 617 /* di, not supported */
 618 void
 619 OP_16007E0 ()
 620 {
 621   abort ();
 622 }
 623
 624 /* ei, not supported */
 625 void
 626 OP_16087E0 ()
 627 {
 628   abort ();
 629 }
 630
 631 /* halt, not supported */
 632 void
 633 OP_12007E0 ()
 634 {
 635   abort ();
 636 }
 637
 638 /* reti, not supported */
 639 void
 640 OP_14007E0 ()
 641 {
 642   abort ();
 643 }
 644
 645 /* trap, not supportd */
 646 void
 647 OP_10007E0 ()
 648 {
 649   abort ();
 650 }
 651
 652 /* ldsr, not supported */
 653 void
 654 OP_2007E0 ()
 655 {
 656   abort ();
 657 }
 658
 659 /* stsr, not supported */
 660 void
 661 OP_4007E0 ()
 662 {
 663   abort ();
 664 }
 665