MIPS Dependent Features
***********************

GNU AS for MIPS architectures supports several different MIPS processors, and MIPS ISA levels I through IV.  For information about the MIPS instruction set, see MIPS RISC Architecture, by Kane and Heindrich (Prentice-Hall).  For an overview of MIPS assembly conventions, see ``Appendix D: Assembly Language Programming'' in the same work.

Assembler options
=================

The MIPS configurations of GNU AS support these special options:

-G NUM
     This option sets the largest size of an object that can be referenced implicitly with the gp register.  It is only accepted for targets that use ECOFF format.  The default value is 8.

-EB
-EL
     Any MIPS configuration of AS can select big-endian or little-endian output at run time (unlike the other GNU development tools, which must be configured for one or the other).  Use -EB to select big-endian output, and -EL for little-endian.

-mips1
-mips2
-mips3
-mips4
     Generate code for a particular MIPS Instruction Set Architecture level. -mips1 corresponds to the R2000 and R3000 processors, -mips2 to the R6000 processor, -mips3 to the R4000 processor, and -mips4 to the R8000 and R10000 processors.  You can also switch instruction sets during the assembly; see Directives to override the ISA level.

-mips16
-no-mips16
     Generate code for the MIPS 16 processor.  This is equivalent to putting .set mips16 at the start of the assembly file.  -no-mips16 turns off this option.

-m4010
-no-m4010
     Generate code for the LSI R4010 chip.  This tells the assembler to accept the R4010 specific instructions (addciu, ffc, etc.), and to not schedule nop instructions around accesses to the HI and LO registers.  -no-m4010 turns off this option.

-m4650
-no-m4650
     Generate code for the MIPS R4650 chip.  This tells the assembler to accept the mad and madu instruction, and to not schedule nop instructions around accesses to the HI and LO registers. -no-m4650 turns off this option.

-m3900
-no-m3900
-m4100
-no-m4100
     For each option -mNNNN, generate code for the MIPS RNNNN chip.  This tells the assembler to accept instructions specific to that chip, and to schedule for that chip's hazards.

-mcpu=CPU
     Generate code for a particular MIPS cpu.  It is exactly equivalent to -mCPU, except that there are more value of CPU understood.  Valid CPU value are:

          2000, 3000, 3900, 4000, 4010, 4100, 4111, 4300, 4400, 4600, 4650, 5000, 6000, 8000, 10000

-nocpp
     This option is ignored.  It is accepted for command-line compatibility with other assemblers, which use it to turn off C style preprocessing.  With GNU AS, there is no need for -nocpp, because the GNU assembler itself never runs the C preprocessor.

--trap
--no-break
     AS automatically macro expands certain division and multiplication instructions to check for overflow and division by zero.  This option causes AS to generate code to take a trap exception rather than a break exception when an error is detected.  The trap instructions are only supported at Instruction Set Architecture level 2 and higher.

--break
--no-trap
     Generate code to take a break exception rather than a trap exception when an error is detected.  This is the default.

MIPS ECOFF object code
======================

Assembling for a MIPS ECOFF target supports some additional sections besides the usual .text, .data and .bss.  The additional sections are .rdata, used for read-only data, .sdata, used for small data, and .sbss, used for small common objects.

When assembling for ECOFF, the assembler uses the $gp ($28) register to form the address of a ``small object''.  Any object in the .sdata or .sbss sections is considered ``small'' in this sense. For external objects, or for objects in the .bss section, you can use the GCC -G option to control the size of objects addressed via $gp; the default value is 8, meaning that a reference to any object eight bytes or smaller uses $gp.  Passing -G 0 to AS prevents it from using the $gp register on the basis of object size (but the assembler uses $gp for objects in .sdata or sbss in any case).  The size of an object in the .bss section is set by the .comm or .lcomm directive that defines it.  The size of an external object may be set with the .extern directive.  For example, .extern sym,4 declares that the object at sym is 4 bytes in length, whie leaving sym otherwise undefined.

Using small ECOFF objects requires linker support, and assumes that the $gp register is correctly initialized (normally done automatically by the startup code).  MIPS ECOFF assembly code must not modify the $gp register.

Directives for debugging information
====================================

MIPS ECOFF AS supports several directives used for generating debugging information which are not support by traditional MIPS assemblers.  These are .def, .endef, .dim, .file, .scl, .size, .tag, .type, .val, .stabd, .stabn, and .stabs.  The debugging information generated by the three .stab directives can only be read by GDB, not by traditional MIPS debuggers (this enhancement is required to fully support C++ debugging).  These directives are primarily used by compilers, not assembly language programmers!

Directives to override the ISA level
====================================

GNU AS supports an additional directive to change the MIPS Instruction Set Architecture level on the fly: .set mipsN.  N should be a number from 0 to 4.  A value from 1 to 4 makes the assembler accept instructions for the corresponding ISA level, from that point on in the assembly.  .set mipsN affects not only which instructions are permitted, but also how certain macros are expanded.  .set mips0 restores the ISA level to its original level: either the level you selected with command line options, or the default for your configuration.  You can use this feature to permit specific R4000 instructions while assembling in 32 bit mode.  Use this directive with care!

The directive .set mips16 puts the assembler into MIPS 16 mode, in which it will assemble instructions for the MIPS 16 processor.  Use .set nomips16 to return to normal 32 bit mode.

Traditional MIPS assemblers do not support this directive.

Directives for extending MIPS 16 bit instructions
=================================================

By default, MIPS 16 instructions are automatically extended to 32 bits when necessary.  The directive .set noautoextend will turn this off.  When .set noautoextend is in effect, any 32 bit instruction must be explicitly extended with the .e modifier (e.g., li.e $4,1000).  The directive .set autoextend may be used to once again automatically extend instructions when necessary.

This directive is only meaningful when in MIPS 16 mode.  Traditional MIPS assemblers do not support this directive.

Directive to mark data as an instruction
========================================

The .insn directive tells AS that the following data is actually instructions.  This makes a difference in MIPS 16 mode: when loading the address of a label which precedes instructions, AS automatically adds 1 to the value, so that jumping to the loaded address will do the right thing.

Directives to save and restore options
======================================

The directives .set push and .set pop may be used to save and restore the current settings for all the options which are controlled by .set.  The .set push directive saves the current settings on a stack.  The .set pop directive pops the stack and restores the settings.

These directives can be useful inside an macro which must change an option such as the ISA level or instruction reordering but does not want to change the state of the code which invoked the macro.

Traditional MIPS assemblers do not support these directives.