#    Makefile template for Configure for the MIPS simulator.
#    Written by Cygnus Support.

## COMMON_PRE_CONFIG_FRAG

srcdir=@srcdir@
srcroot=$(srcdir)/../../

SIM_NO_OBJ =

# start-sanitize-sky
SIM_SKY_OBJS = \
	sky-console.o \
	sky-device.o \
	sky-dma.o \
	sky-engine.o \
	sky-interact.o \
	sky-gpuif.o \
	sky-hardware.o \
	sky-indebug.o \
	sky-libvpe.o \
	sky-vif.o \
	sky-psio.o \
	sky-vu.o \
	sky-vudis.o \
	sky-gs.o \
	sky-gdb.o
# end-sanitize-sky

SIM_IGEN_OBJ = \
	support.o \
	itable.o \
	semantics.o \
	idecode.o \
	icache.o \
	@mips_igen_engine@ \
	irun.o \

SIM_M16_OBJ = \
	m16_support.o \
	m16_semantics.o \
	m16_idecode.o \
	m16_icache.o \
	\
	m32_support.o \
	m32_semantics.o \
	m32_idecode.o \
	m32_icache.o \
	\
	itable.o \
	m16run.o \

MIPS_EXTRA_OBJS = @mips_extra_objs@
MIPS_EXTRA_LIBS = @mips_extra_libs@

SIM_OBJS = \
	$(SIM_@sim_gen@_OBJ) \
	$(SIM_NEW_COMMON_OBJS) \
	$(MIPS_EXTRA_OBJS) \
	interp.o \
	sim-main.o \
	sim-hload.o \
	sim-engine.o \
	sim-stop.o \
	sim-resume.o \
	sim-reason.o \


# List of flags to always pass to $(CC).
SIM_SUBTARGET=@SIM_SUBTARGET@

# FIXME: Hack to find syscall.h?  Better support for syscall.h
# is in progress.
SIM_EXTRA_CFLAGS = \
	$(SIM_SUBTARGET) \
	-I$(srcdir)/../../newlib/libc/sys/idt

SIM_EXTRA_CLEAN = clean-extra

SIM_EXTRA_ALL = $(SIM_@sim_gen@_ALL)

SIM_EXTRA_LIBS = $(MIPS_EXTRA_LIBS)

# List of main object files for `run'.
SIM_RUN_OBJS = nrun.o



## COMMON_POST_CONFIG_FRAG

SIM_NO_INTERP = oengine.c
interp.o: $(srcdir)/interp.c config.h sim-main.h $(SIM_@sim_gen@_INTERP)


../igen/igen:
	cd ../igen && $(MAKE)

IGEN_TRACE= # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries # -G trace-all
IGEN_INSN=$(srcdir)/mips.igen
IGEN_DC=$(srcdir)/mips.dc
M16_DC=$(srcdir)/m16.dc
IGEN_INCLUDE=\
	$(start-sanitize-r5900) \
	$(srcdir)/r5900.igen \
	$(end-sanitize-r5900) \
	$(start-sanitize-cygnus) \
	$(srcdir)/mdmx.igen \
	$(end-sanitize-cygnus) \
	$(srcdir)/m16.igen \
	$(srcdir)/tx.igen \
	$(srcdir)/vr.igen \

SIM_IGEN_ALL = tmp-igen

BUILT_SRC_FROM_IGEN = \
	icache.h \
	icache.c \
	idecode.h \
	idecode.c \
	semantics.h \
	semantics.c \
	model.h \
	model.c \
	support.h \
	support.c \
	engine.h \
	engine.c \
	irun.c \

# NB:	Since these can be built by either tmp-igen or tmp-m16
#	they are explicitly marked as being dependant on the
#	dependant on the selected generator.
BUILT_SRC_FROM_GEN = \
	itable.h \
	itable.c \

$(BUILT_SRC_FROM_GEN): $(SIM_@sim_gen@_ALL)

$(BUILT_SRC_FROM_IGEN): tmp-igen

tmp-igen: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
	cd ../igen && $(MAKE)
	../igen/igen \
		$(IGEN_TRACE) \
		-I $(srcdir) \
		-Werror \
		-Wnodiscard \
		@sim_igen_flags@ \
		-G gen-direct-access \
		-G gen-zero-r0 \
		-B 32 \
		-H 31 \
		-i $(IGEN_INSN) \
		-o $(IGEN_DC) \
		-x \
		-n icache.h    -hc tmp-icache.h \
		-n icache.c    -c  tmp-icache.c \
		-n semantics.h -hs tmp-semantics.h \
		-n semantics.c -s  tmp-semantics.c \
		-n idecode.h   -hd tmp-idecode.h \
		-n idecode.c   -d  tmp-idecode.c \
		-n model.h     -hm tmp-model.h \
		-n model.c     -m  tmp-model.c \
		-n support.h   -hf tmp-support.h \
		-n support.c   -f  tmp-support.c \
		-n itable.h    -ht tmp-itable.h \
		-n itable.c    -t  tmp-itable.c \
		-n engine.h    -he tmp-engine.h \
		-n engine.c    -e  tmp-engine.c \
		-n irun.c      -r  tmp-irun.c
	$(srcdir)/../../move-if-change tmp-icache.h icache.h
	$(srcdir)/../../move-if-change tmp-icache.c icache.c
	$(srcdir)/../../move-if-change tmp-idecode.h idecode.h
	$(srcdir)/../../move-if-change tmp-idecode.c idecode.c
	$(srcdir)/../../move-if-change tmp-semantics.h semantics.h
	$(srcdir)/../../move-if-change tmp-semantics.c semantics.c
	$(srcdir)/../../move-if-change tmp-model.h model.h
	$(srcdir)/../../move-if-change tmp-model.c model.c
	$(srcdir)/../../move-if-change tmp-support.h support.h
	$(srcdir)/../../move-if-change tmp-support.c support.c
	$(srcdir)/../../move-if-change tmp-itable.h itable.h
	$(srcdir)/../../move-if-change tmp-itable.c itable.c
	$(srcdir)/../../move-if-change tmp-engine.h engine.h
	$(srcdir)/../../move-if-change tmp-engine.c engine.c
	$(srcdir)/../../move-if-change tmp-irun.c irun.c
	touch tmp-igen

semantics.o: sim-main.h semantics.c $(SIM_EXTRA_DEPS)
engine.o: sim-main.h engine.c $(SIM_EXTRA_DEPS)
support.o: sim-main.h support.c $(SIM_EXTRA_DEPS)
idecode.o: sim-main.h idecode.c $(SIM_EXTRA_DEPS)
itable.o: sim-main.h itable.c $(SIM_EXTRA_DEPS)



SIM_M16_ALL = tmp-m16

BUILT_SRC_FROM_M16 = \
	m16_icache.h \
	m16_icache.c \
	m16_idecode.h \
	m16_idecode.c \
	m16_semantics.h \
	m16_semantics.c \
	m16_model.h \
	m16_model.c \
	m16_support.h \
	m16_support.c \
	\
	m32_icache.h \
	m32_icache.c \
	m32_idecode.h \
	m32_idecode.c \
	m32_semantics.h \
	m32_semantics.c \
	m32_model.h \
	m32_model.c \
	m32_support.h \
	m32_support.c \

$(BUILT_SRC_FROM_M16): tmp-m16

tmp-m16: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
	cd ../igen && $(MAKE)
	../igen/igen \
		$(IGEN_TRACE) \
		-I $(srcdir) \
		-Werror \
		-Wnodiscard \
		@sim_m16_flags@ \
		-G gen-direct-access \
		-G gen-zero-r0 \
		-B 16 \
		-H 15 \
		-i $(IGEN_INSN) \
		-o $(M16_DC) \
		-P m16_ \
		-x \
		-n m16_icache.h    -hc tmp-icache.h \
		-n m16_icache.c    -c  tmp-icache.c \
		-n m16_semantics.h -hs tmp-semantics.h \
		-n m16_semantics.c -s  tmp-semantics.c \
		-n m16_idecode.h   -hd tmp-idecode.h \
		-n m16_idecode.c   -d  tmp-idecode.c \
		-n m16_model.h     -hm tmp-model.h \
		-n m16_model.c     -m  tmp-model.c \
		-n m16_support.h   -hf tmp-support.h \
		-n m16_support.c   -f  tmp-support.c \
		#
	$(srcdir)/../../move-if-change tmp-icache.h m16_icache.h
	$(srcdir)/../../move-if-change tmp-icache.c m16_icache.c
	$(srcdir)/../../move-if-change tmp-idecode.h m16_idecode.h
	$(srcdir)/../../move-if-change tmp-idecode.c m16_idecode.c
	$(srcdir)/../../move-if-change tmp-semantics.h m16_semantics.h
	$(srcdir)/../../move-if-change tmp-semantics.c m16_semantics.c
	$(srcdir)/../../move-if-change tmp-model.h m16_model.h
	$(srcdir)/../../move-if-change tmp-model.c m16_model.c
	$(srcdir)/../../move-if-change tmp-support.h m16_support.h
	$(srcdir)/../../move-if-change tmp-support.c m16_support.c
	../igen/igen \
		$(IGEN_TRACE) \
		-I $(srcdir) \
		-Werror \
		-Wnodiscard \
		@sim_igen_flags@ \
		-G gen-direct-access \
		-G gen-zero-r0 \
		-B 32 \
		-H 31 \
		-i $(IGEN_INSN) \
		-o $(IGEN_DC) \
		-P m32_ \
		-x \
		-n m32_icache.h    -hc tmp-icache.h \
		-n m32_icache.c    -c  tmp-icache.c \
		-n m32_semantics.h -hs tmp-semantics.h \
		-n m32_semantics.c -s  tmp-semantics.c \
		-n m32_idecode.h   -hd tmp-idecode.h \
		-n m32_idecode.c   -d  tmp-idecode.c \
		-n m32_model.h     -hm tmp-model.h \
		-n m32_model.c     -m  tmp-model.c \
		-n m32_support.h   -hf tmp-support.h \
		-n m32_support.c   -f  tmp-support.c \
		#
	$(srcdir)/../../move-if-change tmp-icache.h m32_icache.h
	$(srcdir)/../../move-if-change tmp-icache.c m32_icache.c
	$(srcdir)/../../move-if-change tmp-idecode.h m32_idecode.h
	$(srcdir)/../../move-if-change tmp-idecode.c m32_idecode.c
	$(srcdir)/../../move-if-change tmp-semantics.h m32_semantics.h
	$(srcdir)/../../move-if-change tmp-semantics.c m32_semantics.c
	$(srcdir)/../../move-if-change tmp-model.h m32_model.h
	$(srcdir)/../../move-if-change tmp-model.c m32_model.c
	$(srcdir)/../../move-if-change tmp-support.h m32_support.h
	$(srcdir)/../../move-if-change tmp-support.c m32_support.c
	../igen/igen \
		$(IGEN_TRACE) \
		-I $(srcdir) \
		-Werror \
		-Wnodiscard \
		-Wnowidth \
		@sim_igen_flags@ @sim_m16_flags@ \
		-G gen-direct-access \
		-G gen-zero-r0 \
		-i $(IGEN_INSN) \
		-n itable.h    -ht tmp-itable.h \
		-n itable.c    -t  tmp-itable.c \
		#
	$(srcdir)/../../move-if-change tmp-itable.h itable.h
	$(srcdir)/../../move-if-change tmp-itable.c itable.c
	touch tmp-m16


clean-extra:
	rm -f gencode oengine.c tmp.igen
	rm -f $(BUILT_SRC_FROM_GEN)
	rm -f $(BUILT_SRC_FROM_IGEN)
	rm -f $(BUILT_SRC_FROM_M16)
	rm -f tmp-*
	rm -f libhack.a hack
	rm -f m16* m32* itable*

# start-sanitize-vr4xxx
# HACK ....

SIM_HACK_OBJ = \
	itable.o \
        m16vr4111_icache.o m16vr4111_idecode.o m16vr4111_model.o \
	m16vr4111_run.o m16vr4111_semantics.o m16vr4111_support.o \
        m16vr4121_icache.o m16vr4121_idecode.o m16vr4121_model.o \
        m16vr4121_run.o m16vr4121_semantics.o m16vr4121_support.o \
	m32mipsIV_engine.o m32mipsIV_icache.o m32mipsIV_idecode.o \
	m32mipsIV_model.o m32mipsIV_semantics.o m32mipsIV_support.o \
	m32vr4100_engine.o m32vr4100_icache.o m32vr4100_idecode.o \
	m32vr4100_model.o m32vr4100_semantics.o m32vr4100_support.o \
	m32vr4111_engine.o m32vr4111_icache.o m32vr4111_idecode.o \
	m32vr4111_model.o m32vr4111_semantics.o m32vr4111_support.o \
	m32vr4320_engine.o m32vr4320_icache.o m32vr4320_idecode.o \
	m32vr4320_model.o m32vr4320_semantics.o m32vr4320_support.o \
	m32vr4121_engine.o m32vr4121_icache.o m32vr4121_idecode.o \
	m32vr4121_model.o m32vr4121_semantics.o m32vr4121_support.o \
        vr4run.o

HACK_OBJS = \
	itable.o m16vr4111_icache.o m16vr4111_idecode.o \
	m16vr4111_model.o m16vr4111_run.o m16vr4111_semantics.o \
	m16vr4111_support.o m16vr4121_icache.o m16vr4121_idecode.o \
	m16vr4121_model.o m16vr4121_run.o m16vr4121_semantics.o \
	m16vr4121_support.o m32mipsIV_engine.o m32mipsIV_icache.o \
	m32mipsIV_idecode.o m32mipsIV_model.o m32mipsIV_semantics.o \
	m32mipsIV_support.o m32vr4100_engine.o m32vr4100_icache.o \
	m32vr4100_idecode.o m32vr4100_model.o m32vr4100_semantics.o \
	m32vr4100_support.o m32vr4111_engine.o m32vr4111_icache.o \
	m32vr4111_idecode.o m32vr4111_model.o m32vr4111_semantics.o \
	m32vr4111_support.o m32vr4320_engine.o m32vr4320_icache.o \
	m32vr4320_idecode.o m32vr4320_model.o m32vr4320_semantics.o \
	m32vr4320_support.o m32vr4121_engine.o m32vr4121_icache.o \
	m32vr4121_idecode.o m32vr4121_model.o m32vr4121_semantics.o \
	m32vr4121_support.o \
	$(SIM_NEW_COMMON_OBJS) \
	$(MIPS_EXTRA_OBJS) \
	interp.o \
	sim-main.o \
	sim-hload.o \
	sim-engine.o \
	sim-stop.o \
	sim-resume.o \
	sim-reason.o \
	callback.o syscall.o targ-map.o \
	vr4run.o

HACK_GEN_SRCS = \
	itable.c \
	m16vr4111_icache.c m16vr4111_idecode.c m16vr4111_model.c \
	m16vr4111_run.c m16vr4111_semantics.c m16vr4111_support.c \
	m16vr4121_icache.c m16vr4121_idecode.c m16vr4121_model.c \
	m16vr4121_run.c m16vr4121_semantics.c m16vr4121_support.c \
	m32mipsIV_engine.c m32mipsIV_icache.c m32mipsIV_idecode.c \
	m32mipsIV_model.c m32mipsIV_semantics.c m32mipsIV_support.c \
	m32vr4100_engine.c m32vr4100_icache.c m32vr4100_idecode.c \
	m32vr4100_model.c m32vr4100_semantics.c m32vr4100_support.c \
	m32vr4111_engine.c m32vr4111_icache.c m32vr4111_idecode.c \
	m32vr4111_model.c m32vr4111_semantics.c m32vr4111_support.c \
	m32vr4320_engine.c m32vr4320_icache.c m32vr4320_idecode.c \
	m32vr4320_model.c m32vr4320_semantics.c m32vr4320_support.c \
	m32vr4121_engine.c m32vr4121_icache.c m32vr4121_idecode.c \
	m32vr4121_model.c m32vr4121_semantics.c m32vr4121_support.c

$(HACK_GEN_SRCS): tmp-hack

libhack.a: $(HACK_OBJS)
	rm -f libhack.a
	$(AR) $(AR_FLAGS) libhack.a $(HACK_OBJS)
	$(RANLIB) libhack.a
hack: tmp-hack $(SIM_RUN_OBJS) libhack.a
	$(CC) $(ALL_CFLAGS) -o hack$(EXEEXT) \
	  $(SIM_RUN_OBJS) libhack.a $(EXTRA_LIBS)

tmp-hack: tmp-m16-hack tmp-m32-hack tmp-itable-hack tmp-run-hack targ-vals.h
tmp-m32-hack: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
	for t in m32mipsIV:mipsIV m32vr4100:vr4100 m32vr4111:vr4100 m32vr4320:vr4320 m32vr4121:vr4121 ; \
	do \
	  p=`echo $${t} | sed -e 's/:.*//'` ; \
	  m=`echo $${t} | sed -e 's/.*://'` ; \
	  ../igen/igen \
		$(IGEN_TRACE) \
		-I $(srcdir) \
		-Werror \
		-Wnodiscard \
		-N 0 \
		-M $${m} -F 32,64,f \
		-G gen-direct-access \
		-G gen-zero-r0 \
		-B 32 \
		-H 31 \
		-i $(IGEN_INSN) \
		-o $(IGEN_DC) \
		-P $${p}_ \
		-x \
		-n $${p}_icache.h    -hc tmp-icache.h \
		-n $${p}_icache.c    -c  tmp-icache.c \
		-n $${p}_semantics.h -hs tmp-semantics.h \
		-n $${p}_semantics.c -s  tmp-semantics.c \
		-n $${p}_idecode.h   -hd tmp-idecode.h \
		-n $${p}_idecode.c   -d  tmp-idecode.c \
		-n $${p}_model.h     -hm tmp-model.h \
		-n $${p}_model.c     -m  tmp-model.c \
		-n $${p}_support.h   -hf tmp-support.h \
		-n $${p}_support.c   -f  tmp-support.c \
		-n $${p}_engine.h    -he tmp-engine.h \
		-n $${p}_engine.c    -e  tmp-engine.c \
		; \
	  $(srcdir)/../../move-if-change tmp-icache.h $${p}_icache.h ; \
	  $(srcdir)/../../move-if-change tmp-icache.c $${p}_icache.c ; \
	  $(srcdir)/../../move-if-change tmp-idecode.h $${p}_idecode.h ; \
	  $(srcdir)/../../move-if-change tmp-idecode.c $${p}_idecode.c ; \
	  $(srcdir)/../../move-if-change tmp-semantics.h $${p}_semantics.h ; \
	  $(srcdir)/../../move-if-change tmp-semantics.c $${p}_semantics.c ; \
	  $(srcdir)/../../move-if-change tmp-model.h $${p}_model.h ; \
	  $(srcdir)/../../move-if-change tmp-model.c $${p}_model.c ; \
	  $(srcdir)/../../move-if-change tmp-support.h $${p}_support.h ; \
	  $(srcdir)/../../move-if-change tmp-support.c $${p}_support.c ; \
	  $(srcdir)/../../move-if-change tmp-engine.h $${p}_engine.h ; \
	  $(srcdir)/../../move-if-change tmp-engine.c $${p}_engine.c ; \
	done
	touch tmp-m32-hack
tmp-m16-hack: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
	for t in m16vr4111:vr4100 m16vr4121:vr4121 ; \
	do \
	  p=`echo $${t} | sed -e 's/:.*//'` ; \
	  m=`echo $${t} | sed -e 's/.*://'` ; \
	  ../igen/igen \
		$(IGEN_TRACE) \
		-I $(srcdir) \
		-Werror \
		-Wnodiscard \
		-N 0 \
		-M $${m},mips16 -F 16 \
		-G gen-direct-access \
		-G gen-zero-r0 \
		-B 16 \
		-H 15 \
		-i $(IGEN_INSN) \
		-o $(M16_DC) \
		-P $${p}_ \
		-x \
		-n $${p}_icache.h    -hc tmp-icache.h \
		-n $${p}_icache.c    -c  tmp-icache.c \
		-n $${p}_semantics.h -hs tmp-semantics.h \
		-n $${p}_semantics.c -s  tmp-semantics.c \
		-n $${p}_idecode.h   -hd tmp-idecode.h \
		-n $${p}_idecode.c   -d  tmp-idecode.c \
		-n $${p}_model.h     -hm tmp-model.h \
		-n $${p}_model.c     -m  tmp-model.c \
		-n $${p}_support.h   -hf tmp-support.h \
		-n $${p}_support.c   -f  tmp-support.c \
		-n $${p}_engine.h    -he tmp-engine.h \
		; \
	  $(srcdir)/../../move-if-change tmp-icache.h $${p}_icache.h ; \
	  $(srcdir)/../../move-if-change tmp-icache.c $${p}_icache.c ; \
	  $(srcdir)/../../move-if-change tmp-idecode.h $${p}_idecode.h ; \
	  $(srcdir)/../../move-if-change tmp-idecode.c $${p}_idecode.c ; \
	  $(srcdir)/../../move-if-change tmp-semantics.h $${p}_semantics.h ; \
	  $(srcdir)/../../move-if-change tmp-semantics.c $${p}_semantics.c ; \
	  $(srcdir)/../../move-if-change tmp-model.h $${p}_model.h ; \
	  $(srcdir)/../../move-if-change tmp-model.c $${p}_model.c ; \
	  $(srcdir)/../../move-if-change tmp-support.h $${p}_support.h ; \
	  $(srcdir)/../../move-if-change tmp-support.c $${p}_support.c ; \
	  $(srcdir)/../../move-if-change tmp-engine.h $${p}_engine.h ; \
	done
	touch tmp-m16-hack
tmp-itable-hack: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
	../igen/igen \
		$(IGEN_TRACE) \
		-I $(srcdir) \
		-Werror \
		-Wnodiscard \
		-Wnowidth \
		-N 0 \
		-F 32,64,f -M vr4100,vr4320,mipsIV,vr4121 -F 16 -M mips16 \
		-G gen-direct-access \
		-G gen-zero-r0 \
		-i $(IGEN_INSN) \
		-n itable.h    -ht tmp-itable.h \
		-n itable.c    -t  tmp-itable.c \
		#
	$(srcdir)/../../move-if-change tmp-itable.h itable.h
	$(srcdir)/../../move-if-change tmp-itable.c itable.c
	touch tmp-itable-hack
tmp-run-hack: $(srcdir)/m16run.c
	for m in vr4111 vr4121 ; \
	do \
	  sed <  $(srcdir)/m16run.c > tmp-run \
		-e "s/^sim_/m16$${m}_/" \
		-e "s/m16_/m16$${m}_/" \
		-e "s/m32_/m32$${m}_/" ; \
	  $(srcdir)/../../move-if-change tmp-run m16$${m}_run.c ; \
	done
	touch tmp-run-hack

# end-sanitize-vr4xxx