Tue Oct 15 16:19:51 1996 Stu Grossman (grossman@critters.cygnus.com) * interp.c (MEM_SIZE): It's now bytes, not a power of 2. * (map): Add support for external mem in the 1->2 meg range. Also, abort() when memory access is way out of bounds. (Better to die than to give wrong result. (This will be fixed later.)) * (sim_size): MEM_SIZE is now bytes, not shift factor. Tue Oct 1 15:53:24 1996 Gavin Koch * simops.c (trace_input): Swapped order of operands for output output of OP_IMM_REG. Changed the fetching of the operands for OP_LOAD32, and OP_STORE32 to work like op-function. Mon Sep 30 15:46:33 1996 Stu Grossman (grossman@critters.cygnus.com) * interp.c: Move includes of remote-sim.h and callback.h to v850-sim.h. * (lookup_hash): Add PC to report of hash failure. * (map load_mem store_mem): New memory subsystem. Models V851 memory system. * (sim_write sim_read): Use new memory subsystem. * (sim_resume): Don't load and save PC into EIPC anymore. Needed to make user-defined traps work right. * simops.c (OP_*): Use new memory subsystem. * (OP_14007E0 (reti)): Implement reti. * (OP_14996E0 (trap)): Implement user-defined traps. Move I/O to trap 31. Use new memory subsystem. * v850_sim.h: Prototypes for load_mem, store_mem and map. Use load_mem in RLW macro. Fri Sep 27 18:34:09 1996 Stu Grossman (grossman@critters.cygnus.com) * gencode.c (write_opcodes): Output hex values for opcode mask and patterns. * interp.c (sim_resume): Save and restore PC from the appropriate register. * (sim_fetch_register sim_store_register): Fix byte-order problem with reading and writing registers. * simops.c (OP_FFFF): Implement pseudo-breakpoint insn. Fri Sep 27 17:42:37 1996 Jeffrey A Law (law@cygnus.com) * simops.c (trace_input): Fix thinko. Wed Sep 18 09:54:12 1996 Michael Meissner * simops.c (exec_bfd): Rename from sim_bfd. (trace_input): Ditto. Thu Sep 12 12:03:05 1996 Michael Meissner * simops.c (trace_input): Use find_nearest_line to print line number, function name or file name of PC. Wed Sep 11 16:44:37 1996 Michael Meissner * simops.c: Add tracing support. Use SEXTxx macros instead of doing hardwired shifts. * configure.in (--enable-sim-cflags): Add switch to add additional flags to simulator buld. If --enable-sim-cflags=trace, turn on tracing. * configure: Regenerate. * Makefile.in: Don't require a VPATH capable make if configuring in the same directory. Don't use CFLAGS for configuration flags. Add flags from --enable-sim-cflags. Support canadian cross builds. Rebuild whole simulator if include files change. * interp.c (v850_debug): New global for debugging. (lookup_hash,sim_size,sim_set_profile): Use printf_filtered callback, instead of calling printf directly. (sim_{open,trace}): Enable tracing if -t and compiled for tracing. * v850_sim.h: Use limits.h to set the various sized types. (SEXT{5,7,16,22}): New macros. Mon Sep 9 20:50:46 1996 Jeffrey A Law (law@cygnus.com) * interp.c (hash): Make this an inline function when compiling with GCC. Simplify. * simpos.c: Explicitly include "sys/syscall.h". Remove some #if 0'd code. Enable more emulated syscalls. Wed Sep 4 01:48:55 1996 Jeffrey A Law (law@cygnus.com) * interp.c: Fix sign bit handling for add and sub instructions. Tue Sep 3 10:20:30 1996 Jeffrey A Law (law@cygnus.com) * gencode.c: Fix various indention & style problems. Remove test code. Remove #if 0 code. * interp.c: Provide prototypes for all static functions. Fix minor indention problems. (sim_open, sim_resume): Remove unused variables. (sim_read): Return type is "int". * simops.c: Remove unused variables. (divh): Make result of divide-by-zero zero. (setf): Initialize result to keep compiler quiet. (sar instructions): These just clear the overflow bit. * v850_sim.h: Provide prototypes for put_byte, put_half and put_word. * interp.c: OP should be an array of 32bit operands! (v850_callback): Declare. (do_format_5): Fix extraction of OP[0]. (sim_size): Remove debugging printf. (sim_set_callbacks): Do something useful. (sim_stop_reason): Gross hacks to get c-torture running. * simops.c: Simplify code for computing targets of bCC insns. Invert 's' bit if 'ov' bit is set for some instructions. Fix 'cy' bit handling for numerous instructions. Make the simulator stop when a halt instruction is encountered. Very crude support for emulated syscalls (trap 0). * v850_sim.h: Include "callback.h" and declare v850_callback. Items in the operand array are 32bits. Sun Sep 1 22:35:35 1996 Jeffrey A Law (law@cygnus.com) * interp.c (sim_resume): Fix code to check for a format 3 opcode. * simops.c: bCC insns only argument is a constant, not a register value (duh...) Fri Aug 30 10:33:49 1996 Jeffrey A Law (law@cygnus.com) * simops.c: Fix "not1" and "set1". * simops.c: Don't forget to initialize temp for "ld.h" and "ld.w" * interp.c: Remove various debugging printfs. * simops.c: Fix satadd, satsub boundary case handling. * interp.c (hash): Fix. * interp.c (do_format_8): Get operands correctly and call the target function. * simops.c: Rough cut at "clr1", "not1", "set1", and "tst1". Thu Aug 29 13:53:29 1996 Jeffrey A Law (law@cygnus.com) * interp.c (do_format_4): Get operands correctly and call the target function. * simops.c: Rough cut at "sld.b", "sld.h", "sld.w", "sst.b", "sst.h", and "sst.w". * v850_sim.h: The V850 doesn't have split I&D spaces. Change accordingly. Remove many unused definitions. * interp.c: The V850 doesn't have split I&D spaces. Change accordingly. (get_longlong, get_longword, get_word): Deleted. (write_longlong, write_longword, write_word): Deleted. (get_operands): Deleted. (get_byte, get_half, get_word): New functions. (put_byte, put_half, put_word): New functions. * simops.c: Remove unused functions. Rough cut at "ld.b", "ld.h", "ld.w", "st.b", "st.h", "st.w" insns. * v850_sim.h (struct _state): Remove "psw" field. Add "sregs" field. (PSW): Remove bogus definition. * simops.c: Change condition code handling to use the psw register within the sregs array. Handle "ldsr" and "stsr". * simops.c: Handle "satadd", "satsub", "satsubi", "satsubr". * interp.c (do_format_5): Get operands correctly and call the target function. (sim_resume): Don't do a PC update for format 5 instructions. * simops.c: Handle "jarl" and "jmp" instructions. * simops.c: Fix minor typos. Handle "cmp", "setf", "tst" "di", and "ei" instructions correctly. * interp.c (do_format_3): Get operands correctly and call the target function. * simops.c: Handle bCC instructions. * simops.c: Add condition code handling to shift insns. Fix minor typos in condition code handling for other insns. * Makefile.in: Fix typo. * simops.c: Add condition code handling to "sub" "subr" and "divh" instructions. * interp.c (hash): Update to be more accurate. (lookup_hash): Call hash rather than computing the hash code here. (do_format_1_2): Handle format 1 and format 2 instructions. Get operands correctly and call the target function. (do_format_6): Get operands correctly and call the target function. (do_formats_9_10): Rough cut so shift ops will work. (sim_resume): Tweak to deal with format 1 and format 2 handling in a single funtion. Don't update the PC for format 3 insns. Fix typos. * simops.c: Slightly reorganize. Add condition code handling to "add", "addi", "and", "andi", "or", "ori", "xor", "xori" and "not" instructions. * v850_sim.h (reg_t): Registers are 32bits. (_state): The V850 has 32 general registers. Add a 32bit psw and pc register too. Add accessor macros * Makefile.in, interp.c, v850_sim.h: Bring over endianness changes from the d10v simulator. * simops.c: Add shift support. * simops.c: Add multiply & divide support. Abort for system instructions. * simops.c: Add logicals, mov, movhi, movea, add, addi, sub and subr. No condition codes yet. Wed Aug 28 13:53:22 1996 Jeffrey A Law (law@cygnus.com) * ChangeLog, Makefile.in, configure, configure.in, v850_sim.h, gencode.c, interp.c, simops.c: Created.