kernel configuration options. The intention is to make it easier to
build a config tool - later.
+- ARM Platform Bus Type(CCI):
+ CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
+ provides full cache coherency between two clusters of multi-core
+ CPUs and I/O coherency for devices and I/O masters
+
+ CONFIG_SYS_FSL_HAS_CCI400
+
+ Defined For SoC that has cache coherent interconnect
+ CCN-400
+
+ CONFIG_SYS_FSL_HAS_CCN504
+
+ Defined for SoC that has cache coherent interconnect CCN-504
The following options need to be configured:
binary in its image. This device tree file should be in the
board directory and called <soc>-<board>.dts. The binary file
is then picked up in board_init_f() and made available through
- the global data structure as gd->blob.
+ the global data structure as gd->fdt_blob.
CONFIG_OF_SEPARATE
If this variable is defined, U-Boot will build a device tree
Define this if you need to first read the OOB and then the
data. This is used, for example, on davinci platforms.
- CONFIG_SPL_OMAP3_ID_NAND
- Support for an OMAP3-specific set of functions to return the
- ID and MFR of the first attached NAND chip, if present.
-
CONFIG_SPL_RAM_DEVICE
Support for running image already present in ram, in SPL binary