ARC: Invalidate instruction and data caches early on boot

[people/ms/u-boot.git] / arch / arc / lib / start.S

diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S
index 95d64f9d4375505e32e0f3af5c72bc53bb548fee..0d72fe71d42bbdf1f304150e2a1d27d2a07d7fc7 100644 (file)
--- a/arch/arc/lib/start.S
+++ b/arch/arc/lib/start.S
@@ -44,6 +44,14 @@ ENTRY(_start)
 #endif
        sr      r5, [ARC_AUX_IC_CTRL]
 
+       mov     r5, 1
+       sr      r5, [ARC_AUX_IC_IVIC]
+       ; As per ARC HS databook (see chapter 5.3.3.2)
+       ; it is required to add 3 NOPs after each write to IC_IVIC.
+       nop
+       nop
+       nop
+
 1:
        ; Disable/enable D-cache according to configuration
        lr      r5, [ARC_BCR_DC_BUILD]
@@ -57,6 +65,10 @@ ENTRY(_start)
 #endif
        sr      r5, [ARC_AUX_DC_CTRL]
 
+       mov     r5, 1
+       sr      r5, [ARC_AUX_DC_IVDC]
+
+
 1:
 #ifdef CONFIG_ISA_ARCV2
        ; Disable System-Level Cache (SLC)