Merge branch 'master' of git://git.denx.de/u-boot-rockchip

[people/ms/u-boot.git] / arch / arm / mach-rockchip / rk3288 / sdram_rk3288.c

diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
index 2feda612054b9cc4582f5bce41c098e5f2e3738f..95efb117fc17c439327bdc485d3749b22e69f148 100644 (file)
--- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
@@ -22,6 +22,7 @@
 #include <asm/arch/grf_rk3288.h>
 #include <asm/arch/pmu_rk3288.h>
 #include <asm/arch/sdram.h>
+#include <asm/arch/sdram_common.h>
 #include <linux/err.h>
 #include <power/regulator.h>
 #include <power/rk8xx_pmic.h>
@@ -923,53 +924,7 @@ error:
        printf("DRAM init failed!\n");
        hang();
 }
-#endif /* CONFIG_SPL_BUILD */
-
-size_t sdram_size_mb(struct rk3288_pmu *pmu)
-{
-       u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
-       size_t chipsize_mb = 0;
-       size_t size_mb = 0;
-       u32 ch;
-       u32 sys_reg = readl(&pmu->sys_reg[2]);
-       u32 chans;
-
-       chans = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) & SYS_REG_NUM_CH_MASK);
-
-       for (ch = 0; ch < chans; ch++) {
-               rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
-                       SYS_REG_RANK_MASK);
-               col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
-               bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
-               cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
-                               SYS_REG_CS0_ROW_MASK);
-               cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
-                               SYS_REG_CS1_ROW_MASK);
-               bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) &
-                       SYS_REG_BW_MASK));
-               row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
-                       SYS_REG_ROW_3_4_MASK;
-               chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
-
-               if (rank > 1)
-                       chipsize_mb += chipsize_mb >>
-                               (cs0_row - cs1_row);
-               if (row_3_4)
-                       chipsize_mb = chipsize_mb * 3 / 4;
-               size_mb += chipsize_mb;
-       }
-
-       /*
-       * we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff
-       * is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is 
-       * inaccessible for some IP controller.
-       */
-       size_mb = min(size_mb, 0xfe000000 >> 20);
 
-       return size_mb;
-}
-
-#ifdef CONFIG_SPL_BUILD
 # ifdef CONFIG_ROCKCHIP_FAST_SPL
 static int veyron_init(struct dram_info *priv)
 {
@@ -1018,29 +973,27 @@ static int rk3288_dmc_ofdata_to_platdata(struct udevice *dev)
 {
 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
        struct rk3288_sdram_params *params = dev_get_platdata(dev);
-       const void *blob = gd->fdt_blob;
-       int node = dev_of_offset(dev);
        int ret;
 
        /* Rk3288 supports dual-channel, set default channel num to 2 */
        params->num_channels = 2;
-       ret = fdtdec_get_int_array(blob, node, "rockchip,pctl-timing",
-                                  (u32 *)&params->pctl_timing,
-                                  sizeof(params->pctl_timing) / sizeof(u32));
+       ret = dev_read_u32_array(dev, "rockchip,pctl-timing",
+                                (u32 *)&params->pctl_timing,
+                                sizeof(params->pctl_timing) / sizeof(u32));
        if (ret) {
                debug("%s: Cannot read rockchip,pctl-timing\n", __func__);
                return -EINVAL;
        }
-       ret = fdtdec_get_int_array(blob, node, "rockchip,phy-timing",
-                                  (u32 *)&params->phy_timing,
-                                  sizeof(params->phy_timing) / sizeof(u32));
+       ret = dev_read_u32_array(dev, "rockchip,phy-timing",
+                                (u32 *)&params->phy_timing,
+                                sizeof(params->phy_timing) / sizeof(u32));
        if (ret) {
                debug("%s: Cannot read rockchip,phy-timing\n", __func__);
                return -EINVAL;
        }
-       ret = fdtdec_get_int_array(blob, node, "rockchip,sdram-params",
-                                  (u32 *)&params->base,
-                                  sizeof(params->base) / sizeof(u32));
+       ret = dev_read_u32_array(dev, "rockchip,sdram-params",
+                                (u32 *)&params->base,
+                                sizeof(params->base) / sizeof(u32));
        if (ret) {
                debug("%s: Cannot read rockchip,sdram-params\n", __func__);
                return -EINVAL;
@@ -1087,12 +1040,14 @@ static int rk3288_dmc_probe(struct udevice *dev)
 {
 #ifdef CONFIG_SPL_BUILD
        struct rk3288_sdram_params *plat = dev_get_platdata(dev);
-#endif
-       struct dram_info *priv = dev_get_priv(dev);
+       struct udevice *dev_clk;
        struct regmap *map;
        int ret;
-       struct udevice *dev_clk;
+#endif
+       struct dram_info *priv = dev_get_priv(dev);
 
+       priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
+#ifdef CONFIG_SPL_BUILD
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
        ret = conv_of_platdata(dev);
        if (ret)
@@ -1107,14 +1062,12 @@ static int rk3288_dmc_probe(struct udevice *dev)
 
        priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
        priv->sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
-       priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
 
-#ifdef CONFIG_SPL_BUILD
        priv->chan[0].pctl = regmap_get_range(plat->map, 0);
        priv->chan[0].publ = regmap_get_range(plat->map, 1);
        priv->chan[1].pctl = regmap_get_range(plat->map, 2);
        priv->chan[1].publ = regmap_get_range(plat->map, 3);
-#endif
+
        ret = rockchip_get_clk(&dev_clk);
        if (ret)
                return ret;
@@ -1126,13 +1079,14 @@ static int rk3288_dmc_probe(struct udevice *dev)
        priv->cru = rockchip_get_cru();
        if (IS_ERR(priv->cru))
                return PTR_ERR(priv->cru);
-#ifdef CONFIG_SPL_BUILD
        ret = setup_sdram(dev);
        if (ret)
                return ret;
+#else
+       priv->info.base = CONFIG_SYS_SDRAM_BASE;
+       priv->info.size = rockchip_sdram_size(
+                       (phys_addr_t)&priv->pmu->sys_reg[2]);
 #endif
-       priv->info.base = 0;
-       priv->info.size = sdram_size_mb(priv->pmu) << 20;
 
        return 0;
 }