#include <asm/arch/grf_rk3288.h>
#include <asm/arch/pmu_rk3288.h>
#include <asm/arch/sdram.h>
+#include <asm/arch/sdram_common.h>
#include <linux/err.h>
#include <power/regulator.h>
-#include <power/rk808_pmic.h>
+#include <power/rk8xx_pmic.h>
DECLARE_GLOBAL_DATA_PTR;
struct regmap *map;
};
+const int ddrconf_table[] = {
+ /* row col,bw */
+ 0,
+ ((1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
+ ((2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
+ ((3 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
+ ((4 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
+ ((1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
+ ((2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
+ ((3 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
+ ((1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
+ ((2 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
+ ((3 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
+ 0,
+ 0,
+ 0,
+ 0,
+ ((4 << 4) | 2),
+};
+
#define TEST_PATTEN 0x5aa5f00f
#define DQS_GATE_TRAINING_ERROR_RANK0 (1 << 4)
#define DQS_GATE_TRAINING_ERROR_RANK1 (2 << 4)
static void phy_pctrl_reset(struct rk3288_cru *cru,
struct rk3288_ddr_publ *publ,
- u32 channel)
+ int channel)
{
int i;
u32 freq)
{
int i;
+
if (freq <= 250000000) {
if (freq <= 150000000)
clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);
UPCTL0_LPDDR3_ODT_EN_SHIFT));
}
-static void pctl_cfg(u32 channel, struct rk3288_ddr_pctl *pctl,
+static void pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl,
struct rk3288_sdram_params *sdram_params,
struct rk3288_grf *grf)
{
setbits_le32(&pctl->scfg, 1);
}
-static void phy_cfg(const struct chan_info *chan, u32 channel,
+static void phy_cfg(const struct chan_info *chan, int channel,
struct rk3288_sdram_params *sdram_params)
{
struct rk3288_ddr_publ *publ = chan->publ;
while ((readl(&publ->pgsr) & PGSR_DLDONE)
!= PGSR_DLDONE)
;
- /* if at low power state,need wakeup first,
+ /*
+ * if at low power state,need wakeup first,
* and then enter the config
* so here no break.
*/
}
}
-static void set_bandwidth_ratio(const struct chan_info *chan, u32 channel,
+static void set_bandwidth_ratio(const struct chan_info *chan, int channel,
u32 n, struct rk3288_grf *grf)
{
struct rk3288_ddr_pctl *pctl = chan->pctl;
setbits_le32(&pctl->dfistcfg0, 1 << 2);
}
-static int data_training(const struct chan_info *chan, u32 channel,
+static int data_training(const struct chan_info *chan, int channel,
struct rk3288_sdram_params *sdram_params)
{
unsigned int j;
writel(sys_reg, &dram->pmu->sys_reg[2]);
rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, sdram_params->base.stride);
}
-const int ddrconf_table[] = {
- /* row col,bw */
- 0,
- ((1 << 4) | 1),
- ((2 << 4) | 1),
- ((3 << 4) | 1),
- ((4 << 4) | 1),
- ((1 << 4) | 2),
- ((2 << 4) | 2),
- ((3 << 4) | 2),
- ((1 << 4) | 0),
- ((2 << 4) | 0),
- ((3 << 4) | 0),
- 0,
- 0,
- 0,
- 0,
- ((4 << 4) | 2),
-};
static int sdram_rank_bw_detect(struct dram_info *dram, int channel,
struct rk3288_sdram_params *sdram_params)
const struct chan_info *chan = &dram->chan[channel];
struct rk3288_ddr_publ *publ = chan->publ;
- if (-1 == data_training(chan, channel, sdram_params)) {
+ if (data_training(chan, channel, sdram_params) < 0) {
reg = readl(&publ->datx8[0].dxgsr[0]);
/* Check the result for rank 0 */
if ((channel == 0) && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) {
debug("data training fail!\n");
- return -EIO;
+ return -EIO;
} else if ((channel == 1) &&
(reg & DQS_GATE_TRAINING_ERROR_RANK0)) {
sdram_params->num_channels = 1;
sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw;
if (need_trainig &&
- (-1 == data_training(chan, channel, sdram_params))) {
+ (data_training(chan, channel, sdram_params) < 0)) {
if (sdram_params->base.dramtype == LPDDR3) {
ddr_phy_ctl_reset(dram->cru, channel, 1);
udelay(10);
printf("DRAM init failed!\n");
hang();
}
-#endif /* CONFIG_SPL_BUILD */
-size_t sdram_size_mb(struct rk3288_pmu *pmu)
-{
- u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
- size_t chipsize_mb = 0;
- size_t size_mb = 0;
- u32 ch;
- u32 sys_reg = readl(&pmu->sys_reg[2]);
- u32 chans;
-
- chans = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) & SYS_REG_NUM_CH_MASK);
-
- for (ch = 0; ch < chans; ch++) {
- rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
- SYS_REG_RANK_MASK);
- col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
- bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
- cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
- SYS_REG_CS0_ROW_MASK);
- cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
- SYS_REG_CS1_ROW_MASK);
- bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) &
- SYS_REG_BW_MASK));
- row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
- SYS_REG_ROW_3_4_MASK;
- chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
-
- if (rank > 1)
- chipsize_mb += chipsize_mb >>
- (cs0_row - cs1_row);
- if (row_3_4)
- chipsize_mb = chipsize_mb * 3 / 4;
- size_mb += chipsize_mb;
- }
-
- /*
- * we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff
- * is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is
- * inaccessible for some IP controller.
- */
- size_mb = min(size_mb, 0xfe000000 >> 20);
-
- return size_mb;
-}
-
-#ifdef CONFIG_SPL_BUILD
# ifdef CONFIG_ROCKCHIP_FAST_SPL
static int veyron_init(struct dram_info *priv)
{
return ret;
/* Slowly raise to max CPU voltage to prevent overshoot */
- ret = rk808_spl_configure_buck(pmic, 1, 1200000);
+ ret = rk8xx_spl_configure_buck(pmic, 1, 1200000);
if (ret)
return ret;
udelay(175);/* Must wait for voltage to stabilize, 2mV/us */
- ret = rk808_spl_configure_buck(pmic, 1, 1400000);
+ ret = rk8xx_spl_configure_buck(pmic, 1, 1400000);
if (ret)
return ret;
udelay(100);/* Must wait for voltage to stabilize, 2mV/us */
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3288_sdram_params *params = dev_get_platdata(dev);
- const void *blob = gd->fdt_blob;
- int node = dev_of_offset(dev);
int ret;
/* Rk3288 supports dual-channel, set default channel num to 2 */
params->num_channels = 2;
- ret = fdtdec_get_int_array(blob, node, "rockchip,pctl-timing",
- (u32 *)¶ms->pctl_timing,
- sizeof(params->pctl_timing) / sizeof(u32));
+ ret = dev_read_u32_array(dev, "rockchip,pctl-timing",
+ (u32 *)¶ms->pctl_timing,
+ sizeof(params->pctl_timing) / sizeof(u32));
if (ret) {
debug("%s: Cannot read rockchip,pctl-timing\n", __func__);
return -EINVAL;
}
- ret = fdtdec_get_int_array(blob, node, "rockchip,phy-timing",
- (u32 *)¶ms->phy_timing,
- sizeof(params->phy_timing) / sizeof(u32));
+ ret = dev_read_u32_array(dev, "rockchip,phy-timing",
+ (u32 *)¶ms->phy_timing,
+ sizeof(params->phy_timing) / sizeof(u32));
if (ret) {
debug("%s: Cannot read rockchip,phy-timing\n", __func__);
return -EINVAL;
}
- ret = fdtdec_get_int_array(blob, node, "rockchip,sdram-params",
- (u32 *)¶ms->base,
- sizeof(params->base) / sizeof(u32));
+ ret = dev_read_u32_array(dev, "rockchip,sdram-params",
+ (u32 *)¶ms->base,
+ sizeof(params->base) / sizeof(u32));
if (ret) {
debug("%s: Cannot read rockchip,sdram-params\n", __func__);
return -EINVAL;
{
#ifdef CONFIG_SPL_BUILD
struct rk3288_sdram_params *plat = dev_get_platdata(dev);
-#endif
- struct dram_info *priv = dev_get_priv(dev);
+ struct udevice *dev_clk;
struct regmap *map;
int ret;
- struct udevice *dev_clk;
+#endif
+ struct dram_info *priv = dev_get_priv(dev);
+ priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
+#ifdef CONFIG_SPL_BUILD
#if CONFIG_IS_ENABLED(OF_PLATDATA)
ret = conv_of_platdata(dev);
if (ret)
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
priv->sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
- priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
-#ifdef CONFIG_SPL_BUILD
priv->chan[0].pctl = regmap_get_range(plat->map, 0);
priv->chan[0].publ = regmap_get_range(plat->map, 1);
priv->chan[1].pctl = regmap_get_range(plat->map, 2);
priv->chan[1].publ = regmap_get_range(plat->map, 3);
-#endif
+
ret = rockchip_get_clk(&dev_clk);
if (ret)
return ret;
priv->cru = rockchip_get_cru();
if (IS_ERR(priv->cru))
return PTR_ERR(priv->cru);
-#ifdef CONFIG_SPL_BUILD
ret = setup_sdram(dev);
if (ret)
return ret;
+#else
+ priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.size = rockchip_sdram_size(
+ (phys_addr_t)&priv->pmu->sys_reg[2]);
#endif
- priv->info.base = 0;
- priv->info.size = sdram_size_mb(priv->pmu) << 20;
return 0;
}
projects / people / ms / u-boot.git / blobdiff