powerpc: T1040: Remove macro CONFIG_PPC_T1040

[people/ms/u-boot.git] / arch / powerpc / include / asm / immap_85xx.h

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index c82c709e707bd12b3615bb6a57e24e22d875edae..4de9fd3389574d8d5f1682389d5b122a0e56f636 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1770,13 +1770,13 @@ typedef struct ccsr_gur {
 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL                0x000000f8
 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT  3
 #define FSL_CORENET_RCWSR6_BOOT_LOC    0x0f800000
-#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
+#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL        0xfe000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT  25
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL        0x00ff0000
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT  16
 #define FSL_CORENET_RCWSR6_BOOT_LOC    0x0f800000
-#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
+#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_PPC_T1042) ||\
 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL        0xff000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT  24
@@ -1797,7 +1797,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define PXCKEN_MASK    0x80000000
 #define PXCK_MASK      0x00FF0000
 #define PXCK_BITS_START        16
-#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) || \
+#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) || \
        defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL                0xff800000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT  23
@@ -1848,7 +1848,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define FSL_CORENET_RCWSR8_HOST_AGT_B1         0x00e00000
 #define FSL_CORENET_RCWSR8_HOST_AGT_B2         0x00100000
 #define FSL_CORENET_RCWSR11_EC1                        0x00c00000 /* bits 360..361 */
-#ifdef CONFIG_PPC_P4080
+#ifdef CONFIG_ARCH_P4080
 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1             0x00000000
 #define FSL_CORENET_RCWSR11_EC1_FM1_USB1               0x00800000
 #define FSL_CORENET_RCWSR11_EC2                        0x001c0000 /* bits 363..365 */
@@ -1856,8 +1856,8 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2             0x00080000
 #define FSL_CORENET_RCWSR11_EC2_USB2                   0x00100000
 #endif
-#if defined(CONFIG_PPC_P2041) \
-       || defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020)
+#if defined(CONFIG_ARCH_P2041) || \
+       defined(CONFIG_ARCH_P3041) || defined(CONFIG_ARCH_P5020)
 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII       0x00000000
 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII         0x00800000
 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE                0x00c00000
@@ -1866,7 +1866,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII         0x00100000
 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE                0x00180000
 #endif
-#if defined(CONFIG_PPC_P5040)
+#if defined(CONFIG_ARCH_P5040)
 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII        0x00000000
 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII          0x00800000
 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE         0x00c00000
@@ -2488,7 +2488,7 @@ typedef struct ccsr_gur {
        u8      res11a[76];
        par_io_t qe_par_io[7];
        u8      res11b[1600];
-#elif defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#elif defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
        u8      res11a[12];
        u32     iovselsr;
        u8      res11b[60];
@@ -2883,8 +2883,8 @@ struct ccsr_pman {
 #define CONFIG_SYS_MPC85xx_TDM_OFFSET          0x185000
 #define CONFIG_SYS_MPC85xx_QE_OFFSET           0x140000
 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET     0x1e0000
-#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\
-       && !defined(CONFIG_PPC_B4420)
+#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \
+       !defined(CONFIG_ARCH_B4420)
 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET                0x240000
 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET                0x250000
 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET                0x260000
@@ -2940,7 +2940,7 @@ struct ccsr_pman {
 #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET                0x9000
 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET         0xa000
 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET         0x9000
-#if defined(CONFIG_ARCH_MPC8572) || defined(CONFIG_P2020)
+#if defined(CONFIG_ARCH_MPC8572) || defined(CONFIG_ARCH_P2020)
 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET         0x8000
 #else
 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET         0xb000