env: Rename getenv/_f() to env_get()

[people/ms/u-boot.git] / board / freescale / t4qds / t4240qds.c

diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c
index 0c1a4fbd9ff7b4f6a44656f740290a8e15f23f15..2bdd6a349d7991af5e9f0ea2f9218ada5a6fca7a 100644 (file)
--- a/board/freescale/t4qds/t4240qds.c
+++ b/board/freescale/t4qds/t4240qds.c
@@ -15,7 +15,6 @@
 #include <asm/immap_85xx.h>
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
-#include <asm/fsl_portals.h>
 #include <asm/fsl_liodn.h>
 #include <fm_eth.h>
 
@@ -266,7 +265,7 @@ static int adjust_vdd(ulong vdd_override)
        vdd_target = vdd[vid];
 
        /* check override variable for overriding VDD */
-       vdd_string = getenv("t4240qds_vdd_mv");
+       vdd_string = env_get("t4240qds_vdd_mv");
        if (vdd_override == 0 && vdd_string &&
            !strict_strtoul(vdd_string, 10, &vdd_string_override))
                vdd_override = vdd_string_override;
@@ -354,14 +353,18 @@ int config_frontside_crossbar_vsc3316(void)
                        FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
        srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
        switch (srds_prtcl_s1) {
+       case 37:
        case 38:
                /* swap first lane and third lane on slot1 */
                vsc3316_fsm1_tx[0][1] = 14;
                vsc3316_fsm1_tx[6][1] = 0;
                vsc3316_fsm1_rx[1][1] = 2;
                vsc3316_fsm1_rx[6][1] = 13;
+       case 39:
        case 40:
+       case 45:
        case 46:
+       case 47:
        case 48:
                /* swap first lane and third lane on slot2 */
                vsc3316_fsm1_tx[2][1] = 8;
@@ -382,17 +385,24 @@ int config_frontside_crossbar_vsc3316(void)
                                FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
        srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
        switch (srds_prtcl_s2) {
+       case 37:
        case 38:
                /* swap first lane and third lane on slot3 */
                vsc3316_fsm2_tx[2][1] = 11;
                vsc3316_fsm2_tx[5][1] = 4;
                vsc3316_fsm2_rx[2][1] = 9;
                vsc3316_fsm2_rx[4][1] = 7;
+       case 39:
        case 40:
+       case 45:
        case 46:
+       case 47:
        case 48:
+       case 49:
        case 50:
+       case 51:
        case 52:
+       case 53:
        case 54:
                /* swap first lane and third lane on slot4 */
                vsc3316_fsm2_tx[6][1] = 3;
@@ -425,6 +435,7 @@ int config_backside_crossbar_mux(void)
        case 0:
                /* SerDes3 is not enabled */
                break;
+       case 1:
        case 2:
        case 9:
        case 10:
@@ -434,13 +445,20 @@ int config_backside_crossbar_mux(void)
                brdcfg |= BRDCFG12_SD3MX_SLOT5;
                QIXIS_WRITE(brdcfg[12], brdcfg);
                break;
+       case 3:
        case 4:
+       case 5:
        case 6:
+       case 7:
        case 8:
+       case 11:
        case 12:
+       case 13:
        case 14:
+       case 15:
        case 16:
        case 17:
+       case 18:
        case 19:
        case 20:
                /* SD3(4:7) => SLOT6(0:3) */
@@ -462,6 +480,7 @@ int config_backside_crossbar_mux(void)
        case 0:
                /* SerDes4 is not enabled */
                break;
+       case 1:
        case 2:
                /* 10b, SD4(0:7) => SLOT7(0:7) */
                brdcfg = QIXIS_READ(brdcfg[12]);
@@ -469,8 +488,11 @@ int config_backside_crossbar_mux(void)
                brdcfg |= BRDCFG12_SD4MX_SLOT7;
                QIXIS_WRITE(brdcfg[12], brdcfg);
                break;
+       case 3:
        case 4:
+       case 5:
        case 6:
+       case 7:
        case 8:
                /* x1b, SD4(4:7) => SLOT8(0:3) */
                brdcfg = QIXIS_READ(brdcfg[12]);
@@ -478,9 +500,13 @@ int config_backside_crossbar_mux(void)
                brdcfg |= BRDCFG12_SD4MX_SLOT8;
                QIXIS_WRITE(brdcfg[12], brdcfg);
                break;
+       case 9:
        case 10:
+       case 11:
        case 12:
+       case 13:
        case 14:
+       case 15:
        case 16:
        case 18:
                /* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */
@@ -501,7 +527,7 @@ int config_backside_crossbar_mux(void)
 int board_early_init_r(void)
 {
        const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
-       const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+       int flash_esel = find_tlb_idx((void *)flashbase, 1);
 
        /*
         * Remap Boot flash + PROMJET region to caching-inhibited
@@ -512,18 +538,19 @@ int board_early_init_r(void)
        flush_dcache();
        invalidate_icache();
 
-       /* invalidate existing TLB entry for flash + promjet */
-       disable_tlb(flash_esel);
+       if (flash_esel == -1) {
+               /* very unlikely unless something is messed up */
+               puts("Error: Could not find TLB for FLASH BASE\n");
+               flash_esel = 2; /* give our best effort to continue */
+       } else {
+               /* invalidate existing TLB entry for flash + promjet */
+               disable_tlb(flash_esel);
+       }
 
        set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
                MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                0, flash_esel, BOOKE_PAGESZ_256M, 1);
 
-       set_liodns();
-#ifdef CONFIG_SYS_DPAA_QBMAN
-       setup_portals();
-#endif
-
        /* Disable remote I2C connection to qixis fpga */
        QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
 
@@ -608,28 +635,13 @@ unsigned long get_board_ddr_clk(void)
        return 66666666;
 }
 
-static const char *serdes_clock_to_string(u32 clock)
-{
-       switch (clock) {
-       case SRDS_PLLCR0_RFCK_SEL_100:
-               return "100";
-       case SRDS_PLLCR0_RFCK_SEL_125:
-               return "125";
-       case SRDS_PLLCR0_RFCK_SEL_156_25:
-               return "156.25";
-       case SRDS_PLLCR0_RFCK_SEL_161_13:
-               return "161.1328125";
-       default:
-               return "???";
-       }
-}
-
 int misc_init_r(void)
 {
        u8 sw;
-       serdes_corenet_t *srds_regs =
-               (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+       void *srds_base = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+       serdes_corenet_t *srds_regs;
        u32 actual[MAX_SERDES];
+       u32 pllcr0, expected;
        unsigned int i;
 
        sw = QIXIS_READ(brdcfg[2]);
@@ -652,8 +664,9 @@ int misc_init_r(void)
        }
 
        for (i = 0; i < MAX_SERDES; i++) {
-               u32 pllcr0 = srds_regs->bank[i].pllcr0;
-               u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
+               srds_regs = srds_base + i * 0x1000;
+               pllcr0 = srds_regs->bank[0].pllcr0;
+               expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
                if (expected != actual[i]) {
                        printf("Warning: SERDES%u expects reference clock %sMHz, but actual is %sMHz\n",
                               i + 1, serdes_clock_to_string(expected),
@@ -664,7 +677,7 @@ int misc_init_r(void)
        return 0;
 }
 
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
 {
        phys_addr_t base;
        phys_size_t size;
@@ -681,12 +694,14 @@ void ft_board_setup(void *blob, bd_t *bd)
 #endif
 
        fdt_fixup_liodn(blob);
-       fdt_fixup_dr_usb(blob, bd);
+       fsl_fdt_fixup_dr_usb(blob, bd);
 
 #ifdef CONFIG_SYS_DPAA_FMAN
        fdt_fixup_fman_ethernet(blob);
        fdt_fixup_board_enet(blob);
 #endif
+
+       return 0;
 }
 
 /*