arm: Remove mx51_efikamx, mx51_efikasb boards

[people/ms/u-boot.git] / board / genesi / mx51_efikamx / imximage_mx.cfg

diff --git a/board/genesi/mx51_efikamx/imximage_mx.cfg b/board/genesi/mx51_efikamx/imximage_mx.cfg
deleted file mode 100644 (file)
index e2911eb..0000000
--- a/board/genesi/mx51_efikamx/imximage_mx.cfg
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * Copyright (C) 2009 Pegatron Corporation
- * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
- * Copyright (C) 2009-2012 Genesi USA, Inc.
- *
- * BASED ON: imx51evk
- *
- * (C) Copyright 2009
- * Stefano Babic DENX Software Engineering sbabic@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- *
- * Refer doc/README.imximage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-BOOT_FROM      spi
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type           Address        Value
- *
- * where:
- *     Addr-type register length (1,2 or 4 bytes)
- *     Address   absolute address of the register
- *     value     value to be stored in the register
- */
-/*
- * Essential GPIO settings to be done as early as possible
- * PCBIDn pad settings are all the defaults except #2 which needs HVE off
- */
-DATA 4 0x73fa8134 0x3                  # PCBID0 ALT3 GPIO 3_16
-DATA 4 0x73fa8130 0x3                  # PCBID1 ALT3 GPIO 3_17
-DATA 4 0x73fa8128 0x3                  # PCBID2 ALT3 GPIO 3_11
-DATA 4 0x73fa8504 0xe4                 # PCBID2 PAD ~HVE
-DATA 4 0x73fa8198 0x3                  # LED0 ALT3 GPIO 3_13
-DATA 4 0x73fa81c4 0x3                  # LED1 ALT3 GPIO 3_14
-DATA 4 0x73fa81c8 0x3                  # LED2 ALT3 GPIO 3_15
-
-/* DDR bus IOMUX PAD settings */
-DATA 4 0x73fa850c 0x20c5               # SDODT1
-DATA 4 0x73fa8510 0x20c5               # SDODT0
-DATA 4 0x73fa84ac 0xc5                 # SDWE
-DATA 4 0x73fa84b0 0xc5                 # SDCKE0
-DATA 4 0x73fa84b4 0xc5                 # SDCKE1
-DATA 4 0x73fa84cc 0xc5                 # DRAM_CS0
-DATA 4 0x73fa84d0 0xc5                 # DRAM_CS1
-DATA 4 0x73fa882c 0x2                  # DRAM_B4
-DATA 4 0x73fa88a4 0x2                  # DRAM_B0
-DATA 4 0x73fa88ac 0x2                  # DRAM_B1
-DATA 4 0x73fa88b8 0x2                  # DRAM_B2
-DATA 4 0x73fa84d4 0xc5                 # DRAM_DQM0
-DATA 4 0x73fa84d8 0xc5                 # DRAM_DQM1
-DATA 4 0x73fa84dc 0xc5                 # DRAM_DQM2
-DATA 4 0x73fa84e0 0xc5                 # DRAM_DQM3
-
-/*
- * Setting DDR for micron
- * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
- * CAS=3 BL=4
- */
-/* ESDCTL_ESDCTL0 */
-DATA 4 0x83fd9000 0x82a20000
-/* ESDCTL_ESDCTL1 */
-DATA 4 0x83fd9008 0x82a20000
-/* ESDCTL_ESDMISC */
-DATA 4 0x83fd9010 0xcaaaf6d0
-/* ESDCTL_ESDCFG0 */
-DATA 4 0x83fd9004 0x3f3574aa
-/* ESDCTL_ESDCFG1 */
-DATA 4 0x83fd900c 0x3f3574aa
-
-/* Init DRAM on CS0 */
-/* ESDCTL_ESDSCR */
-DATA 4 0x83fd9014 0x04008008
-DATA 4 0x83fd9014 0x0000801a
-DATA 4 0x83fd9014 0x0000801b
-DATA 4 0x83fd9014 0x00448019
-DATA 4 0x83fd9014 0x07328018
-DATA 4 0x83fd9014 0x04008008
-DATA 4 0x83fd9014 0x00008010
-DATA 4 0x83fd9014 0x00008010
-DATA 4 0x83fd9014 0x06328018
-DATA 4 0x83fd9014 0x03808019
-DATA 4 0x83fd9014 0x00408019
-DATA 4 0x83fd9014 0x00008000
-
-/* Init DRAM on CS1 */
-DATA 4 0x83fd9014 0x0400800c
-DATA 4 0x83fd9014 0x0000801e
-DATA 4 0x83fd9014 0x0000801f
-DATA 4 0x83fd9014 0x0000801d
-DATA 4 0x83fd9014 0x0732801c
-DATA 4 0x83fd9014 0x0400800c
-DATA 4 0x83fd9014 0x00008014
-DATA 4 0x83fd9014 0x00008014
-DATA 4 0x83fd9014 0x0632801c
-DATA 4 0x83fd9014 0x0380801d
-DATA 4 0x83fd9014 0x0040801d
-DATA 4 0x83fd9014 0x00008004
-
-/* Write to CTL0 */
-DATA 4 0x83fd9000 0xb2a20000
-/* Write to CTL1 */
-DATA 4 0x83fd9008 0xb2a20000
-/* ESDMISC */
-DATA 4 0x83fd9010 0x000ad6d0
-/* ESDCTL_ESDCDLYGD */
-DATA 4 0x83fd9034 0x90000000
-DATA 4 0x83fd9014 0x00000000