MIPS: Split I & D cache line size config

[people/ms/u-boot.git] / board / tplink / wdr4300 / Kconfig

diff --git a/board/tplink/wdr4300/Kconfig b/board/tplink/wdr4300/Kconfig
index ded7f9b1798dfdd2bae10a13dfc4189b10fda016..67a0228773ba4ddce3d1ae05e5cb0ffcfaf6f65a 100644 (file)
--- a/board/tplink/wdr4300/Kconfig
+++ b/board/tplink/wdr4300/Kconfig
@@ -18,10 +18,13 @@ config SYS_TEXT_BASE
 config SYS_DCACHE_SIZE
        default 32768
 
+config SYS_DCACHE_LINE_SIZE
+       default 32
+
 config SYS_ICACHE_SIZE
        default 65536
 
-config SYS_CACHELINE_SIZE
+config SYS_ICACHE_LINE_SIZE
        default 32
 
 endif