Add support for the Infineon XC16X.

[thirdparty/binutils-gdb.git] / cpu / ChangeLog

diff --git a/cpu/ChangeLog b/cpu/ChangeLog
index f2d1d7d4203e085cecfa6d10ce7ffc37637d79d0..0efd530321ea4185949dc1a9041d8e9482aaba9a 100644 (file)
--- a/cpu/ChangeLog
+++ b/cpu/ChangeLog
@@ -1,3 +1,36 @@
+2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
+            Anil Paranjape   <anilp1@kpitcummins.com>
+            Shilin Shakti    <shilins@kpitcummins.com>
+
+       * xc16x.cpu: New file containing complete CGEN specific XC16X CPU
+       description.
+       * xc16x.opc: New file containing supporting XC16C routines.
+
+2006-02-10  Nick Clifton  <nickc@redhat.com>
+
+       * iq2000.opc (parse_hi16): Truncate shifted values to 16 bits.
+
+2006-01-06  DJ Delorie  <dj@redhat.com>
+
+       * m32c.cpu (mov.w:q): Fix mode.
+       (push32.b.imm): Likewise, for the comment.
+
+2005-12-16  Nathan Sidwell  <nathan@codesourcery.com>
+
+       Second part of ms1 to mt renaming.
+       * mt.cpu (define-arch, define-isa): Set name to mt.
+       (define-mach): Adjust.
+       * mt.opc (CGEN_ASM_HASH): Update.
+       (mt_asm_hash, mt_cgen_insn_supported): Renamed.
+       (parse_loopsize, parse_imm16): Adjust.
+
+2005-12-13  DJ Delorie  <dj@redhat.com>
+
+       * m32c.cpu (jsri): Fix order so register names aren't treated as
+       symbols.
+       (indexb, indexbd, indexbs, indexl, indexld, indexls, indexw,
+       indexwd, indexws): Fix encodings.
+
 2005-12-12  Nathan Sidwell  <nathan@codesourcery.com>
 
        * mt.cpu: Rename from ms1.cpu.