drm/amd/display: Fix 4to1 MPC black screen with DPP RCO

[thirdparty/kernel/stable.git] / drivers / gpu / drm / amd / display / dc / dcn31 / dcn31_dccg.c

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
index 7f34418e63081810335c40ee0bdeabcb1f648989..7d2b982506fd7ba9e820002cbee2a74e23adc461 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
@@ -66,17 +66,8 @@ void dccg31_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)
                REG_UPDATE(DPPCLK_DTO_CTRL,
                                DPPCLK_DTO_ENABLE[dpp_inst], 1);
        } else {
-               //DTO must be enabled to generate a 0Hz clock output
-               if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp) {
-                       REG_UPDATE(DPPCLK_DTO_CTRL,
-                                       DPPCLK_DTO_ENABLE[dpp_inst], 1);
-                       REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
-                                       DPPCLK0_DTO_PHASE, 0,
-                                       DPPCLK0_DTO_MODULO, 1);
-               } else {
-                       REG_UPDATE(DPPCLK_DTO_CTRL,
-                                       DPPCLK_DTO_ENABLE[dpp_inst], 0);
-               }
+               REG_UPDATE(DPPCLK_DTO_CTRL,
+                               DPPCLK_DTO_ENABLE[dpp_inst], 0);
        }
        dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;
 }