usb: replace ehci_*_remove() with usb_deregister()

[people/ms/u-boot.git] / drivers / usb / host / ehci-marvell.c

diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c
index 03c489c014a482eb4f7c66dcc0fbd962f4110ba1..253fcb3c9621fb8aa129ecb0f7d1c0dbc9e50023 100644 (file)
--- a/drivers/usb/host/ehci-marvell.c
+++ b/drivers/usb/host/ehci-marvell.c
@@ -12,6 +12,7 @@
 #include "ehci.h"
 #include <linux/mbus.h>
 #include <asm/arch/cpu.h>
+#include <dm.h>
 
 #if defined(CONFIG_KIRKWOOD)
 #include <asm/arch/soc.h>
@@ -21,9 +22,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define rdl(off)       readl(MVUSB0_BASE + (off))
-#define wrl(off, val)  writel((val), MVUSB0_BASE + (off))
-
 #define USB_WINDOW_CTRL(i)     (0x320 + ((i) << 4))
 #define USB_WINDOW_BASE(i)     (0x324 + ((i) << 4))
 #define USB_TARGET_DRAM                0x0
@@ -31,16 +29,19 @@ DECLARE_GLOBAL_DATA_PTR;
 /*
  * USB 2.0 Bridge Address Decoding registers setup
  */
-#ifdef CONFIG_ARMADA_XP
+#ifdef CONFIG_DM_USB
 
-#define MVUSB0_BASE            MVEBU_USB20_BASE
+struct ehci_mvebu_priv {
+       struct ehci_ctrl ehci;
+       fdt_addr_t hcd_base;
+};
 
 /*
  * Once all the older Marvell SoC's (Orion, Kirkwood) are converted
  * to the common mvebu archticture including the mbus setup, this
  * will be the only function needed to configure the access windows
  */
-static void usb_brg_adrdec_setup(void)
+static void usb_brg_adrdec_setup(u32 base)
 {
        const struct mbus_dram_target_info *dram;
        int i;
@@ -48,24 +49,72 @@ static void usb_brg_adrdec_setup(void)
        dram = mvebu_mbus_dram_info();
 
        for (i = 0; i < 4; i++) {
-               wrl(USB_WINDOW_CTRL(i), 0);
-               wrl(USB_WINDOW_BASE(i), 0);
+               writel(0, base + USB_WINDOW_CTRL(i));
+               writel(0, base + USB_WINDOW_BASE(i));
        }
 
        for (i = 0; i < dram->num_cs; i++) {
                const struct mbus_dram_window *cs = dram->cs + i;
 
                /* Write size, attributes and target id to control register */
-               wrl(USB_WINDOW_CTRL(i),
-                   ((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
-                   (dram->mbus_dram_target_id << 4) | 1);
+               writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
+                      (dram->mbus_dram_target_id << 4) | 1,
+                      base + USB_WINDOW_CTRL(i));
 
                /* Write base address to base register */
-               wrl(USB_WINDOW_BASE(i), cs->base);
+               writel(cs->base, base + USB_WINDOW_BASE(i));
        }
 }
+
+static int ehci_mvebu_probe(struct udevice *dev)
+{
+       struct ehci_mvebu_priv *priv = dev_get_priv(dev);
+       struct ehci_hccr *hccr;
+       struct ehci_hcor *hcor;
+
+       /*
+        * Get the base address for EHCI controller from the device node
+        */
+       priv->hcd_base = dev_get_addr(dev);
+       if (priv->hcd_base == FDT_ADDR_T_NONE) {
+               debug("Can't get the EHCI register base address\n");
+               return -ENXIO;
+       }
+
+       usb_brg_adrdec_setup(priv->hcd_base);
+
+       hccr = (struct ehci_hccr *)(priv->hcd_base + 0x100);
+       hcor = (struct ehci_hcor *)
+               ((u32)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+       debug("ehci-marvell: init hccr %x and hcor %x hc_length %d\n",
+             (u32)hccr, (u32)hcor,
+             (u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+       return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
+}
+
+static const struct udevice_id ehci_usb_ids[] = {
+       { .compatible = "marvell,orion-ehci", },
+       { }
+};
+
+U_BOOT_DRIVER(ehci_mvebu) = {
+       .name   = "ehci_mvebu",
+       .id     = UCLASS_USB,
+       .of_match = ehci_usb_ids,
+       .probe = ehci_mvebu_probe,
+       .remove = ehci_deregister,
+       .ops    = &ehci_usb_ops,
+       .platdata_auto_alloc_size = sizeof(struct usb_platdata),
+       .priv_auto_alloc_size = sizeof(struct ehci_mvebu_priv),
+       .flags  = DM_FLAG_ALLOC_PRIV_DMA,
+};
+
 #else
-static void usb_brg_adrdec_setup(void)
+#define MVUSB_BASE(port)       MVUSB0_BASE
+
+static void usb_brg_adrdec_setup(int index)
 {
        int i;
        u32 size, base, attrib;
@@ -95,16 +144,16 @@ static void usb_brg_adrdec_setup(void)
                size = gd->bd->bi_dram[i].size;
                base = gd->bd->bi_dram[i].start;
                if ((size) && (attrib))
-                       wrl(USB_WINDOW_CTRL(i),
-                               MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
-                                       attrib, MVCPU_WIN_ENABLE));
+                       writel(MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
+                                                  attrib, MVCPU_WIN_ENABLE),
+                               MVUSB0_BASE + USB_WINDOW_CTRL(i));
                else
-                       wrl(USB_WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
+                       writel(MVCPU_WIN_DISABLE,
+                              MVUSB0_BASE + USB_WINDOW_CTRL(i));
 
-               wrl(USB_WINDOW_BASE(i), base);
+               writel(base, MVUSB0_BASE + USB_WINDOW_BASE(i));
        }
 }
-#endif
 
 /*
  * Create the appropriate control structures to manage
@@ -113,9 +162,9 @@ static void usb_brg_adrdec_setup(void)
 int ehci_hcd_init(int index, enum usb_init_type init,
                struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
-       usb_brg_adrdec_setup();
+       usb_brg_adrdec_setup(index);
 
-       *hccr = (struct ehci_hccr *)(MVUSB0_BASE + 0x100);
+       *hccr = (struct ehci_hccr *)(MVUSB_BASE(index) + 0x100);
        *hcor = (struct ehci_hcor *)((uint32_t) *hccr
                        + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
 
@@ -134,3 +183,5 @@ int ehci_hcd_stop(int index)
 {
        return 0;
 }
+
+#endif /* CONFIG_DM_USB */