+2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
+ Matthew Fortune <matthew.fortune@imgtec.com>
+
+ * config/tc-mips.c (validate_mips_insn): Handle
+ OP_SAVE_RESTORE_LIST specially.
+ (mips_encode_save_restore, mips16_encode_save_restore): New
+ functions.
+ (match_save_restore_list_operand): Factor out SAVE/RESTORE
+ operand insertion into the instruction word or halfword to these
+ new functions.
+ (mips_cpu_info_table): Add "interaptiv-mr2" entry.
+
+ * doc/c-mips.texi (MIPS Options): Add `interaptiv-mr2' to the
+ `-march=' argument list.
+
+2017-06-27 Maciej W. Rozycki <macro@imgtec.com>
+
+ * testsuite/gas/mips/mips16e-save.d: Rename to...
+ * testsuite/gas/mips/save.d: ... this.
+ * testsuite/gas/mips/mips16e-save-err.d: Update the
+ `error-output' option and rename to...
+ * testsuite/gas/mips/save-err.d: ... this.
+ * testsuite/gas/mips/mips16e-save-err.l: Rename to...
+ * testsuite/gas/mips/save-err.l: ... this.
+ * testsuite/gas/mips/mips16e-save.s: Rename to...
+ * testsuite/gas/mips/save.s: ... this.
+ * testsuite/gas/mips/mips16e-save-err.s: Rename to...
+ * testsuite/gas/mips/save-err.s: ... this.
+ * testsuite/gas/mips/mips.exp: Rename `mips16e-save' and
+ `mips16e-save-err' invocations to `save' and `save-err'
+ respectively and reorder these tests away from MIPS16 tests.
+
+2017-06-27 Maciej W. Rozycki <macro@imgtec.com>
+
+ * testsuite/gas/mips/mips16e-save.d: Remove `-mmips:isa32
+ -mmips:16' from `objdump' flags and `-march=mips32 -mips16' from
+ `as' flags.
+ * testsuite/gas/mips/mips16e-save-err.d: Remove `-march=mips32'
+ from `as' flags.
+ * testsuite/gas/mips/mips16e-save.s: Remove the `.set mips16'
+ pseudo-op.
+ * testsuite/gas/mips/mips16e-save-err.s: Likewise.
+ * testsuite/gas/mips/mips.exp: Run SAVE/RESTORE tests across all
+ MIPS16e architectures.
+
+2017-06-27 Maciej W. Rozycki <macro@imgtec.com>
+
+ * testsuite/gas/mips/mips16e-save-err.d: New test.
+ * gas/testsuite/gas/mips/mips.exp: Fold `mips16e-save-err' list
+ test into the new test.
+
+2017-06-27 Maciej W. Rozycki <macro@imgtec.com>
+
+ * testsuite/gas/mips/mips16e-save.d: Capitalize the `name'
+ option.
+
+2017-06-26 Kuan-Lin Chen <rufus@andestech.com>
+
+ * config/tc-riscv.c (md_apply_fix) [BFD_RELOC_32]: Convert to a
+ R_RISCV_32_PCREL relocation.
+
+2017-06-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/21661
+ * config/obj-elf.c (obj_elf_symver): Don't allow .symver with
+ common symbol.
+ (elf_frob_symbol): Likewise.
+ * testsuite/gas/elf/elf.exp: Run pr21661.
+ * testsuite/gas/elf/pr21661.d: New file.
+ * testsuite/gas/elf/pr21661.s: Likewise.
+
+2017-06-26 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-arm.c (fpu_any): Only define for ELF based targets.
+
+2017-06-26 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * /config/tc-arc.c (is_br_jmp_insn_p): Update macro with known
+ instructions to be accounted as jumps.
+ (assemble_insn): Check for limms into the delay slots. Emit an
+ error if so.
+ * testsuite/gas/arc/asm-errors-3.d: New file.
+ * testsuite/gas/arc/asm-errors-3.err: Likewise.
+ * testsuite/gas/arc/asm-errors-3.s: Likewise.
+
+2017-06-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * NEWS: Mention support of ARM Cortex-R52 processor.
+ * config/tc-arm.c (arm_cpus): Add entry for ARM Cortex-R52 processor.
+ * doc/c-arm.texi: Mention support for -mcpu=cortex-r52.
+
+2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * NEWS: Mention support for ARMv8-R architecture.
+ * config/tc-arm.c (arm_archs): Add entry for ARMv8-R.
+ (arm_extensions): Restrict pan, ras and rdma extension to
+ ARMv8-A and make crypto, fp and simd extensions available to
+ ARMv8-R.
+ (cpu_arch_ver): Add entry for ARMv8-R.
+ (aeabi_set_public_attributes): Update gas_assert for Tag_DIV_use
+ logic.
+ * testsuite/gas/arm/armv8-a+fp.s: Rename into ...
+ * testsuite/gas/arm/armv8-ar+fp.s: This. Remove .arch directive.
+ * testsuite/gas/arm/armv8-a+fp.d: Specify source to assemble and
+ architecture to assemble for.
+ * testsuite/gas/arm/armv8-r+fp.d: New.
+ * testsuite/gas/arm/armv8-a+simd.s: Rename into ...
+ * testsuite/gas/arm/armv8-ar+simd.s: This. Remove .arch directive.
+ * testsuite/gas/arm/armv8-a+simd.d: Specify source to assemble and
+ architecture to assemble for.
+ * testsuite/gas/arm/armv8-r+simd.d: New.
+ * testsuite/gas/arm/armv8-a-bad.s: Rename into ...
+ * testsuite/gas/arm/armv8-ar-bad.s: This. Remove .arch directive.
+ * testsuite/gas/arm/armv8-a-bad.l: Rename into ...
+ * testsuite/gas/arm/armv8-ar-bad.l: This. Decrement line number by 1.
+ * testsuite/gas/arm/armv8-a-bad.d: Specify source to assemble,
+ architecture to assemble for and adjust error output file.
+ * testsuite/gas/arm/armv8-r-bad.d: New.
+ * testsuite/gas/arm/armv8-a-barrier.s: Rename into ...
+ * testsuite/gas/arm/armv8-ar-barrier.s: This.
+ * testsuite/gas/arm/armv8-a-barrier-arm.d: Adjust source.
+ * testsuite/gas/arm/armv8-a-barrier-thumb.d: Likewise.
+ * testsuite/gas/arm/armv8-r-barrier-arm.d: New.
+ * testsuite/gas/arm/armv8-r-barrier-thumb.d: New.
+ * testsuite/gas/arm/armv8-a-it-bad.s: Rename into ...
+ * testsuite/gas/arm/armv8-ar-it-bad.s: This. Remove .arch directive.
+ * testsuite/gas/arm/armv8-a-it-bad.l: Rename into ...
+ * testsuite/gas/arm/armv8-ar-it-bad.l: This. Decrement line number
+ by 1.
+ * testsuite/gas/arm/armv8-a-it-bad.d: Specify source to assemble,
+ architecture to assemble for and adjust error output file.
+ * testsuite/gas/arm/armv8-r-it-bad.d: New.
+ * testsuite/gas/arm/armv8-a.s: Rename into ...
+ * testsuite/gas/arm/armv8-ar.s: This. Remove .arch directive.
+ * testsuite/gas/arm/armv8-a.d: Specify source to assemble and
+ architecture to assemble for.
+ * testsuite/gas/arm/armv8-r.d: New.
+ * testsuite/gas/arm/attr-march-armv8-r+crypto.d: New.
+ * testsuite/gas/arm/attr-march-armv8-r+fp.d: New.
+ * testsuite/gas/arm/attr-march-armv8-r+simd.d: New.
+ * testsuite/gas/arm/attr-march-armv8-r.d: New.
+ * testsuite/gas/arm/crc32.s: Rename into ...
+ * testsuite/gas/arm/crc32-armv8-ar.s: This.
+ * testsuite/gas/arm/crc32.d: Rename into ...
+ * testsuite/gas/arm/crc32-armv8-a.d: This. Specify source to assemble.
+ * testsuite/gas/arm/crc32-armv8-r.d: New.
+ * testsuite/gas/arm/crc32-bad.s: Rename into ...
+ * testsuite/gas/arm/crc32-armv8-ar-bad.s: This.
+ * testsuite/gas/arm/crc32-bad.d: Rename into ...
+ * testsuite/gas/arm/crc32-armv8-a-bad.d: This. Specify source to
+ assemble.
+ * testsuite/gas/arm/crc32-armv8-r-bad.d: New.
+ * testsuite/gas/arm/mask_1.s: Rename into ...
+ * testsuite/gas/arm/mask_1-armv8-ar.s: This.
+ * testsuite/gas/arm/mask_1.d: Rename into ...
+ * testsuite/gas/arm/mask_1-armv8-a.d: This. Specify source to
+ assemble.
+ * testsuite/gas/arm/mask_1-armv8-r.d: new.
+
+2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (arm_ext_v6m): Delete.
+ (arm_ext_v7m): Delete.
+ (arm_ext_m): Remove ARM_EXT_OS from the set of feature defined M
+ profile.
+ (arm_arch_v6m_only): Delete.
+ (do_t_swi): Remove special case for ARMv6S-M.
+ (md_assemble): Display error message previously in do_t_swi when
+ SVC is not available.
+ (insns): Guard swi and svc by arm_ext_os for Thumb mode.
+ (aeabi_set_public_attributes): Remove special case for ARMv6S-M.
+
+2017-05-11 Andrew Waterman <andrew@sifive.com>
+
+ * config/tc-riscv.c (riscv_ip): Changes as_warn to as_bad for improper
+ shift amounts.
+
+2017-06-22 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-arm.c (arm_ext_v7m): Add ATTRIBUTE_UNUSED.
+
+2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (fpu_any): Defined from FPU_ANY.
+ (cpu_arch_ver): Add all architectures and sort by release date.
+ (have_ext_for_needed_feat_p): New.
+ (get_aeabi_cpu_arch_from_fset): New.
+ (aeabi_set_public_attributes): Call above function to determine
+ Tag_CPU_arch and Tag_CPU_arch_profile values. Adapt Tag_ARM_ISA_use
+ and Tag_THUMB_ISA_use selection logic to check absence of feature bit
+ accordingly.
+ * testsuite/gas/arm/attr-march-armv1.d: Fix expected Tag_CPU_arch build
+ attribute value.
+ * testsuite/gas/arm/attr-march-armv2.d: Likewise.
+ * testsuite/gas/arm/attr-march-armv2a.d: Likewise.
+ * testsuite/gas/arm/attr-march-armv2s.d: Likewise.
+ * testsuite/gas/arm/attr-march-armv3.d: Likewise.
+ * testsuite/gas/arm/attr-march-armv3m.d: Likewise.
+ * testsuite/gas/arm/pr12198-2.d: Likewise.
+
+2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
+
+ * testsuite/gas/i386/cet-intel.d: Updated.
+ * testsuite/gas/i386/cet.d: Likewise.
+ * testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
+ * testsuite/gas/i386/x86-64-cet.d: Likewise.
+ * testsuite/gas/i386/cet.s: Update incsspd and setssbsy tests.
+ * testsuite/gas/i386/x86-64-cet.s: Likewise.
+
+2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
+
+ * testsuite/gas/i386/cet-intel.d: Updated.
+ * testsuite/gas/i386/cet.d: Likewise.
+ * testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
+ * testsuite/gas/i386/x86-64-cet.d: Likewise.
+ * testsuite/gas/i386/cet.s: Replace savessp with saveprevssp.
+ * testsuite/gas/i386/x86-64-cet.s: Likewise.
+
+2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (md_assemble): Update NOTRACK prefix check.
+ * testsuite/gas/i386/notrack-intel.d: Updated.
+ * testsuite/gas/i386/notrack.d: Likewise.
+ * testsuite/gas/i386/notrackbad.l: Likewise.
+ * testsuite/gas/i386/x86-64-notrack-intel.d: Likewise.
+ * testsuite/gas/i386/x86-64-notrack.d: Likewise.
+ * testsuite/gas/i386/x86-64-notrackbad.l: Likewise.
+ * testsuite/gas/i386/notrack.s: Add NOTRACK prefix tests with
+ memory indirect branch.
+ * testsuite/gas/i386/x86-64-notrack.s: Likewise.
+ * testsuite/gas/i386/notrackbad.s: Remove memory indirect branch
+ with NOTRACK prefix.
+ * testsuite/gas/i386/x86-64-notrackbad.s: Likewise.
+
+2017-06-20 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (arm_extensions): New duplicate idiv entry to enable
+ Thumb division for ARMv7 architecture.
+ (arm_parse_extension): Document expected behavior for duplicate
+ entries.
+ (s_arm_arch_extension): Likewise.
+ * testsuite/gas/arm/forbid-armv7-idiv-ext.d: New test.
+ * testsuite/gas/arm/forbid-armv7-idiv-ext.l: New expected output for
+ above test.
+
+2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (aeabi_set_public_attributes): Populate flags from
+ feature bits used or selected_cpu depending on whether a CPU was
+ selected by the user.
+
+2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (aeabi_set_public_attributes): Test *mcpu_ext_opt to
+ decide whether to set Tag_DSP_extension build attribute value. Remove
+ now useless arm_arch variable.
+
+2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (dyn_mcpu_ext_opt): New static variable.
+ (dyn_march_ext_opt): Likewise.
+ (md_begin): Copy extension feature bits alongside architecture ones.
+ Merge extensions feature bits in selected_cpu and cpu_variant if there
+ is some.
+ (arm_parse_extension): Pass architecture and extension feature bits in
+ separate parameters, with architecture bits being read only. Update
+ **opt_p directly rather than *ext_set and initialize it if needed.
+ (arm_parse_cpu): Stop merging architecture and extension feature bits
+ and instead use mcpu_cpu_opt and dyn_mcpu_ext_opt to memorize them
+ respectively. Adapt to change in parameters of arm_parse_extension.
+ (arm_parse_arch): Adapt to change in parameters of arm_parse_extension.
+ (aeabi_set_attribute_string): Make function static.
+ (arm_md_post_relax): New function.
+ (s_arm_cpu): Stop merging architecture and extension feature bits and
+ instead use mcpu_cpu_opt and dyn_mcpu_ext_opt to memorize them
+ respectively. Merge extension feature bits in cpu_variant
+ if there is any.
+ (s_arm_arch): Reset extension feature bit. Set selected_cpu from
+ *mcpu_cpu_opt and cpu_variant from selected_cpu and *mfpu_opt for
+ consistency with s_arm_cpu.
+ (s_arm_arch_extension): Update *dyn_mcpu_ext_opt rather than
+ selected_cpu, allocating it before hand if needed. Set selected_cpu
+ from it and then cpu_variant.
+ (s_arm_fpu): Merge *mcpu_ext_opt feature bits if any in cpu_variant.
+ * config/tc-arm.h (md_post_relax_hook): Set to arm_md_post_relax.
+ (aeabi_set_public_attributes): Delete external declaration.
+ (arm_md_post_relax): Declare externally.
+
+2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (struct arm_cpu_option_table): New ext field.
+ (ARM_CPU_OPT): Add parameter to set new ext field and reorder canonical
+ name field just after the name field.
+ (arm_cpus): Move extension feature bit from value field to ext field,
+ reorder parameter according to changes in ARM_CPU_OPT and reindent.
+ (arm_parse_cpu): Point mcpu_cpu_opt to a bitfield merging the value and
+ ext field from the selected arm_cpus entry.
+ (s_arm_cpu): Likewise.
+
+2017-06-21 James Greenhalgh <james.greenhalgh@arm.com>
+
+ * config/tc-aarch64.c (aarch64_cpus): Add cortex-a55 and cortex-a75.
+ * doc/c-aarch64.texi (-mcpu): Document cortex-a55 and cortex-a75.
+
+2017-06-15 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/21594
+ * testsuite/gas/i386/mpx.s: Add 2 tests with invalid bnd
+ register.
+ * testsuite/gas/i386/x86-64-mpx.s: Likewise.
+ * testsuite/gas/i386/mpx.d: Updated.
+ * testsuite/gas/i386/x86-64-mpx.d: Likewise.
+
+2017-06-14 Max Filippov <jcmvbkbc@gmail.com>
+
+ * config/tc-xtensa.c (density_supported, xtensa_fetch_width,
+ absolute_literals_supported): Leave definitions uninitialized.
+ (directive_state): Leave entries for directive_density and
+ directive_absolute_literals initialized to false.
+ (xg_init_global_config, xtensa_init): New functions.
+ * config/tc-xtensa.h (TARGET_BYTES_BIG_ENDIAN): Define as 0.
+ (HOST_SPECIAL_INIT): New definition.
+ (xtensa_init): New declaration.
+
+2017-06-07 Michael Collison <michael.collison@arm.com>
+
+ * config/tc-aarch64.c (reg_entry_reg_names): Add IP0,
+ IP1, FP, and LR as register aliases of register 16, 17, 29
+ and 30 respectively.
+ * testsuite/gas/aarch64/diagnostic.l: Remove diagnostic
+ prohibiting register 'lr' which is now an alias.
+ * testsuite/gas/aarch64/diagnostic.s: Remove instruction
+ utilizing register 'lr' which is now an alias.
+
+2017-06-06 Jiong Wang <jiong.wang@arm.com>
+
+ * config/tc-arm.c (reject_bad_reg): Allow REG_SP on ARMv8-A.
+ (parse_operands): Allow REG_SP for OP_oRRnpcsp and OP_RRnpcsp on
+ ARMv8-A.
+ (do_co_reg): Allow REG_SP for Rd on ARMv8-A.
+ (do_t_add_sub): Likewise.
+ (do_t_mov_cmp): Likewise.
+ (do_t_tb): Likewise.
+ * testsuite/gas/arm/ld-sp-warn.l: Delete the warning on REG_SP as Rt for
+ ldrsb.
+ * testsuite/gas/arm/sp-pc-validations-bad-t-v8a.d: New test.
+ * testsuite/gas/arm/sp-pc-validations-bad-t-v8a.l: New test.
+ * testsuite/gas/arm/sp-pc-validations-bad-t.d: Specifies -march=armv7-a.
+ * testsuite/gas/arm/sp-pc-validations-bad-t.s: Remove ".arch armv7-a".
+ * testsuite/gas/arm/sp-usage-thumb2-relax-on-v7.d: New test.
+ * testsuite/gas/arm/sp-usage-thumb2-relax-on-v7.l: New test.
+ * testsuite/gas/arm/sp-usage-thumb2-relax-on-v8.d: New test.
+ * testsuite/gas/arm/sp-usage-thumb2-relax.s: New test.
+ * testsuite/gas/arm/strex-bad-t.d: Specifies -march=armv7-a.
+
+2017-06-05 Jim Wilson <jim.wilson@linaro.org>
+
+ * config/tc-arm.c (arm_cpus): Delete falkor and qdf24xx entries.
+ * doc/c-arm.texi (-mcpu): Likewise.
+
+2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
+
+ * config/tc-arc.c (cpu_types): Include arc-cpu.def
+
+2017-05-23 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/testsuite/gas/i386/notrackbad.l: Updated for non-ELF
+ targets.
+ * gas/testsuite/gas/i386/x86-64-notrackbad.l: Likewise.
+
+2017-05-23 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * config/tc-arc.c (md_apply_fix): Use as_bad_where.
+ (assemble_insn): Use as_bad.
+
+2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (REX_PREFIX): Changed to 7.
+ (NOTRACK_PREFIX): New.
+ (MAX_PREFIXES): Changed to 8.
+ (_i386_insn): Add notrack_prefix.
+ (PREFIX_GROUP): Add PREFIX_DS.
+ (add_prefix): Return PREFIX_DS for DS_PREFIX_OPCODE.
+ (md_assemble): Check if NOTRACK prefix is supported.
+ (parse_insn): Set notrack_prefix and issue an error for
+ other prefixes after NOTRACK prefix.
+ * testsuite/gas/i386/i386.exp: Run tests for NOTRACK prefix.
+ * testsuite/gas/i386/notrack-intel.d: New file.
+ * testsuite/gas/i386/notrack.d: Likewise.
+ * testsuite/gas/i386/notrack.s: Likewise.
+ * testsuite/gas/i386/notrackbad.l: Likewise.
+ * testsuite/gas/i386/notrackbad.s: Likewise.
+ * testsuite/gas/i386/x86-64-notrack-intel.d: Likewise.
+ * testsuite/gas/i386/x86-64-notrack.d: Likewise.
+ * testsuite/gas/i386/x86-64-notrack.s: Likewise.
+ * testsuite/gas/i386/x86-64-notrackbad.l: Likewise.
+ * testsuite/gas/i386/x86-64-notrackbad.s: Likewise.
+
+2017-05-22 Jiong Wang <jiong.wang@arm.com>
+
+ * configure.tgt: Set "arch" to "aarch64" if ${cpu} equals "aarch64".
+ Recognize the new triplet name aarch64*-linux-gnu_ilp32.
+ * configure.ac: Output DEFAULT_ARCH macro for AArch64.
+ * configure: Regenerate.
+ * config/tc-aarch64.h (aarch64_after_parse_args): New declaration.
+ (md_after_parse_args): New define.
+ * config/tc-aarch64.c (aarch64_abi_type): New enumeration
+ AARCH64_ABI_NONE.
+ (DEFAULT_ARCH): New define.
+ (aarch64_abi): Set default value to AARCH64_ABI_NONE.
+ (aarch64_after_parse_args): New function.
+
+2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * config/tc-sparc.c (sparc_arch_table): Entries for `sparc6',
+ `v9m8' and `v8plusm8'.
+ (sparc_md_end): Handle SPARC_OPCODE_ARCH_M8.
+ (get_hwcap_name): Support the M8 hardware capabilities.
+ (sparc_ip): Handle new operand types.
+ * doc/c-sparc.texi (Sparc-Opts): Document -Av9m8, -Av8plusm8 and
+ -Asparc6, and the corresponding -xarch aliases.
+ * testsuite/gas/sparc/sparc6.s: New file.
+ * testsuite/gas/sparc/sparc6.d: Likewise.
+ * testsuite/gas/sparc/sparc6-diag.s: Likewise.
+ * testsuite/gas/sparc/sparc6-diag.l: Likewise.
+ * testsuite/gas/sparc/fpcmpshl.s: Likewise.
+ * testsuite/gas/sparc/fpcmpshl.d: Likewise.
+ * testsuite/gas/sparc/fpcmpshl-diag.s: Likewise.
+ * testsuite/gas/sparc/fpcmpshl-diag.l: Likewise.
+ * testsuite/gas/sparc/ldm-stm.s: Likewise.
+ * testsuite/gas/sparc/ldm-stm.d: Likewise.
+ * testsuite/gas/sparc/ldm-stm-diag.s: Likewise.
+ * testsuite/gas/sparc/ldm-stm-diag.l: Likewise.
+ * testsuite/gas/sparc/ldmf-stmf.s: Likewise.
+ * testsuite/gas/sparc/ldmf-stmf.d: Likewise.
+ * testsuite/gas/sparc/ldmf-stmf-diag.s: Likewise.
+ * testsuite/gas/sparc/ldmf-stmf-diag.l: Likewise.
+ * testsuite/gas/sparc/on.s: Likewise.
+ * testsuite/gas/sparc/on.d: Likewise.
+ * testsuite/gas/sparc/on-diag.s: Likewise.
+ * testsuite/gas/sparc/on-diag.l: Likewise.
+ * testsuite/gas/sparc/rle.s: Likewise.
+ * testsuite/gas/sparc/rle.d: Likewise.
+ * testsuite/gas/sparc/sparc.exp (gas_64_check): Run new tests.
+ * testsuite/gas/sparc/rdasr.s: Add test for RDENTROPY.
+ * testsuite/gas/sparc/rdasr.d: Likewise.
+
+2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * testsuite/gas/sparc/call-relax.d: Support 32-bit targets.
+ * testsuite/gas/sparc/sparc.exp (gas_64_check): Use -64 to
+ run asi-bump-warn.
+
+2017-05-19 Georg-Johann Lay <avr@gjlay.de>
+
+ PR ld/21472
+ * config/tc-avr.c (mcu_types): Add entries for: attiny416,
+ attiny417, attiny816, attiny817.
+
+2017-05-18 Alan Modra <amodra@gmail.com>
+
+ * config/tc-aarch64.c: Don't compare booleans against TRUE or FALSE.
+ * config/tc-hppa.c: Likewise.
+ * config/tc-mips.c: Likewise.
+ * config/tc-score7.c: Likewise.
+
+2017-05-16 Alan Modra <amodra@gmail.com>
+
+ * write.c (GENERIC_FORCE_RELOCATION_LOCAL): Define.
+ (TC_FORCE_RELOCATION_LOCAL): Use it.
+ (GENERIC_FORCE_RELOCATION_SUB_SAME): Define.
+ (TC_FORCE_RELOCATION_SUB_SAME): Use it.
+ * config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL,
+ TC_FORCE_RELOCATION_SUB_SAME): Use GENERIC defines.
+ * config/tc-aarch64.h: Similarly.
+ * config/tc-avr.h: Similarly.
+ * config/tc-cris.h: Similarly.
+ * config/tc-i386.h: Similarly.
+ * config/tc-i960.h: Similarly.
+ * config/tc-ia64.h: Similarly.
+ * config/tc-microblaze.h: Similarly.
+ * config/tc-mips.h: Similarly.
+ * config/tc-msp430.h: Similarly.
+ * config/tc-nds32.h: Similarly.
+ * config/tc-pru.h: Similarly.
+ * config/tc-riscv.h: Similarly.
+ * config/tc-rl78.h: Similarly.
+ * config/tc-s390.h: Similarly.
+ * config/tc-sh.h: Similarly.
+ * config/tc-sh64.h: Similarly.
+ * config/tc-sparc.h: Similarly.
+ * config/tc-xtensa.h: Similarly.
+ * config/tc-mn10300.h: Similarly.
+ (GENERIC_FORCE_RELOCATION_LOCAL): Define.
+ * config/tc-msp430.c (msp430_force_relocation_local): Modify to
+ be addition to rather than replacement of standard
+ TC_FORCE_RELOCATION_LOCAL.
+
+2017-05-15 Nick Clifton <nickc@redhat.com>
+
+ PR gas/21458
+ * config/tc-arm.c (do_adr): If the ADR involves a thumb function
+ symbol, ensure that the T bit will be set.
+ (do_adrl): Likewise.
+ (do_t_adr): Likewise.
+ * testsuite/gas/arm/pr21458.s: New test.
+ * testsuite/gas/arm/pr21458.d: New test driver.
+
+2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
+
+ * testsuite/gas/mips/mips16-pcrel-1.d: Remove `-mips3' from `as'
+ flags.
+ * testsuite/gas/mips/mips16-pcrel-pic-1.d: Likewise.
+ * testsuite/gas/mips/mips16-pcrel-n32-0.d: Likewise.
+ * testsuite/gas/mips/mips16-pcrel-n32-1.d: Likewise.
+ * testsuite/gas/mips/mips16-pcrel-n64-0.d: Likewise.
+ * testsuite/gas/mips/mips16-pcrel-n64-1.d: Likewise.
+ * testsuite/gas/mips/mips16-pcrel-n64-sym32-0.d: Likewise.
+ * testsuite/gas/mips/mips16-pcrel-n64-sym32-1.d: Likewise.
+ * testsuite/gas/mips/mips16-pcrel-reloc-4.d: Likewise.
+ * testsuite/gas/mips/mips16-pcrel-reloc-5.d: Likewise.
+ * testsuite/gas/mips/mips16-pcrel-reloc-6.d: Likewise.
+ * testsuite/gas/mips/mips16-pcrel-reloc-7.d: Likewise.
+ * testsuite/gas/mips/mips16-pcrel-addend-4.d: Likewise.
+ * testsuite/gas/mips/mips16-pcrel-addend-5.d: Likewise.
+ * testsuite/gas/mips/mips16-pcrel-addend-6.d: Likewise.
+ * testsuite/gas/mips/mips16-pcrel-addend-7.d: Likewise.
+ * testsuite/gas/mips/mips16-pcrel-addend-9.d: Likewise.
+ * testsuite/gas/mips/mips16-pcrel-addend-pic-9.d: Likewise.
+ * testsuite/gas/mips/mips16-pcrel-addend-n32-8.d: Likewise.
+ * testsuite/gas/mips/mips16-pcrel-addend-n32-9.d: Likewise.
+ * testsuite/gas/mips/mips16-pcrel-addend-n64-sym32-8.d:
+ Likewise.
+ * testsuite/gas/mips/mips16-pcrel-addend-n64-sym32-9.d:
+ Likewise.
+ * testsuite/gas/mips/mips16-pcrel-addend-n64-8.d: Likewise.
+ * testsuite/gas/mips/mips16-pcrel-addend-n64-9.d: Likewise.
+ * testsuite/gas/mips/mips16-pcrel-absolute-2.d: Likewise.
+ * testsuite/gas/mips/mips16-pcrel-absolute-3.d: Likewise.
+ * testsuite/gas/mips/mips16-pcrel-absolute-6.d: Likewise.
+ * testsuite/gas/mips/mips16-pcrel-absolute-7.d: Likewise.
+ * testsuite/gas/mips/mips16-pcrel-absolute-pic-6.d: Likewise.
+ * testsuite/gas/mips/mips16-pcrel-absolute-n32-4.d: Likewise.
+ * testsuite/gas/mips/mips16-pcrel-absolute-n32-6.d: Likewise.
+ * testsuite/gas/mips/mips16-pcrel-absolute-n64-4.d: Likewise.
+ * testsuite/gas/mips/mips16-pcrel-absolute-n64-6.d: Likewise.
+ * testsuite/gas/mips/mips16-pcrel-absolute-n64-sym32-4.d:
+ Likewise.
+ * testsuite/gas/mips/mips16-pcrel-absolute-n64-sym32-6.d:
+ Likewise.
+ * testsuite/gas/mips/mips16-pcrel-absolute-pic-n32-4.d:
+ Likewise.
+ * testsuite/gas/mips/mips16-pcrel-absolute-pic-n32-6.d:
+ Likewise.
+ * testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-4.d:
+ Likewise.
+ * testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-6.d:
+ Likewise.
+ * testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-sym32-4.d:
+ Likewise.
+ * testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-sym32-6.d:
+ Likewise.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-0.d: New test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-1.d: New test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-2.d: New test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-n32-0.d: New test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-n32-1.d: New test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-n64-sym32-0.d: New
+ test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-n64-sym32-1.d: New
+ test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-delay-0.d: New test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-delay-1.d: New test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-reloc-2.d: New test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-reloc-3.d: New test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-reloc-6.d: New test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-reloc-7.d: New test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-addend-2.d: New test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-addend-3.d: New test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-addend-6.d: New test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-addend-7.d: New test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-addend-8.d: New test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-addend-9.d: New test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-addend-n32-8.d: New
+ test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-addend-n32-9.d: New
+ test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-addend-n64-sym32-8.d:
+ New test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-addend-n64-sym32-9.d:
+ New test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute.d: New test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-1.d: New
+ test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-2.d: New
+ test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-3.d: New
+ test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-4.d: New
+ test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-5.d: New
+ test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-6.d: New
+ test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-7.d: New
+ test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-pic-4.d: New
+ test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-pic-6.d: New
+ test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-n32-4.d: New
+ test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-n32-6.d: New
+ test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-n64-sym32-4.d:
+ New test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-n64-sym32-6.d:
+ New test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-pic-n32-4.d:
+ New test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-pic-n32-6.d:
+ New test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-pic-n64-sym32-4.d:
+ New test.
+ * testsuite/gas/mips/mips16e2@mips16-pcrel-absolute-pic-n64-sym32-6.d:
+ New test.
+ * testsuite/gas/mips/mips16-pcrel-1.l: Adjust line numbers.
+ * testsuite/gas/mips/mips16-pcrel-1.s: Adjust for alignment
+ preservation between MIPS16 and MIPS16e2 code.
+ * testsuite/gas/mips/mips.exp: Run MIPS16 relaxation tests over
+ all MIPS16 architectures.
+
+2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
+
+ * testsuite/gas/mips/mips16e2.d: New test.
+ * testsuite/gas/mips/mips16e2-mt.d: New test.
+ * testsuite/gas/mips/mips16e2-sub.d: New test.
+ * testsuite/gas/mips/mips16e2@mips16e2-sub.d: New test.
+ * testsuite/gas/mips/mips16e2-mt-sub.d: New test.
+ * testsuite/gas/mips/mips16e2@mips16e2-mt-sub.d: New test.
+ * testsuite/gas/mips/mips16e2-hilo.d: New test.
+ * testsuite/gas/mips/mips16e2-hilo-n32.d: New test.
+ * testsuite/gas/mips/mips16e2-reloc-error.d: New test.
+ * testsuite/gas/mips/mips16e2-imm-error.d: New test.
+ * testsuite/gas/mips/elf_ase_mips16e2.d: New test.
+ * testsuite/gas/mips/elf_ase_mips16e2-2.d: New test.
+ * testsuite/gas/mips/elf-rel9-mips16e2.d: New test.
+ * testsuite/gas/mips/mips16e2-lui.d: New test.
+ * testsuite/gas/mips/mips16e2@mips32r2-sync.d: New test.
+ * testsuite/gas/mips/mips16e2@mips32r2-sync-1.d: New test.
+ * testsuite/gas/mips/mips16e2@lui-2.d: New test.
+ * testsuite/gas/mips/mips16e2-reloc-error.l: New stderr output.
+ * testsuite/gas/mips/mips16e2-imm-error.l: New stderr output.
+ * testsuite/gas/mips/mips16e2@lui-2.l: New stderr output.
+ * testsuite/gas/mips/mips16e2.s: New test source.
+ * testsuite/gas/mips/mips16e2-mt.s: New test source.
+ * testsuite/gas/mips/mips16e2-sub.s: New test source.
+ * testsuite/gas/mips/mips16e2-mt-sub.s: New test source.
+ * testsuite/gas/mips/mips16e2-hilo.s: New test source.
+ * testsuite/gas/mips/mips16e2-reloc-error.s: New test source.
+ * testsuite/gas/mips/mips16e2-imm-error.s: New test source.
+ * testsuite/gas/mips/elf-rel9-mips16e2.s: New test source.
+ * testsuite/gas/mips/mips16e2-lui.s: New test source.
+ * testsuite/gas/mips/mips.exp: Expand `mips32r2-sync',
+ `mips32r2-sync-1', `lui-1' and `lui-2' tests across MIPS16e2
+ architectures. Run the new tests.
+
+2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
+
+ * testsuite/gas/mips/mips.exp (run_dump_test_arch): Add
+ `mips16e2@' prefix.
+ (run_list_test_arch): Likewise.
+ (mips16e2-32, mips16e2-64): New architectures.
+ * testsuite/gas/mips/mips16e2-32@mips16-macro.d: New test.
+ * testsuite/gas/mips/mips16e2-32@mips16-macro-t.d: New test.
+ * testsuite/gas/mips/mips16e2-32@mips16-macro-e.d: New test.
+ * testsuite/gas/mips/mips16e2-32@mips16-insn-t.d: New test.
+ * testsuite/gas/mips/mips16e2-32@mips16-insn-e.d: New test.
+ * testsuite/gas/mips/mips16e2-32@mips16e-64.d: New test.
+ * testsuite/gas/mips/mips16e2-32@mips16-sub.d: New test.
+ * testsuite/gas/mips/mips16e2-32@mips16e-64-sub.d: New test.
+ * testsuite/gas/mips/mips16e2@relax-swap3.d: New test.
+ * testsuite/gas/mips/mips16-32@mips16-asmacro.d: Remove `source'
+ tag. Add `-I$srcdir/$subdir' to `as' flags.
+ * testsuite/gas/mips/mips16-64@mips16-asmacro.d: Likewise.
+ * testsuite/gas/mips/mips16e2-32@mips16-macro.l: New stderr
+ output.
+ * testsuite/gas/mips/mips16e2-32@mips16-macro-t.l: New stderr
+ output.
+ * testsuite/gas/mips/mips16e2-32@mips16-macro-e.l: New stderr
+ output.
+ * testsuite/gas/mips/mips16e2-32@mips16-insn-t.l: New stderr
+ output.
+ * testsuite/gas/mips/mips16e2-32@mips16-insn-e.l: New stderr
+ output.
+ * testsuite/gas/mips/mips16-sub.s: Add `.set nomips16e2'.
+ * testsuite/gas/mips/mips16e-sub.s: Likewise.
+ * testsuite/gas/mips/mips16e-64-sub.s: Likewise.
+ * testsuite/gas/mips/mips16-asmacro.s: Remove `.set mips32'.
+ * testsuite/gas/mips/mips16-32@mips16-asmacro.s: New test
+ source.
+ * testsuite/gas/mips/mips16-64@mips16-asmacro.s: New test
+ source.
+
+2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
+ Matthew Fortune <matthew.fortune@imgtec.com>
+ Andrew Bennett <andrew.bennett@imgtec.com>
+
+ * config/tc-mips.c (RELAX_MIPS16_ENCODE): Add `e2' flag.
+ (RELAX_MIPS16_E2): New macro.
+ (RELAX_MIPS16_PIC, RELAX_MIPS16_SYM32, RELAX_MIPS16_NOMACRO)
+ (RELAX_MIPS16_USER_SMALL, RELAX_MIPS16_USER_EXT)
+ (RELAX_MIPS16_DSLOT, RELAX_MIPS16_JAL_DSLOT)
+ (RELAX_MIPS16_EXTENDED, RELAX_MIPS16_MARK_EXTENDED)
+ (RELAX_MIPS16_CLEAR_EXTENDED, RELAX_MIPS16_ALWAYS_EXTENDED)
+ (RELAX_MIPS16_MARK_ALWAYS_EXTENDED)
+ (RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED, RELAX_MIPS16_MACRO)
+ (RELAX_MIPS16_MARK_MACRO, RELAX_MIPS16_CLEAR_MACRO): Shift bits.
+ (mips16_immed_extend): New prototype.
+ (options): Add OPTION_MIPS16E2 and OPTION_NO_MIPS16E2 enum
+ values.
+ (md_longopts): Add "mmips16e2" and "mno-mips16e2" options.
+ (mips_ases): Add "mips16e2" entry.
+ (mips_set_ase): Handle MIPS16e2 ASE.
+ (insn_insert_operand): Explicitly handle immediates with MIPS16
+ instructions that require 32-bit encoding.
+ (is_opcode_valid_16): Pass enabled ASE bitmask on to
+ `opcode_is_member'.
+ (validate_mips_insn): Explicitly handle immediates with MIPS16
+ instructions that require 32-bit encoding.
+ (operand_reg_mask) <OP_REG28>: Add handler.
+ (match_reg28_operand): New function.
+ (match_operand) <OP_REG28>: Add handler.
+ (append_insn): Pass ASE_MIPS16E2 setting to RELAX_MIPS16_ENCODE.
+ (match_mips16_insn): Handle MIPS16 instructions that require
+ 32-bit encoding and `V' and `u' operand codes.
+ (mips16_ip): Allow any characters except from `.' in opcodes.
+ (mips16_immed_extend): Handle 9-bit immediates. Do not shuffle
+ immediates whose width is not one of these listed.
+ (md_estimate_size_before_relax): Handle MIPS16e2 relaxation.
+ (mips_relax_frag): Likewise.
+ (md_convert_frag): Likewise.
+ (mips_convert_ase_flags): Handle MIPS16e2 ASE.
+
+ * doc/as.texinfo (Target MIPS options): Add `-mmips16e2' and
+ `-mno-mips16e2' options.
+ (-mmips16e2, -mno-mips16e2): New options.
+ * doc/c-mips.texi (MIPS Options): Add `-mmips16e2' and
+ `-mno-mips16e2' options.
+ (MIPS ASE Instruction Generation Overrides): Add `.set mips16e2'
+ and `.set nomips16e2'.
+
+2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
+
+ * config/tc-mips.c (match_int_operand): Call
+ `match_out_of_range' before returning failure for 0x8000-0xffff
+ values conditionally allowed.
+
+2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
+
+ * config/tc-mips.c (match_int_operand): Call
+ `match_not_constant' before returning failure for a non-constant
+ 16-bit immediate conditionally allowed.
+
+2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
+
+ * config/tc-mips.c (match_const_int): Call `match_out_of_range'
+ rather than `match_not_constant' for unrelocated operands
+ retrieved as an `O_big' expression.
+ (match_int_operand): Call `match_out_of_range' for relocatable
+ operands retrieved as an `O_big' expression.
+ (match_mips16_insn): Call `match_out_of_range' for relaxable
+ operands retrieved as an `O_big' expression.
+ * testsuite/gas/mips/addiu-error.d: New test.
+ * testsuite/gas/mips/mips16@addiu-error.d: New test.
+ * testsuite/gas/mips/micromips@addiu-error.d: New test.
+ * testsuite/gas/mips/break-error.d: New test.
+ * testsuite/gas/mips/lui-1.l: Adjust error message.
+ * testsuite/gas/mips/addiu-error.l: New stderr output.
+ * testsuite/gas/mips/mips16@addiu-error.l: New stderr output.
+ * testsuite/gas/mips/micromips@addiu-error.l: New stderr output.
+ * testsuite/gas/mips/break-error.l: New stderr output.
+ * testsuite/gas/mips/addiu-error.s: New test source.
+ * testsuite/gas/mips/break-error.s: New test source.
+ * testsuite/gas/mips/mips.exp: Run the new tests.
+
+2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
+
+ * config/tc-mips.c (match_mips16_insn): Remove the explicit
+ OT_INTEGER check before the `match_expression' call.
+ * testsuite/gas/mips/mips16-insn-e.l: Adjust messages.
+ * testsuite/gas/mips/mips16-32@mips16-insn-e.l: Likewise.
+ * testsuite/gas/mips/mips16-64@mips16-insn-e.l: Likewise.
+ * testsuite/gas/mips/mips16e-32@mips16-insn-e.l: Likewise.
+ * testsuite/gas/mips/mips16-reg-error.d: New test.
+ * testsuite/gas/mips/mips16-reg-error.l: New stderr output.
+ * testsuite/gas/mips/mips16-reg-error.s: New test source.
+ * testsuite/gas/mips/mips.exp: Run the new test.
+
+2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
+
+ * config/tc-mips.c (match_mips16_insn): Call
+ `match_not_constant' for a disallowed relocation operation.
+ * testsuite/gas/mips/mips16-reloc-error.d: New test.
+ * testsuite/gas/mips/mips16-reloc-error.l: New stderr output.
+ * testsuite/gas/mips/mips16-reloc-error.s: New test source.
+ * testsuite/gas/mips/mips.exp: Run the new test.
+
+2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
+
+ * testsuite/gas/mips/lui-1.d: New test.
+ * testsuite/gas/mips/lui-2.d: New test.
+ * gas/testsuite/gas/mips/mips.exp: Fold corresponding list tests
+ into the new tests.
+
2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (match_const_int): Update description.
projects / thirdparty / binutils-gdb.git / blobdiff