+2020-06-30 H.J. Lu <hongjiu.lu@intel.com>
+
+ * NEWS: Mention x86 NaCl target support removal.
+ * config/tc-i386.c: Remove x86 NaCl target support.
+ * config/tc-i386.h: Likewise.
+ * configure.tgt: Likewise.
+ * testsuite/gas/i386/i386.exp: Likewise.
+ * testsuite/gas/i386/iamcu-1.d: Likewise.
+ * testsuite/gas/i386/iamcu-2.d: Likewise.
+ * testsuite/gas/i386/iamcu-3.d: Likewise.
+ * testsuite/gas/i386/iamcu-4.d: Likewise.
+ * testsuite/gas/i386/iamcu-5.d: Likewise.
+ * testsuite/gas/i386/k1om.d: Likewise.
+ * testsuite/gas/i386/l1om.d: Likewise.
+
+2020-06-30 Nelson Chu <nelson.chu@sifive.com>
+
+ * config/tc-riscv.c (riscv_csr_class_check): Removed. Move the
+ checking into riscv_csr_address.
+ (riscv_csr_version_check): Likewise.
+ (riscv_csr_address): New function. Return the suitable CSR address
+ after checking the ISA dependency and versions. Issue warnings if
+ we find any conflict and -mcsr-check is set. CSR_CLASS_F and
+ CSR_CLASS_DEBUG are unprivileged CSR for now, so don't check the
+ priv spec versions for them.
+ (reg_csr_lookup_internal): Call riscv_csr_address to find the
+ suitable CSR address.
+ * testsuite/gas/riscv/priv-reg-fail-fext.d: Remove -mpriv-spec=1.11.
+ * testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-fext.l: We don't care the
+ priv spec warnings here. These warnings are added by accident.
+ Remove them and only focus on the ISA dependency warnings.
+ * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Updated since
+ dscratch0 and dscratch1 are regarded as the unprivileged CSR rather
+ than the privileged ones.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
+ * testsuite/gas/riscv/priv-reg.s: Likewise. Add missing debug CSR.
+ * testsuite/gas/riscv/priv-reg-version-1p9.d: Likewise.
+ * testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise.
+ * testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise.
+ * testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise.
+ * testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
+ * testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
+
+2020-06-29 H.J. Lu <hongjiu.lu@intel.com>
+
+ * tc-i386.c (build_vex_prefix): Support VEX base opcode length > 1.
+ (md_assemble): Don't process ImmExt without operands.
+
+2020-06-29 Hans-Peter Nilsson <hp@bitrange.com>
+
+ PR gas/25331
+ * config/tc-mmix.c (md_assemble) <fixup for
+ BFD_RELOC_MMIX_BASE_PLUS_OFFSET>: This fixup affects 1 byte, not 8.
+ Also, set its fx_no_overflow.
+ (md_convert_frag) <case ENCODE_RELAX (STATE_PUSHJSTUB, STATE_ZERO)>:
+ Similarly this fixup affects 4 bytes, not 8 and needs its
+ fx_no_overflow set.
+ * config/tc-mmix.h (TC_FX_SIZE_SLACK): Don't define.
+ * testsuite/gas/mmix/pr25331.d, testsuite/gas/mmix/pr25331.s: New test.
+
+2020-06-29 Alan Modra <amodra@gmail.com>
+
+ * config/tc-s12z.c: Use C style comments.
+ * config/tc-z80.c: Likewise.
+ * config/tc-xtensa.c (emit_ld_r_n): Remove commented out code.
+
+2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (md_assemble): Process ImmExt without
+ operands.
+
+2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (check_VecOperands): Replace vecsib with sib.
+ Replace VecSIB128, VecSIB256 and VecSIB512 with VECSIB128,
+ VECSIB256 and VECSIB512, respectively.
+ (build_modrm_byte): Replace vecsib with sib.
+
+2020-06-26 Jan Beulich <jbeulich@suse.com>
+
+ * testsuite/gas/i386/nop-1-suffix.d: New.
+ * testsuite/gas/i386/i386.exp: Run new test.
+
+2020-06-26 Pat Bernardi <bernardi@adacore.com>
+
+ * config/tc-m68k.c (m68k_elf_gnu_attribute): New function.
+ (md_pseudo_table): Handle "gnu_attribute".
+ * doc/as.texi: Document GNU attribute for M68K.
+
+2020-06-25 Nick Clifton <nickc@redhat.com>
+
+ PR 26141
+ * config/tc-arm.c (arm_force_relocation): Force resolution of
+ BFD_RELOC_THUMB_PCREL_BRANCH12 relocations.
+ * testsuite/gas/arm/plt-1.d: Adjust expected disassembly.
+
+2020-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (md_assemble): Move call to process_immext()
+ ...
+ (process_operands): ... here.
+
+2020-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (process_suffix): Skip ambiguous operand size
+ diagnostic when there is a sizing prefix. Switch to word/dword/
+ qword encoding when there is a sizing prefix and no (explicit or
+ derived) suffix.
+ (update_imm): Handle presence of a sizing prefix.
+ * testsuite/gas/i386/noreg16-data32.d,
+ testsuite/gas/i386/noreg32-data16.d,
+ testsuite/gas/i386/noreg32-data16.e,
+ testsuite/gas/i386/noreg64-data16.d,
+ testsuite/gas/i386/noreg64-data16.e,
+ testsuite/gas/i386/noreg64-rex64.d: New.
+ * testsuite/gas/i386/i386.exp: Run new tests.
+ * testsuite/gas/i386/noreg32.s, testsuite/gas/i386/noreg64.s:
+ Introduce and use pfx* macros.
+ * testsuite/gas/i386/noreg16.s: Likewise. Replace 32-bit
+ addressing.
+ * testsuite/gas/i386/noreg16.d: Adjust expectations.
+
+2020-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * testsuite/gas/i386/avx-16bit.d,
+ testsuite/gas/i386/avx-scalar.d, testsuite/gas/i386/avx.d,
+ testsuite/gas/i386/avx512f-16bit.d,
+ testsuite/gas/i386/avx512f.d,
+ testsuite/gas/i386/evex-lig256.d,
+ testsuite/gas/i386/evex-lig512.d
+ testsuite/gas/i386/evex-wig1.d, testsuite/gas/i386/katmai.d,
+ testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg32.d,
+ testsuite/gas/i386/ptwrite.d, testsuite/gas/i386/simd.d,
+ testsuite/gas/i386/sse2-16bit.d,
+ testsuite/gas/i386/sse2.d, testsuite/gas/i386/sse2avx.d: Adjust
+ expectations.
+
+2020-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (md_assemble): Also reject explicit REX
+ prefixes with VEX and alike encoded insns. Zap consumed bits
+ from i.rex.
+ (output_insn): Don't ignore REX prefix for VEX and alike
+ encodings; abort() instead if encountered.
+ * testsuite/gas/i386/x86-64-pseudos.s: Move REX-with-VEX cases
+ ...
+ * testsuite/gas/i386/x86-64-pseudos-bad.s: ... here.
+ * testsuite/gas/i386/x86-64-pseudos.d,
+ testsuite/gas/i386/x86-64-pseudos-bad.l: Adjust expectations.
+
+2020-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (process_operands): Translate explicit REX
+ prefix into i.rex for SSE2AVX templates.
+ (set_rex_vrex): New helper.
+ (build_modrm_byte): Use it.
+ * testsuite/gas/i386/x86-64-sse2avx.s: Add cases with explict
+ REX prefixes.
+ * testsuite/gas/i386/x86-64-sse2avx.d: Adjust expectations.
+
+2020-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (cpu_flags_match): Only match SSE2AVX
+ templates when there's no data size prefix.
+ (md_assemble): Reject data size prefix also for legacy encoded
+ SIMD templates.
+ * testsuite/gas/i386/prefix32.s, testsuite/gas/i386/prefix64.s:
+ Uncomment previously not working line.
+ * testsuite/gas/i386/sse2avx.s: Add ldmxcsr/stmxcsr cases with
+ data16 prefix.
+ * testsuite/gas/i386/prefix32.l, testsuite/gas/i386/prefix64.l,
+ testsuite/gas/i386/sse2avx.d: Adjust expectations.
+
+2020-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (build_evex_prefix): Drop early setting of
+ vec_length.
+
+2020-06-23 Nelson Chu <nelson.chu@sifive.com>
+
+ * config/tc-riscv.c (explicit_priv_attr): Rename explicit_csr to
+ explicit_priv_attr. It used to indicate CSR or priv instructions are
+ explictly used.
+ (riscv_is_priv_insn): Return True if it is a privileged instruction.
+ (riscv_ip): Call riscv_is_priv_insn to check whether the instruction
+ is privileged or not. If it is, then set explicit_priv_attr to TRUE.
+ (riscv_write_out_attrs): Clarification of when to generate the elf
+ priv spec attributes.
+ * testsuite/gas/riscv/attribute-11.s: Add comments.
+ * testsuite/gas/riscv/attribute-14.s: New testcase. Use symbol
+ `priv_insn_<n>` to decide which priv instruction is expected to used.
+ (<n> is a to e.)
+ * testsuite/gas/riscv/attribute-14a.d: Likewise.
+ * testsuite/gas/riscv/attribute-14b.d: Likewise.
+ * testsuite/gas/riscv/attribute-14c.d: Likewise.
+ * testsuite/gas/riscv/attribute-14d.d: Likewise.
+ * testsuite/gas/riscv/attribute-14e.d: Likewise.
+
+2020-06-22 Nelson Chu <nelson.chu@sifive.com>
+
+ * config/tc-riscv.c (buf_size, buf): Remove the unused variables.
+ (riscv_set_default_priv_spec): Get the priv spec version from the
+ priv spec attributes by riscv_get_priv_spec_class_from_numbers.
+
+2020-06-20 Alan Modra <amodra@gmail.com>
+
+ * configure.tgt: Set bfd_gas for all SH targets.
+
+2020-06-18 Jan Beulich <jbeulich@suse.com>
+
+ * testsuite/gas/i386/arch-13.s: Add alternative VMGEXIT case.
+ * testsuite/gas/i386/arch-13.d: Extend -march=. Adjust
+ expectations.
+
+2020-06-16 Lili Cui <lili.cui@intel.com>
+
+ * config/tc-i386.c (cpu_arch): Correct noavx512_vp2intersect
+ cpu_arch to CPU_ANY_VP2INTERSECT_FLAGS.
+ * doc/c-i386.texi: Add avx512_vp2intersect.
+
+2020-06-16 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (md_assemble): Drop SSE4a from SSE check
+ conditional.
+ * testsuite/gas/i386/sse-check.s: Adjust comment.
+ * testsuite/gas/i386/sse-check-error.l,
+ testsuite/gas/i386/sse-check-warn.e,
+ testsuite/gas/i386/x86-64-sse-check-error.l: Adjust
+ expectations.
+
+2020-06-16 Alan Modra <amodra@gmail.com>
+
+ * config/tc-tic30.h: Remove OBJ_AOUT support.
+ * configure.tgt: Delete tic30-*-*aout* entry.
+
+2020-06-15 Max Filippov <jcmvbkbc@gmail.com>
+
+ * config/tc-xtensa.c (XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New
+ macros.
+ (elf32xtensa_abi): New declaration.
+ (option_abi_windowed, option_abi_call0): New enum constants.
+ (md_longopts): Add entries for --abi-windowed and --abi-call0.
+ (md_parse_option): Add handlers for --abi-windowed and
+ --abi-call0.
+ (xtensa_add_config_info): Use xtensa_abi_choice instead of
+ XSHAL_ABI to format ABI tag.
+ * doc/as.texi (Target Xtensa options): Add --abi-windowed and
+ --abi-call0 to the list of options.
+ * doc/c-xtensa.texi: Add description for options --abi-windowed
+ and --abi-call0.
+ * testsuite/gas/xtensa/abi-call0.d: New test definition.
+ * testsuite/gas/xtensa/abi-windowed.d: New test definition.
+ * testsuite/gas/xtensa/abi.s: New test source.
+
+2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/26115
+ * testsuite/gas/i386/tsxldtrk.d: Replace xsuspldtrk with
+ xsusldtrk.
+ * testsuite/gas/i386/tsxldtrk.s: Likewise.
+ * testsuite/gas/i386/x86-64-tsxldtrk.d: Likewise.
+ * testsuite/gas/i386/x86-64-tsxldtrk.s: Likewise.
+
+2020-06-12 Nelson Chu <nelson.chu@sifive.com>
+
+ * testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Removed.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
+ * testsuite/gas/riscv/priv-reg-version-1p9.d: Likewise.
+
+2020-06-09 Seth Girvan <snth@snthhacks.com>
+
+ * doc/c-avr.texi: Improve wording.
+
+2020-06-09 Jan Beulich <jbeulich@suse.com>
+
+ * testsuite/gas/i386/x86-64-pseudos-bad.s,
+ testsuite/gas/i386/x86-64-pseudos-bad.l: New.
+
+2020-06-09 Jan Beulich <jbeulich@suse.com>
+
+ * testsuite/gas/i386/prefix.s: Add bogus prefix-with-VEX/EVEX
+ encoding tests.
+ * testsuite/gas/i386/prefix.d: Adjust expectations.
+
+2020-06-09 Jan Beulich <jbeulich@suse.com>
+
+ * testsuite/gas/i386/prefix.s: Add bogus REP / EVEX.W prefix
+ with VEX/EVEX encoding tests.
+ * testsuite/gas/i386/prefix.d: Adjust expectations.
+
+2020-06-09 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (process_suffix): Restrict defaulting to 'q'
+ suffix.
+ * testsuite/gas/i386/noreg64.s: Add lcall/ljmp cases.
+ * testsuite/gas/i386/noreg64.d: Adjust expectations.
+ * testsuite/gas/i386/noreg-intel64.d,
+ testsuite/gas/i386/noreg-intel64.l,
+ testsuite/gas/i386/noreg-intel64.s: New.
+ * testsuite/gas/i386/i386.exp: Run new tests.
+
+2020-06-09 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (vex_encoding_error): New enumerator.
+ (VEX_check_operands): Rename to VEX_check_encoding. Check
+ for vex_encoding_error. Move Imm4 handling ...
+ (check_VecOperands): ... here.
+ (match_template): Call VEX_check_encoding when there are no
+ operands. Split construct calling check_VecOperands and
+ VEX_check_encoding (when there are operands).
+ (check_register): Don't blindly set vex_encoding_evex.
+ * testsuite/gas/i386/pseudos-bad.s,
+ testsuite/gas/i386/pseudos-bad.l: New.
+ * testsuite/gas/i386/i386.exp: Run new test.
+ * testsuite/gas/i386/xmmhi64.s: Drop {vex2}.
+
+2020-06-08 Alex Coplan <alex.coplan@arm.com>
+
+ * config/tc-arm.c (insns): Add dfb.
+ * testsuite/gas/arm/dfb.d: New test.
+ * testsuite/gas/arm/dfb.s: Input for test.
+
+2020-06-08 Nick Clifton <nickc@redhat.com>
+
+ * testsuite/gas/cfi/cfi-i386-2.d: Skip for PE based targets.
+
+2020-06-08 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (pi): Add checks for RegMask and RegBND.
+
+2020-06-08 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (check_byte_reg): Drop dead conditional
+ around as_bad().
+
+2020-06-08 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (check_register): Split RegTR handling, to
+ fail recognition also in 64-bit mode as well as with i586 or
+ i686 explicitly enabled.
+ * testsuite/gas/i386/x86_64.s: Add insns referencing tr<N>.
+ * testsuite/gas/i386/x86_64-intel.d,
+ testsuite/gas/i386/x86_64.d: Adjust expectations.
+
+2020-06-08 Jan Beulich <jbeulich@suse.com>
+
+ * testsuite/gas/cfi/cfi-i386-2.d: Adjust expectations.
+ * testsuite/gas/cfi/cfi.exp: Run this test.
+
+2020-06-08 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (parse_real_register): Add allow_pseudo_reg
+ check to %st(N) parsing logic.
+ * testsuite/gas/cfi/cfi-i386.s: Set "generic32" arch.
+
+2020-06-08 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (bad_reg): New.
+ (check_VecOperations, i386_att_operand, i386_parse_name): Check
+ for it.
+ (check_register): New, broken out from ...
+ (parse_real_register): ... here. Call it.
+ (parse_register): Call it, and error upon failure.
+ * testsuite/gas/i386/equ-bad.s, testsuite/gas/i386/equ-bad.l,
+ testsuite/gas/i386/x86-64-equ-bad.s,
+ testsuite/gas/i386/x86-64-equ-bad.l: New.
+ * testsuite/gas/i386/i386.exp: Run new tests.
+
+2020-06-06 Alan Modra <amodra@gmail.com>
+
+ * config/tc-ppc.c (md_show_usage): Mention -mpower10 and -mpwr10.
+ * doc/c-ppc.texi: Likewise.
+
+2020-06-06 Alan Modra <amodra@gmail.com>
+
+ * config/tc-ppc.c: Update throughout for reloc renaming.
+
+2020-06-05 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * config/tc-bpf.c (md_apply_fix): Avoid GCC 10 warning
+ stringop-overflow.
+
+2020-06-05 Nelson Chu <nelson.chu@sifive.com>
+
+ * config/tc-riscv.c (explicit_csr): New static boolean.
+ Used to indicate CSR are explictly used.
+ (riscv_ip): Set explicit_csr to TRUE if any CSR is used.
+ (riscv_write_out_attrs): If we already have set elf priv
+ attributes, then generate them. Otherwise, don't generate
+ them when no CSR are used.
+ * testsuite/gas/riscv/attribute-01.d: Remove the priv attributes.
+ * testsuite/gas/riscv/attribute-02.d: Likewise.
+ * testsuite/gas/riscv/attribute-03.d: Likewise.
+ * testsuite/gas/riscv/attribute-04.d: Likewise.
+ * testsuite/gas/riscv/attribute-05.d: Likewise.
+ * testsuite/gas/riscv/attribute-06.d: Likewise.
+ * testsuite/gas/riscv/attribute-07.d: Likewise.
+ * testsuite/gas/riscv/attribute-08.d: Likewise.
+ * testsuite/gas/riscv/attribute-09.d: Likewise.
+ * testsuite/gas/riscv/attribute-10.d: Likewise.
+ * testsuite/gas/riscv/attribute-unknown.d: Likewise.
+ * testsuite/gas/riscv/attribute-11.s: New testcase.
+ * testsuite/gas/riscv/attribute-11.d: New testcase. The CSR is
+ used, so we should output the ELF priv attributes.
+ * testsuite/gas/riscv/attribute-12.d: New testcase. The CSR is
+ used, so output the priv attributes according to the -mpriv-spec.
+ * testsuite/gas/riscv/attribute-13.d: New testcase. The CSR isn't
+ used, so ignore the -mpriv-spec setting.
+
+2020-06-04 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-ip2k. (ip2k_apply_fix): Pass endianness to
+ cgen_get_insn_value.
+ * config/tc-xstormy16.c (xstormy16_md_apply_fix): Pass
+ endianness to cgen_get_insn_value and cgen_put_insn_value.
+
+2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * config/tc-bpf.c (md_apply_fix): Simplify and avoid using
+ cgen_put_insn_value.
+
+2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * config/tc-bpf.c (md_begin): Pass CGEN_CPU_OPEN_INSN_ENDIAN to
+ bpf_cgen_cpu_open.
+ (md_assemble): Remove no longer needed hack.
+
+2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * cgen.c (gas_cgen_finish_insn): Pass the endianness to
+ cgen_put_insn_value.
+ (gas_cgen_md_apply_fix): Likewise.
+ (gas_cgen_md_apply_fix): Likewise.
+ * config/tc-bpf.c (md_apply_fix): Pass data endianness to
+ cgen_put_insn_value.
+ * config/tc-mep.c (mep_check_ivc2_scheduling): Pass endianness to
+ cgen_put_insn_value.
+
+2020-06-04 Alan Modra <amodra@gmail.com>
+
+ * testsuite/config/default.exp: Remove global directive outside
+ proc body.
+ * testsuite/gas/mep/complex-relocs.exp: Likewise.
+ * testsuite/gas/microblaze/relax_size.exp: Likewise.
+ * testsuite/gas/microblaze/reloc_sym.exp: Likewise.
+ * testsuite/gas/mt/relocs.exp: Likewise.
+ * testsuite/gas/rx/rx.exp: Likewise.
+
+2020-06-03 Stephen Casner <casner@acm.org>
+
+ * doc/c-riscv.texi (RISC-V-Options): Fix non-ASCII apostrophe.
+
+2020-06-02 Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
+ Jim Wilson <jimw@sifive.com>
+
+ PR 26051
+ * doc/c-riscv.texi (RISC-V-Formats): Add missing I format using
+ simm12(rs1). Correct S format to use simm12(rs1). Drop SB and B
+ formats using simm12(rs1). Correct SB and B to use rs1 and rs2.
+ Move B before SB. Move J before UJ.
+
+2020-06-01 Alex Coplan <alex.coplan@arm.com>
+
+ * write.c (relax_segment): Fix handling of negative offset when
+ relaxing an rs_org frag.
+ * testsuite/gas/aarch64/org-neg.d: New test.
+ * testsuite/gas/aarch64/org-neg.l: Error output for test.
+ * testsuite/gas/aarch64/org-neg.s: Input for test.
+ * testsuite/gas/arm/org-neg.d: New test.
+ * testsuite/gas/arm/org-neg.l: Error output for test.
+ * testsuite/gas/arm/org-neg.s: Input for test.
+
+2020-05-28 Stephen Casner <casner@acm.org>
+
+ Fix unexpected failures in gas testsuite for pdp11-aout target.
+ These are caused by the PDP11's mix of little-endian octets in
+ shorts but shorts in big endian order for long or quad.
+
+ * config/tc-pdp11.c (md_number_to_chars): Implement .quad
+ * testsuite/gas/all/gas.exp: Select alternate test scripts for
+ pdp11, skip octa test completely.
+ * testsuite/gas/all/eqv-dot-pdp11.s: Identical to eqv-dot.s
+ * testsuite/gas/all/eqv-dot-pdp11.d: Match different octet order.
+ * testsuite/gas/all/cond-pdp11.l: Match different octet order.
+
+2020-05-28 Alex Coplan <alex.coplan@arm.com>
+
+ * frags.c (frag_grow): Fix comment.
+
+2020-05-27 Stephen Casner <casner@acm.org>
+
+ PR gas/26001
+ * config/tc-pdp11.c (parse_reg): Distinguish register names from
+ symbols that begin with a register name.
+ * testsuite/gas/pdp11/pdp11.exp: Add test of such symbols.
+ * testsuite/gas/pdp11/pr26001.s: Likewise.
+ * testsuite/gas/pdp11/pr26001.d: Likewise.
+
+2020-05-27 Simon Cook <simon.cook@embecosm.com>
+
+ * config/tc-riscv.c (riscv_init_csr_hash): NULL initilize next
+ pointer when creating struct riscv_csr_extra.
+
+2020-05-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ * testsuite/gas/i386/align-branch-9.d: Updated for PECOFF.
+ * testsuite/gas/i386/inval-avx512f.s: Add .p2align for PECOFF.
+ * testsuite/gas/i386/inval-avx512f.l: Updated.
+
+2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
+
+ * testsuite/gas/s390/zarch-z13.d: Add regexp checks for vector
+ load/store instruction variants with alignment hints.
+ * testsuite/gas/s390/zarch-z13.s: Emit new vector load/store
+ instruction variants with alignment hints.
+
+2020-05-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/26044
+ * config/tc-xgate.c (md_apply_fix): Check BFD_RELOC_XGATE_PCREL_X
+ instead of R_XGATE_PCREL_X.
+ (xgate_parse_operand): Replace R_XGATE_PCREL_X with
+ BFD_RELOC_XGATE_PCREL_X.
+
+2020-05-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/26044
+ * config/tc-visium.c (md_convert_frag): Replace fragP->fr_literal
+ with &fragP->fr_literal[0].
+
+2020-05-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/26044
+ * config/tc-vax.c (md_estimate_size_before_relax): Replace
+ fragP->fr_literal with &fragP->fr_literal[0].
+ (md_convert_frag): Likewise.
+
+2020-05-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/26044
+ * config/tc-v850.c (md_convert_frag): Replace fragP->fr_literal
+ with &fragP->fr_literal[0].
+
+2020-05-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/26044
+ * config/tc-crx.c (getreg_image): Change argument type to int.
+ (md_convert_frag): Replace fragP->fr_literal with
+ &fragP->fr_literal[0].
+
+2020-05-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/26044
+ * onfig/tc-score.c (s3_do_macro_bcmp): Replace overlapping
+ sprintf with memmove.
+
+2020-05-25 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-mcore.c (md_convert_frag): Replace fragP->fr_literal
+ with &fragP->fr_literal[0].
+
+2020-05-25 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/26041
+ * config/tc-cr16.c (md_assemble): Use memmove to concatenate
+ 2 overlapping strings.
+
+2020-05-25 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-cr16.c (md_convert_frag): Replace fragP->fr_literal
+ with &fragP->fr_literal[0].
+
+2020-05-25 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-csky.c (md_convert_frag): Replace fragp->fr_literal
+ with &fragp->fr_literal[0].
+ * config/tc-microblaze.c (md_apply_fix): Likewise.
+ * config/tc-sh.c (md_convert_frag): Likewise.
+
+2020-05-24 Jim Wilson <jimw@sifive.com>
+
+ PR 26025
+ * config/tc-riscv.c (riscv_pre_output_hook): Change s type from const
+ asection to segT. New locals seg and subseg. Call subseg_set before
+ fix_new_exp. Call subseg_set after loop to restore original values.
+
+2020-05-21 Alan Modra <amodra@gmail.com>
+
+ * atof-generic.c: Replace "if (x) free (x)" with "free (x)"
+ throughout.
+ * config/obj-elf.c: Likewise.
+ * config/tc-aarch64.c: Likewise.
+ * config/tc-arm.c: Likewise.
+ * config/tc-m68k.c: Likewise.
+ * config/tc-nios2.c: Likewise.
+ * config/tc-tic30.c: Likewise.
+ * ecoff.c: Likewise.
+ * read.c: Likewise.
+ * stabs.c: Likewise.
+ * symbols.c: Likewise.
+ * testsuite/gas/all/test-gen.c: Likewise.
+
+2020-05-20 Nelson Chu <nelson.chu@sifive.com>
+
+ * testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Updated.
+ * config/tc-riscv.c (default_arch_with_ext, default_isa_spec):
+ Static variables which are used to set the ISA extensions. You can
+ use -march (or ELF build attributes) and -misa-spec to set them,
+ respectively.
+ (ext_version_hash): The hash table used to handle the extensions
+ with versions.
+ (init_ext_version_hash): Initialize the ext_version_hash according
+ to riscv_ext_version_table.
+ (riscv_get_default_ext_version): The callback function of
+ riscv_parse_subset_t. According to the choosed ISA spec,
+ get the default version for the specific extension.
+ (riscv_set_arch): Set the callback function.
+ (enum options, struct option md_longopts): Add new option -misa-spec.
+ (md_parse_option): Do not call riscv_set_arch for -march. We will
+ call it later in riscv_after_parse_args. Call riscv_get_isa_spec_class
+ to set default_isa_spec class.
+ (riscv_after_parse_args): Call init_ext_version_hash to initialize the
+ ext_version_hash, and then call riscv_set_arch to set the architecture
+ with versions according to default_arch_with_ext.
+ * testsuite/gas/riscv/attribute-02.d: Set 0p0 as default version for
+ x extensions.
+ * testsuite/gas/riscv/attribute-03.d: Likewise.
+ * testsuite/gas/riscv/attribute-09.d: New testcase. For i-ext, we
+ already set it's version to 2p1 by march, so no need to use the default
+ 2p2 version. For m-ext, we do not set the version by -march and ELF arch
+ attribute, so set the default 2p0 to it. For zicsr, it is not defined in
+ ISA spec 2p2, so set 0p0 to it.
+ * testsuite/gas/riscv/attribute-10.d: New testcase. The version of
+ zicsr is 2p0 according to ISA spec 20191213.
+ * config/tc-riscv.c (DEFAULT_RISCV_ARCH_WITH_EXT)
+ (DEFAULT_RISCV_ISA_SPEC): Default configure option settings.
+ You can set them by configure options --with-arch and
+ --with-isa-spec, respectively.
+ (riscv_set_default_isa_spec): New function used to set the
+ default ISA spec.
+ (md_parse_option): Call riscv_set_default_isa_spec rather than
+ call riscv_get_isa_spec_class directly.
+ (riscv_after_parse_args): If the -isa-spec is not set, then we
+ set the default ISA spec according to DEFAULT_RISCV_ISA_SPEC by
+ calling riscv_set_default_isa_spec.
+ * testsuite/gas/riscv/attribute-01.d: Add -misa-spec=2.2, since
+ the --with-isa-spec may be set to different ISA spec.
+ * testsuite/gas/riscv/attribute-02.d: Likewise.
+ * testsuite/gas/riscv/attribute-03.d: Likewise.
+ * testsuite/gas/riscv/attribute-04.d: Likewise.
+ * testsuite/gas/riscv/attribute-05.d: Likewise.
+ * testsuite/gas/riscv/attribute-06.d: Likewise.
+ * testsuite/gas/riscv/attribute-07.d: Likewise.
+ * configure.ac: Add configure options, --with-arch and
+ --with-isa-spec.
+ * configure: Regenerated.
+ * config.in: Regenerated.
+ * config/tc-riscv.c (default_priv_spec): Static variable which is
+ used to check if the CSR is valid for the chosen privilege spec. You
+ can use -mpriv-spec to set it.
+ (enum reg_class): We now get the CSR address from csr_extra_hash rather
+ than reg_names_hash. Therefore, move RCLASS_CSR behind RCLASS_MAX.
+ (riscv_init_csr_hashes): Only need to initialize one hash table
+ csr_extra_hash.
+ (riscv_csr_class_check): Change the return type to void. Don't check
+ the ISA dependency if -mcsr-check isn't set.
+ (riscv_csr_version_check): New function. Check and find the CSR address
+ from csr_extra_hash, according to default_priv_spec. Report warning
+ for the invalid CSR if -mcsr-check is set.
+ (reg_csr_lookup_internal): Updated.
+ (reg_lookup_internal): Likewise.
+ (md_begin): Updated since DECLARE_CSR and DECLARE_CSR_ALIAS are changed.
+ (enum options, struct option md_longopts): Add new GAS option -mpriv-spec.
+ (md_parse_option): Call riscv_set_default_priv_version to set
+ default_priv_spec.
+ (riscv_after_parse_args): If -mpriv-spec isn't set, then set the default
+ privilege spec to the newest one.
+ (enum riscv_csr_class, struct riscv_csr_extra): Move them to
+ include/opcode/riscv.h.
+ * testsuite/gas/riscv/priv-reg-fail-fext.d: This test case just want
+ to check the ISA dependency for CSR, so fix the spec version by adding
+ -mpriv-spec=1.11.
+ * testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. There are some
+ version warnings for the test case.
+ * gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
+ * gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
+ * gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
+ * gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
+ * gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
+ * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case.
+ Check whether the CSR is valid when privilege version 1.9 is choosed.
+ * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
+ * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case.
+ Check whether the CSR is valid when privilege version 1.9.1 is choosed.
+ * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
+ * gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case.
+ Check whether the CSR is valid when privilege version 1.10 is choosed.
+ * gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
+ * gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case.
+ Check whether the CSR is valid when privilege version 1.11 is choosed.
+ * gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
+ * config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Default configure option
+ setting. You can set it by configure option --with-priv-spec.
+ (riscv_set_default_priv_spec): New function used to set the default
+ privilege spec.
+ (md_parse_option): Call riscv_set_default_priv_spec rather than
+ call riscv_get_priv_spec_class directly.
+ (riscv_after_parse_args): If -mpriv-spec isn't set, then we set the
+ default privilege spec according to DEFAULT_RISCV_PRIV_SPEC by
+ calling riscv_set_default_priv_spec.
+ * testsuite/gas/riscv/csr-dw-regnums.d: Add -mpriv-spec=1.11, since
+ the --with-priv-spec may be set to different privilege spec.
+ * testsuite/gas/riscv/priv-reg.d: Likewise.
+ * configure.ac: Add configure option --with-priv-spec.
+ * configure: Regenerated.
+ * config.in: Regenerated.
+ * config/tc-riscv.c (explicit_attr): Rename explicit_arch_attr to
+ explicit_attr. Set it to TRUE if any ELF attribute is found.
+ (riscv_set_default_priv_spec): Try to set the default_priv_spec if
+ the priv attributes are set.
+ (md_assemble): Set the default_priv_spec according to the priv
+ attributes when we start to assemble instruction.
+ (riscv_write_out_attrs): Rename riscv_write_out_arch_attr to
+ riscv_write_out_attrs. Update the arch and priv attributes. If we
+ don't set the corresponding ELF attributes, then try to output the
+ default ones.
+ (riscv_set_public_attributes): If any ELF attribute or -march-attr
+ options is set (explicit_attr is TRUE), then call riscv_write_out_attrs
+ to update the arch and priv attributes.
+ (s_riscv_attribute): Make sure all arch and priv attributes are set
+ before any instruction.
+ * testsuite/gas/riscv/attribute-01.d: Update the priv attributes if any
+ ELF attribute or -march-attr is set. If the priv attributes are not
+ set, then try to update them by the default setting (-mpriv-spec or
+ --with-priv-spec).
+ * testsuite/gas/riscv/attribute-02.d: Likewise.
+ * testsuite/gas/riscv/attribute-03.d: Likewise.
+ * testsuite/gas/riscv/attribute-04.d: Likewise.
+ * testsuite/gas/riscv/attribute-06.d: Likewise.
+ * testsuite/gas/riscv/attribute-07.d: Likewise.
+ * testsuite/gas/riscv/attribute-08.d: Likewise.
+ * testsuite/gas/riscv/attribute-09.d: Likewise.
+ * testsuite/gas/riscv/attribute-10.d: Likewise.
+ * testsuite/gas/riscv/attribute-unknown.d: Likewise.
+ * testsuite/gas/riscv/attribute-05.d: Likewise. Also, the priv spec
+ set by priv attributes must be supported.
+ * testsuite/gas/riscv/attribute-05.s: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Likewise. Updated
+ priv attributes according to the -mpriv-spec option.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise.
+ * testsuite/gas/riscv/priv-reg.d: Removed.
+ * testsuite/gas/riscv/priv-reg-version-1p9.d: New test case. Dump the
+ CSR according to the priv spec 1.9.
+ * testsuite/gas/riscv/priv-reg-version-1p9p1.d: New test case. Dump the
+ CSR according to the priv spec 1.9.1.
+ * testsuite/gas/riscv/priv-reg-version-1p10.d: New test case. Dump the
+ CSR according to the priv spec 1.10.
+ * testsuite/gas/riscv/priv-reg-version-1p11.d: New test case. Dump the
+ CSR according to the priv spec 1.11.
+ * config/tc-riscv.c (md_show_usage): Add descriptions about
+ the new GAS options.
+ * doc/c-riscv.texi: Likewise.
+
+2020-05-19 Peter Bergner <bergner@linux.ibm.com>
+
+ * testsuite/gas/ppc/power9.s <dcbf, dcbfl, dcbflp>: Add tests.
+ * testsuite/gas/ppc/power9.d: Likewise.
+ * testsuite/gas/ppc/power10.s <dcbf, dcbfps, dcbstps, hwsync, lwsync,
+ pause_short, phwsync, plwsync, ptesync, stcisync, stncisync, stsync,
+ sync, wait, waitrsv>: Add tests.
+ * testsuite/gas/ppc/power10.d: Likewise.
+
+2020-05-19 Alexander Fedotov <alfedotov@gmail.com>
+
+ PR 25992
+ * config/tc-arm.c : Add arm_ext_v8r feature.
+ (it_fsm_post_encode): Check arm_ext_v8r feature.
+ (get_aeabi_cpu_arch_from_fset): Check arm_ext_v8r feature.
+
+2020-05-19 Alan Modra <amodra@gmail.com>
+
+ * write.c (write_contents): Use bfd_get_filename rather than
+ accessing bfd->filename directly. Use bfd_section_name rather
+ than accessing section->name directly.
+
+2020-05-19 Alan Modra <amodra@gmail.com>
+
+ * symbols.c (local_symbol_make): Init all of lsy_flags.
+
+2020-05-18 Alan Modra <amodra@gmail.com>
+
+ * symbols.c (resolve_symbol_value): Invoke LOCAL_SYMBOL_CHECK
+ before looking at add_symbol->sy_flags.
+
2020-05-18 Hongtao Liu <hongtao.liu@intel.com>
* config/tc-i386.c: Not handle lret/iret.
projects / thirdparty / binutils-gdb.git / blobdiff