+2020-06-30 H.J. Lu <hongjiu.lu@intel.com>
+
+ * NEWS: Mention x86 NaCl target support removal.
+ * config/tc-i386.c: Remove x86 NaCl target support.
+ * config/tc-i386.h: Likewise.
+ * configure.tgt: Likewise.
+ * testsuite/gas/i386/i386.exp: Likewise.
+ * testsuite/gas/i386/iamcu-1.d: Likewise.
+ * testsuite/gas/i386/iamcu-2.d: Likewise.
+ * testsuite/gas/i386/iamcu-3.d: Likewise.
+ * testsuite/gas/i386/iamcu-4.d: Likewise.
+ * testsuite/gas/i386/iamcu-5.d: Likewise.
+ * testsuite/gas/i386/k1om.d: Likewise.
+ * testsuite/gas/i386/l1om.d: Likewise.
+
+2020-06-30 Nelson Chu <nelson.chu@sifive.com>
+
+ * config/tc-riscv.c (riscv_csr_class_check): Removed. Move the
+ checking into riscv_csr_address.
+ (riscv_csr_version_check): Likewise.
+ (riscv_csr_address): New function. Return the suitable CSR address
+ after checking the ISA dependency and versions. Issue warnings if
+ we find any conflict and -mcsr-check is set. CSR_CLASS_F and
+ CSR_CLASS_DEBUG are unprivileged CSR for now, so don't check the
+ priv spec versions for them.
+ (reg_csr_lookup_internal): Call riscv_csr_address to find the
+ suitable CSR address.
+ * testsuite/gas/riscv/priv-reg-fail-fext.d: Remove -mpriv-spec=1.11.
+ * testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-fext.l: We don't care the
+ priv spec warnings here. These warnings are added by accident.
+ Remove them and only focus on the ISA dependency warnings.
+ * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Updated since
+ dscratch0 and dscratch1 are regarded as the unprivileged CSR rather
+ than the privileged ones.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
+ * testsuite/gas/riscv/priv-reg.s: Likewise. Add missing debug CSR.
+ * testsuite/gas/riscv/priv-reg-version-1p9.d: Likewise.
+ * testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise.
+ * testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise.
+ * testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise.
+ * testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
+ * testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
+
+2020-06-29 H.J. Lu <hongjiu.lu@intel.com>
+
+ * tc-i386.c (build_vex_prefix): Support VEX base opcode length > 1.
+ (md_assemble): Don't process ImmExt without operands.
+
+2020-06-29 Hans-Peter Nilsson <hp@bitrange.com>
+
+ PR gas/25331
+ * config/tc-mmix.c (md_assemble) <fixup for
+ BFD_RELOC_MMIX_BASE_PLUS_OFFSET>: This fixup affects 1 byte, not 8.
+ Also, set its fx_no_overflow.
+ (md_convert_frag) <case ENCODE_RELAX (STATE_PUSHJSTUB, STATE_ZERO)>:
+ Similarly this fixup affects 4 bytes, not 8 and needs its
+ fx_no_overflow set.
+ * config/tc-mmix.h (TC_FX_SIZE_SLACK): Don't define.
+ * testsuite/gas/mmix/pr25331.d, testsuite/gas/mmix/pr25331.s: New test.
+
+2020-06-29 Alan Modra <amodra@gmail.com>
+
+ * config/tc-s12z.c: Use C style comments.
+ * config/tc-z80.c: Likewise.
+ * config/tc-xtensa.c (emit_ld_r_n): Remove commented out code.
+
+2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (md_assemble): Process ImmExt without
+ operands.
+
+2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (check_VecOperands): Replace vecsib with sib.
+ Replace VecSIB128, VecSIB256 and VecSIB512 with VECSIB128,
+ VECSIB256 and VECSIB512, respectively.
+ (build_modrm_byte): Replace vecsib with sib.
+
+2020-06-26 Jan Beulich <jbeulich@suse.com>
+
+ * testsuite/gas/i386/nop-1-suffix.d: New.
+ * testsuite/gas/i386/i386.exp: Run new test.
+
+2020-06-26 Pat Bernardi <bernardi@adacore.com>
+
+ * config/tc-m68k.c (m68k_elf_gnu_attribute): New function.
+ (md_pseudo_table): Handle "gnu_attribute".
+ * doc/as.texi: Document GNU attribute for M68K.
+
+2020-06-25 Nick Clifton <nickc@redhat.com>
+
+ PR 26141
+ * config/tc-arm.c (arm_force_relocation): Force resolution of
+ BFD_RELOC_THUMB_PCREL_BRANCH12 relocations.
+ * testsuite/gas/arm/plt-1.d: Adjust expected disassembly.
+
+2020-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (md_assemble): Move call to process_immext()
+ ...
+ (process_operands): ... here.
+
+2020-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (process_suffix): Skip ambiguous operand size
+ diagnostic when there is a sizing prefix. Switch to word/dword/
+ qword encoding when there is a sizing prefix and no (explicit or
+ derived) suffix.
+ (update_imm): Handle presence of a sizing prefix.
+ * testsuite/gas/i386/noreg16-data32.d,
+ testsuite/gas/i386/noreg32-data16.d,
+ testsuite/gas/i386/noreg32-data16.e,
+ testsuite/gas/i386/noreg64-data16.d,
+ testsuite/gas/i386/noreg64-data16.e,
+ testsuite/gas/i386/noreg64-rex64.d: New.
+ * testsuite/gas/i386/i386.exp: Run new tests.
+ * testsuite/gas/i386/noreg32.s, testsuite/gas/i386/noreg64.s:
+ Introduce and use pfx* macros.
+ * testsuite/gas/i386/noreg16.s: Likewise. Replace 32-bit
+ addressing.
+ * testsuite/gas/i386/noreg16.d: Adjust expectations.
+
+2020-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * testsuite/gas/i386/avx-16bit.d,
+ testsuite/gas/i386/avx-scalar.d, testsuite/gas/i386/avx.d,
+ testsuite/gas/i386/avx512f-16bit.d,
+ testsuite/gas/i386/avx512f.d,
+ testsuite/gas/i386/evex-lig256.d,
+ testsuite/gas/i386/evex-lig512.d
+ testsuite/gas/i386/evex-wig1.d, testsuite/gas/i386/katmai.d,
+ testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg32.d,
+ testsuite/gas/i386/ptwrite.d, testsuite/gas/i386/simd.d,
+ testsuite/gas/i386/sse2-16bit.d,
+ testsuite/gas/i386/sse2.d, testsuite/gas/i386/sse2avx.d: Adjust
+ expectations.
+
+2020-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (md_assemble): Also reject explicit REX
+ prefixes with VEX and alike encoded insns. Zap consumed bits
+ from i.rex.
+ (output_insn): Don't ignore REX prefix for VEX and alike
+ encodings; abort() instead if encountered.
+ * testsuite/gas/i386/x86-64-pseudos.s: Move REX-with-VEX cases
+ ...
+ * testsuite/gas/i386/x86-64-pseudos-bad.s: ... here.
+ * testsuite/gas/i386/x86-64-pseudos.d,
+ testsuite/gas/i386/x86-64-pseudos-bad.l: Adjust expectations.
+
+2020-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (process_operands): Translate explicit REX
+ prefix into i.rex for SSE2AVX templates.
+ (set_rex_vrex): New helper.
+ (build_modrm_byte): Use it.
+ * testsuite/gas/i386/x86-64-sse2avx.s: Add cases with explict
+ REX prefixes.
+ * testsuite/gas/i386/x86-64-sse2avx.d: Adjust expectations.
+
+2020-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (cpu_flags_match): Only match SSE2AVX
+ templates when there's no data size prefix.
+ (md_assemble): Reject data size prefix also for legacy encoded
+ SIMD templates.
+ * testsuite/gas/i386/prefix32.s, testsuite/gas/i386/prefix64.s:
+ Uncomment previously not working line.
+ * testsuite/gas/i386/sse2avx.s: Add ldmxcsr/stmxcsr cases with
+ data16 prefix.
+ * testsuite/gas/i386/prefix32.l, testsuite/gas/i386/prefix64.l,
+ testsuite/gas/i386/sse2avx.d: Adjust expectations.
+
+2020-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (build_evex_prefix): Drop early setting of
+ vec_length.
+
2020-06-23 Nelson Chu <nelson.chu@sifive.com>
* config/tc-riscv.c (explicit_priv_attr): Rename explicit_csr to
projects / thirdparty / binutils-gdb.git / blobdiff