Remove x86 NaCl target support

[thirdparty/binutils-gdb.git] / gas / ChangeLog

diff --git a/gas/ChangeLog b/gas/ChangeLog
index a5ffe08eb4d41bb298096332318b2f3d13760bb0..c249180a0195f2fda6cd27fda269c306daa1a34e 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,80 @@
+2020-06-30  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * NEWS: Mention x86 NaCl target support removal.
+       * config/tc-i386.c: Remove x86 NaCl target support.
+       * config/tc-i386.h: Likewise.
+       * configure.tgt: Likewise.
+       * testsuite/gas/i386/i386.exp: Likewise.
+       * testsuite/gas/i386/iamcu-1.d: Likewise.
+       * testsuite/gas/i386/iamcu-2.d: Likewise.
+       * testsuite/gas/i386/iamcu-3.d: Likewise.
+       * testsuite/gas/i386/iamcu-4.d: Likewise.
+       * testsuite/gas/i386/iamcu-5.d: Likewise.
+       * testsuite/gas/i386/k1om.d: Likewise.
+       * testsuite/gas/i386/l1om.d: Likewise.
+
+2020-06-30  Nelson Chu  <nelson.chu@sifive.com>
+
+       * config/tc-riscv.c (riscv_csr_class_check): Removed.  Move the
+       checking into riscv_csr_address.
+       (riscv_csr_version_check): Likewise.
+       (riscv_csr_address): New function.  Return the suitable CSR address
+       after checking the ISA dependency and versions.  Issue warnings if
+       we find any conflict and -mcsr-check is set.  CSR_CLASS_F and
+       CSR_CLASS_DEBUG are unprivileged CSR for now, so don't check the
+       priv spec versions for them.
+       (reg_csr_lookup_internal): Call riscv_csr_address to find the
+       suitable CSR address.
+       * testsuite/gas/riscv/priv-reg-fail-fext.d: Remove -mpriv-spec=1.11.
+       * testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
+       * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
+       * testsuite/gas/riscv/priv-reg-fail-fext.l:  We don't care the
+       priv spec warnings here.  These warnings are added by accident.
+       Remove them and only focus on the ISA dependency warnings.
+       * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
+       * testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
+       * testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Updated since
+       dscratch0 and dscratch1 are regarded as the unprivileged CSR rather
+       than the privileged ones.
+       * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
+       * testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
+       * testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
+       * testsuite/gas/riscv/priv-reg.s: Likewise.  Add missing debug CSR.
+       * testsuite/gas/riscv/priv-reg-version-1p9.d: Likewise.
+       * testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise.
+       * testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise.
+       * testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise.
+       * testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
+       * testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
+
+2020-06-29  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * tc-i386.c (build_vex_prefix): Support VEX base opcode length > 1.
+       (md_assemble): Don't process ImmExt without operands.
+
+2020-06-29  Hans-Peter Nilsson  <hp@bitrange.com>
+
+       PR gas/25331
+       * config/tc-mmix.c (md_assemble) <fixup for
+       BFD_RELOC_MMIX_BASE_PLUS_OFFSET>: This fixup affects 1 byte, not 8.
+       Also, set its fx_no_overflow.
+       (md_convert_frag) <case ENCODE_RELAX (STATE_PUSHJSTUB, STATE_ZERO)>: 
+       Similarly this fixup affects 4 bytes, not 8 and needs its
+       fx_no_overflow set.
+       * config/tc-mmix.h (TC_FX_SIZE_SLACK): Don't define.
+       * testsuite/gas/mmix/pr25331.d, testsuite/gas/mmix/pr25331.s: New test.
+
+2020-06-29  Alan Modra  <amodra@gmail.com>
+
+       * config/tc-s12z.c: Use C style comments.
+       * config/tc-z80.c: Likewise.
+       * config/tc-xtensa.c (emit_ld_r_n): Remove commented out code.
+
+2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * config/tc-i386.c (md_assemble): Process ImmExt without
+       operands.
+
 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
 
        * config/tc-i386.c (check_VecOperands): Replace vecsib with sib.