/* bfin-defs.h ADI Blackfin gas header file
- Copyright 2005
- Free Software Foundation, Inc.
+ Copyright (C) 2005-2022 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2, or (at your option)
+ the Free Software Foundation; either version 3, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
02110-1301, USA. */
#ifndef BFIN_PARSE_H
-#define BFIN_PARSE_H
+#define BFIN_PARSE_H
-#include <bfd.h>
-#include "as.h"
+#include "opcode/bfin.h"
#define PCREL 1
-#define CODE_FRAG_SIZE 4096 /* 1 page. */
+#define CODE_FRAG_SIZE 4096 /* 1 page. */
/* Definition for all status bits. */
c_uimm2,
c_uimm3,
c_imm3,
- c_pcrel4,
+ c_pcrel4,
c_imm4,
c_uimm4s4,
c_uimm4,
c_negimm5s4,
c_imm5,
c_uimm5,
- c_imm6,
+ c_imm6,
c_imm7,
c_imm8,
c_uimm8,
c_uimm8s4,
c_pcrel8s4,
c_lppcrel10,
- c_pcrel10,
+ c_pcrel10,
c_pcrel12,
c_imm16s4,
c_luimm16,
c_huimm16,
c_rimm16,
c_imm16s2,
- c_uimm16s4,
+ c_uimm16s4,
c_uimm16,
- c_pcrel24
+ c_pcrel24
} const_forms_t;
#define T_REG_A 0x40
/* All registers above this value don't
- belong to a usuable register group. */
+ belong to a usable register group. */
#define T_NOGROUP 0xa0
/* Flags. */
-#define F_REG_ALL 0x1000
-#define F_REG_HIGH 0x2000 /* Half register: high half. */
+#define F_REG_NONE 0
+#define F_REG_HIGH 1
+#define F_REG_LOW 2
enum machine_registers
{
- REG_R0 = T_REG_R, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
+ REG_R0 = T_REG_R, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
REG_P0 = T_REG_P, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
REG_I0 = T_REG_I, REG_I1, REG_I2, REG_I3,
- REG_M0 = T_REG_M, REG_M1, REG_M2, REG_M3,
+ REG_M0 = T_REG_M, REG_M1, REG_M2, REG_M3,
REG_B0 = T_REG_B, REG_B1, REG_B2, REG_B3,
- REG_L0 = T_REG_L, REG_L1, REG_L2, REG_L3,
+ REG_L0 = T_REG_L, REG_L1, REG_L2, REG_L3,
REG_A0x = T_REG_A, REG_A0w, REG_A1x, REG_A1w,
REG_ASTAT = 0x46,
REG_RETS = 0x47,
REG_LC0 = 0x60, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1,
REG_CYCLES, REG_CYCLES2,
REG_USP = 0x70, REG_SEQSTAT, REG_SYSCFG,
- REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
+ REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT,
/* These don't have groups. */
REG_sftreset = T_NOGROUP, REG_omode, REG_excause, REG_emucause,
REG_A0 = 0xc0, REG_A1, REG_CC,
/* Pseudo registers, used only for distinction from symbols. */
REG_RL0, REG_RL1, REG_RL2, REG_RL3,
- REG_RL4, REG_RL5, REG_RL6, REG_RL7,
+ REG_RL4, REG_RL5, REG_RL6, REG_RL7,
REG_RH0, REG_RH1, REG_RH2, REG_RH3,
- REG_RH4, REG_RH5, REG_RH6, REG_RH7,
+ REG_RH4, REG_RH5, REG_RH6, REG_RH7,
REG_LASTREG
};
{
S_AZ = 0,
S_AN,
+ S_AC0_COPY,
+ S_V_COPY,
S_AQ = 6,
+ S_RND_MOD = 8,
S_AC0 = 12,
S_AC1,
S_AV0 = 16,
S_AV1S,
S_V = 24,
S_VS = 25
-};
+};
enum reg_class
LIM_REG_CLASSES
};
-/* mmod field. */
-#define M_S2RND 1
-#define M_T 2
-#define M_W32 3
-#define M_FU 4
-#define M_TFU 6
-#define M_IS 8
-#define M_ISS2 9
-#define M_IH 11
-#define M_IU 12
-
/* Register type checking macros. */
#define CODE_MASK 0x07
#define REG_SAME(a, b) ((a).regno == (b).regno)
#define REG_EQUAL(a, b) (((a).regno & CODE_MASK) == ((b).regno & CODE_MASK))
-#define REG_CLASS(a) ((a.regno) & 0xf0)
+#define REG_CLASS(a) ((a).regno & 0xf0)
#define IS_A1(a) ((a).regno == REG_A1)
-#define IS_H(a) ((a).regno & F_REG_HIGH ? 1: 0)
-#define IS_EVEN(r) (r.regno % 2 == 0)
+#define IS_H(a) ((a).flags & F_REG_HIGH ? 1: 0)
+#define IS_EVEN(r) ((r).regno % 2 == 0)
#define IS_HCOMPL(a, b) (REG_EQUAL(a, b) && \
- ((a).regno & F_REG_HIGH) != ((b).regno & F_REG_HIGH))
+ ((a).flags & F_REG_HIGH) != ((b).flags & F_REG_HIGH))
/* register type checking. */
#define _TYPECHECK(r, x) (((r).regno & CLASS_MASK) == T_REG_##x)
#define IS_BREG(r) (((r).regno & 0xf4) == T_REG_B)
#define IS_LREG(r) (((r).regno & 0xf4) == T_REG_L)
#define IS_CREG(r) ((r).regno == REG_LC0 || (r).regno == REG_LC1)
+#define IS_EMUDAT(r) ((r).regno == REG_EMUDAT)
#define IS_ALLREG(r) ((r).regno < T_NOGROUP)
+#define IS_GENREG(r) \
+ (IS_DREG (r) || IS_PREG (r) \
+ || (r).regno == REG_A0x || (r).regno == REG_A0w \
+ || (r).regno == REG_A1x || (r).regno == REG_A1w)
+
+#define IS_DAGREG(r) \
+ (IS_IREG (r) || IS_MREG (r) || IS_BREG (r) || IS_LREG (r))
+
+#define IS_SYSREG(r) \
+ ((r).regno == REG_ASTAT || (r).regno == REG_SEQSTAT \
+ || (r).regno == REG_SYSCFG || (r).regno == REG_RETI \
+ || (r).regno == REG_RETX || (r).regno == REG_RETN \
+ || (r).regno == REG_RETE || (r).regno == REG_RETS \
+ || (r).regno == REG_LC0 || (r).regno == REG_LC1 \
+ || (r).regno == REG_LT0 || (r).regno == REG_LT1 \
+ || (r).regno == REG_LB0 || (r).regno == REG_LB1 \
+ || (r).regno == REG_CYCLES || (r).regno == REG_CYCLES2 \
+ || (r).regno == REG_EMUDAT)
+
/* Expression value macros. */
typedef enum
-{
+{
ones_compl,
twos_compl,
mult,
struct expressionS;
#define SYMBOL_T symbolS*
-
+
struct expression_cell
{
int value;
int pcrel;
int reloc;
};
-
+
#define INSTR_T struct bfin_insn*
-#define EXPR_T struct expression_cell*
+#define EXPR_T struct expression_cell*
typedef struct expr_node_struct Expr_Node;
-
+
extern INSTR_T gencode (unsigned long x);
-extern INSTR_T conscode (INSTR_T head, INSTR_T tail);
+extern INSTR_T conscode (INSTR_T head, INSTR_T tail);
extern INSTR_T conctcode (INSTR_T head, INSTR_T tail);
extern INSTR_T note_reloc
(INSTR_T code, Expr_Node *, int reloc,int pcrel);
(INSTR_T code, const char * sym, int reloc, int pcrel);
extern INSTR_T note_reloc2
(INSTR_T code, const char *symbol, int reloc, int value, int pcrel);
-
+
/* Types of expressions. */
-typedef enum
+typedef enum
{
Expr_Node_Binop, /* Binary operator. */
Expr_Node_Unop, /* Unary operator. */
} Expr_Node_Type;
/* Types of operators. */
-typedef enum
+typedef enum
{
Expr_Op_Type_Add,
Expr_Op_Type_Sub,
typedef union
{
const char *s_value; /* if relocation symbol, the text. */
- int i_value; /* if constant, the value. */
+ long long i_value; /* if constant, the value. */
Expr_Op_Type op_value; /* if operator, the value. */
} Expr_Node_Value;
/* Operations on the expression node. */
-Expr_Node *Expr_Node_Create (Expr_Node_Type type,
- Expr_Node_Value value,
- Expr_Node *Left_Child,
+Expr_Node *Expr_Node_Create (Expr_Node_Type type,
+ Expr_Node_Value value,
+ Expr_Node *Left_Child,
Expr_Node *Right_Child);
/* Generate the reloc structure as a series of instructions. */
INSTR_T Expr_Node_Gen_Reloc (Expr_Node *head, int parent_reloc);
-
+
#define MKREF(x) mkexpr (0,x)
-#define ALLOCATE(x) malloc (x)
-
+
#define NULL_CODE ((INSTR_T) 0)
#ifndef EXPR_VALUE
extern int debug_codeselection;
-void error (char *format, ...);
+void error (const char *format, ...);
void warn (char *format, ...);
int semantic_error (char *syntax);
void semantic_error_2 (char *syntax);
EXPR_T mkexpr (int, SYMBOL_T);
-extern void bfin_equals (Expr_Node *sym);
/* Defined in bfin-lex.l. */
void set_start_state (void);
+extern int insn_regmask (int, int);
#ifdef __cplusplus
}
#endif
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