/* tc-mep.c -- Assembler for the Toshiba Media Processor.
- Copyright (C) 2001-2014 Free Software Foundation, Inc.
+ Copyright (C) 2001-2021 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
#include "cgen.h"
#include "elf/common.h"
#include "elf/mep.h"
-#include "libbfd.h"
#include "xregex.h"
/* Structure to hold all of the different components describing
static int optbitset = 0;
int
-md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
+md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
{
int i, idx;
switch (c)
/* The MeP version of the cgen parse_operand function. The only difference
from the standard version is that we want to avoid treating '$foo' and
'($foo...)' as references to a symbol called '$foo'. The chances are
- that '$foo' is really a misspelt register. */
+ that '$foo' is really a misspelled register. */
static const char *
mep_parse_operand (CGEN_CPU_DESC cd, enum cgen_parse_operand_type want,
}
void
-md_begin ()
+md_begin (void)
{
/* Initialize the `cgen' interface. */
gas_cgen_initialize_saved_fixups_array();
}
-/* Variant of mep_cgen_assemble_insn. Assemble insn STR of cpu CD as a
+/* Variant of mep_cgen_assemble_insn. Assemble insn STR of cpu CD as a
coprocessor instruction, if possible, into FIELDS, BUF, and INSN. */
static const CGEN_INSN *
const char *errmsg = NULL;
/* The instructions are stored in hashed lists. */
- ilist = CGEN_ASM_LOOKUP_INSN (gas_cgen_cpu_desc,
+ ilist = CGEN_ASM_LOOKUP_INSN (gas_cgen_cpu_desc,
CGEN_INSN_MNEMONIC (pinsn));
start = str;
for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
{
const CGEN_INSN *insn = ilist->insn;
- if (strcmp (CGEN_INSN_MNEMONIC (ilist->insn),
+ if (strcmp (CGEN_INSN_MNEMONIC (ilist->insn),
CGEN_INSN_MNEMONIC (pinsn)) == 0
&& MEP_INSN_COP_P (ilist->insn)
&& mep_cgen_insn_supported (cd, insn))
errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields);
if (errmsg != NULL)
continue;
-
+
errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf,
(bfd_vma) 0);
if (errmsg != NULL)
an internally parallel core or an internally parallel coprocessor,
neither of which are supported at this time. */
if ( num_insns_saved > 2 )
- as_fatal("Internally paralled cores and coprocessors not supported.");
+ as_fatal("Internally paralleled cores and coprocessors not supported.");
/* If there are no insns saved, that's ok. Just return. This will
happen when mep_process_saved_insns is called when the end of the
as_bad (_("core and copro insn lengths must total 32 bits."));
}
else
- as_bad (_("vliw group must consist of 1 core and 1 copro insn."));
+ as_bad (_("vliw group must consist of 1 core and 1 copro insn."));
}
else
{
1. The instruction is a 32 bit core or coprocessor insn and
can be executed by itself. Valid.
- 2. The instrucion is a core instruction for which a cop nop
+ 2. The instruction is a core instruction for which a cop nop
exists. In this case, insert the cop nop into the saved
insn array after the core insn and return. Valid.
CGEN_INSN_VLIW32_NO_MATCHING_NOP))
as_fatal ("No valid nop.");
- /* At this point we know that we have a single 16-bit insn that has
- a matching nop. We have to assemble it and put it into the saved
+ /* At this point we know that we have a single 16-bit insn that has
+ a matching nop. We have to assemble it and put it into the saved
insn and fixup chain arrays. */
if (insn0iscopro)
{
char *errmsg;
mep_insn insn;
-
+
/* Move the insn and it's fixups to the second element of the
- saved insns arrary and insert a 16 bit core nope into the
+ saved insns array and insert a 16 bit core nope into the
first element. */
insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "nop",
&insn.fields, insn.buffer,
/* Move the insn in element 0 to element 1 and insert the
nop into element 0. Move the fixups in element 0 to
- element 1 and save the current fixups to element 0.
+ element 1 and save the current fixups to element 0.
Really there aren't any fixups at this point because we're
inserting a nop but we might as well be general so that
if there's ever a need to insert a general insn, we'll
1. The instruction is a 64 bit coprocessor insn and can be
executed by itself. Valid.
- 2. The instrucion is a core instruction for which a cop nop
+ 2. The instruction is a core instruction for which a cop nop
exists. In this case, insert the cop nop into the saved
insn array after the core insn and return. Valid.
we have to abort. */
/* If the insn is 64 bits long, it can run alone. The size check
- is done indepependantly of whether the insn is core or copro
+ is done independently of whether the insn is core or copro
in case 64 bit coprocessor insns are added later. */
if (insn0length == 64)
return;
nop has been added, then make the necessary changes and
handle its assembly and insertion here. Otherwise,
go figure out why either:
-
+
1. The assembler thinks that there is a 32-bit core nop
to match a 32-bit coprocessor insn, or
2. The assembler thinks that there is a 48-bit core nop
/* Move the insn in element 0 to element 1 and insert the
nop into element 0. Move the fixups in element 0 to
- element 1 and save the current fixups to element 0.
+ element 1 and save the current fixups to element 0.
Really there aren't any fixups at this point because we're
inserting a nop but we might as well be general so that
if there's ever a need to insert a general insn, we'll
#if CGEN_INT_INSN_P
cgen_put_insn_value (gas_cgen_cpu_desc, (unsigned char *) temp, 32,
- m->buffer[0]);
+ m->buffer[0], gas_cgen_cpu_desc->insn_endian);
#else
memcpy (temp, m->buffer, byte_len);
#endif
#endif /* MEP_IVC2_SUPPORTED */
/* The scheduling functions are just filters for invalid combinations.
- If there is a violation, they terminate assembly. Otherise they
- just fall through. Succesful combinations cause no side effects
+ If there is a violation, they terminate assembly. Otherwise they
+ just fall through. Successful combinations cause no side effects
other than valid nop insertion. */
static void
mep_check_parallel_scheduling (void)
{
/* This is where we will eventually read the config information
- and choose which scheduling checking function to call. */
+ and choose which scheduling checking function to call. */
#ifdef MEP_IVC2_SUPPORTED
if (mep_cop == EF_MEP_COP_IVC2)
mep_check_ivc2_scheduling ();
+ copro insn
We want to handle the general case where more than
- one instruction can be preceeded by a +. This will
+ one instruction can be preceded by a +. This will
happen later if we add support for internally parallel
coprocessors. We'll make the parsing nice and general
so that it can handle an arbitrary number of insns
int thisInsnIsCopro = 0;
mep_insn insn;
int i;
-
+
/* Initialize the insn buffer */
-
+
if (! CGEN_INT_INSN_P)
for (i=0; i < CGEN_MAX_INSN_SIZE; i++)
insn.buffer[i]='\0';
/* Check for a + with a core insn and abort if found. */
if (!thisInsnIsCopro)
{
- as_fatal("A core insn cannot be preceeded by a +.\n");
+ as_fatal("A core insn cannot be preceded by a +.\n");
return;
}
valueT
md_section_align (segT segment, valueT size)
{
- int align = bfd_get_section_alignment (stdoutput, segment);
- return ((size + (1 << align) - 1) & (-1 << align));
+ int align = bfd_section_alignment (segment);
+ return ((size + (1 << align) - 1) & -(1 << align));
}
|| S_IS_WEAK (fragP->fr_symbol)
#ifdef MEP_IVC2_SUPPORTED
|| (mep_cop == EF_MEP_COP_IVC2
- && bfd_get_section_flags (stdoutput, segment) & SEC_MEP_VLIW)
+ && bfd_section_flags (segment) & SEC_MEP_VLIW)
#endif /* MEP_IVC2_SUPPORTED */
)
{
}
if (MEP_VLIW && ! MEP_VLIW64
- && (bfd_get_section_flags (stdoutput, segment) & SEC_MEP_VLIW))
+ && (bfd_section_flags (segment) & SEC_MEP_VLIW))
{
/* Use 32 bit branches for vliw32 so the vliw word is not split. */
switch (fragP->fr_cgen.insn->base->num)
{
case MEP_INSN_BSR12:
- fragP->fr_subtype = insn_to_subtype
+ fragP->fr_subtype = insn_to_subtype
(subtype_mappings[fragP->fr_subtype].insn_for_extern);
break;
case MEP_INSN_BEQZ:
#ifdef MEP_IVC2_SUPPORTED
if (mep_cop == EF_MEP_COP_IVC2
- && bfd_get_section_flags (stdoutput, segment) & SEC_MEP_VLIW)
+ && bfd_section_flags (segment) & SEC_MEP_VLIW)
return 0;
#endif /* MEP_IVC2_SUPPORTED */
long rv = relax_frag (segment, fragP, stretch);
#ifdef MEP_IVC2_SUPPORTED
if (mep_cop == EF_MEP_COP_IVC2
- && bfd_get_section_flags (stdoutput, segment) & SEC_MEP_VLIW)
+ && bfd_section_flags (segment) & SEC_MEP_VLIW)
return 0;
#endif
return rv;
}
void
-md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
segT seg ATTRIBUTE_UNUSED,
fragS *fragP)
{
- int addend, rn, bit = 0;
+ uint32_t addend, rn, bit = 0;
int operand;
int where = fragP->fr_opcode - fragP->fr_literal;
int e = target_big_endian ? 0 : 1;
int core_mode;
#ifdef MEP_IVC2_SUPPORTED
- if (bfd_get_section_flags (stdoutput, seg) & SEC_MEP_VLIW
+ if (bfd_section_flags (seg) & SEC_MEP_VLIW
&& mep_cop == EF_MEP_COP_IVC2)
core_mode = 0;
else
/* The default relax_frag doesn't change the state if there is no
growth, so we must manually handle converting out-of-range BEQ
instructions to JMP. */
- if (addend <= 65535 && addend >= -65536)
+ if (addend + 65536 < 131071)
{
if (core_mode)
fragP->fr_fix += 2;
operand = MEP_OPERAND_PCREL17A2;
break;
}
- /* ...FALLTHROUGH... */
+ /* Fall through. */
case MEP_INSN_JMP:
addend = target_address_for (fragP);
case MEP_INSN_BNEZ:
bit = 1;
+ /* Fall through. */
case MEP_INSN_BEQZ:
fragP->fr_opcode[1^e] = bit | (addend & 0xfe);
operand = MEP_OPERAND_PCREL8A2;
case MEP_INSN_BNEI:
bit = 4;
+ /* Fall through. */
case MEP_INSN_BEQI:
if (subtype_mappings[fragP->fr_subtype].growth)
{
switch (fixP->fx_cgen.opinfo)
{
case BFD_RELOC_MEP_LOW16:
- *valP = ((long)(*valP & 0xffff)) << 16 >> 16;
+ *valP = ((*valP & 0xffff) ^ 0x8000) - 0x8000;
break;
case BFD_RELOC_MEP_HI16U:
*valP >>= 16;
break;
}
- /* Now call cgen's md_aply_fix. */
+ /* Now call cgen's md_apply_fix. */
gas_cgen_md_apply_fix (fixP, valP, seg);
}
#ifdef OBJ_COMPLEX_RELC
/* coalescing this into RELOC_MEP_16 is actually a bug,
since it's a signed operand. let the relc code handle it. */
- return BFD_RELOC_RELC;
+ return BFD_RELOC_RELC;
#endif
case MEP_OPERAND_UIMM16:
default:
#ifdef OBJ_COMPLEX_RELC
- /* this is not an error, yet.
+ /* this is not an error, yet.
pass it to the linker. */
return BFD_RELOC_RELC;
#endif
tc_gen_reloc. */
void
-mep_frob_file ()
+mep_frob_file (void)
{
struct mep_hi_fixup * l;
number_to_chars_littleendian (buf, val, n);
}
-char *
+const char *
md_atof (int type, char *litP, int *sizeP)
{
return ieee_md_atof (type, litP, sizeP, TRUE);
}
bfd_vma
-mep_elf_section_letter (int letter, char **ptrmsg)
+mep_elf_section_letter (int letter, const char **ptrmsg)
{
if (letter == 'v')
return SHF_MEP_VLIW;
{
flagword applicable = bfd_applicable_section_flags (stdoutput);
vtext_section = subseg_new (VTEXT_SECTION_NAME, 0);
- bfd_set_section_flags (stdoutput, vtext_section,
+ bfd_set_section_flags (vtext_section,
applicable & (SEC_ALLOC | SEC_LOAD | SEC_RELOC
| SEC_CODE | SEC_READONLY
| SEC_MEP_VLIW));
{
/* Take care of any insns left to be parallelized when the file ends.
This is mainly here to handle the case where the file ends with an
- insn preceeded by a + or the file ends unexpectedly. */
+ insn preceded by a + or the file ends unexpectedly. */
if (mode == VLIW)
mep_process_saved_insns ();
}
pluspresent = 0;
}
- return 1;
+ return 1;
}
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