-@c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
-@c 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
+@c Copyright (C) 1996-2021 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@table @code
-@cindex @code{-mcpu=} command line option, ARM
+@cindex @code{-mcpu=} command-line option, ARM
@item -mcpu=@var{processor}[+@var{extension}@dots{}]
This option specifies the target processor. The assembler will issue an
error message if an attempt is made to assemble an instruction which
will not execute on the target processor. The following processor names are
-recognized:
+recognized:
@code{arm1},
@code{arm2},
@code{arm250},
@code{arm1020e},
@code{arm1022e},
@code{arm1026ej-s},
+@code{fa606te} (Faraday FA606TE processor),
+@code{fa616te} (Faraday FA616TE processor),
@code{fa626te} (Faraday FA626TE processor),
+@code{fmp626} (Faraday FMP626 processor),
@code{fa726te} (Faraday FA726TE processor),
@code{arm1136j-s},
@code{arm1136jf-s},
@code{mpcore},
@code{mpcorenovfp},
@code{cortex-a5},
+@code{cortex-a7},
@code{cortex-a8},
@code{cortex-a9},
@code{cortex-a15},
+@code{cortex-a17},
+@code{cortex-a32},
+@code{cortex-a35},
+@code{cortex-a53},
+@code{cortex-a55},
+@code{cortex-a57},
+@code{cortex-a72},
+@code{cortex-a73},
+@code{cortex-a75},
+@code{cortex-a76},
+@code{cortex-a76ae},
+@code{cortex-a77},
+@code{cortex-a78},
+@code{cortex-a78ae},
+@code{cortex-a78c},
+@code{ares},
@code{cortex-r4},
@code{cortex-r4f},
+@code{cortex-r5},
+@code{cortex-r7},
+@code{cortex-r8},
+@code{cortex-r52},
+@code{cortex-m35p},
+@code{cortex-m33},
+@code{cortex-m23},
+@code{cortex-m7},
@code{cortex-m4},
@code{cortex-m3},
@code{cortex-m1},
@code{cortex-m0},
+@code{cortex-m0plus},
+@code{cortex-x1},
+@code{exynos-m1},
+@code{marvell-pj4},
+@code{marvell-whitney},
+@code{neoverse-n1},
+@code{neoverse-n2},
+@code{neoverse-v1},
+@code{xgene1},
+@code{xgene2},
@code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
@code{i80200} (Intel XScale processor)
-@code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
+@code{iwmmxt} (Intel XScale processor with Wireless MMX technology coprocessor)
and
-@code{xscale}.
+@code{xscale}.
The special name @code{all} may be used to allow the
assembler to accept instructions valid for any ARM processor.
-In addition to the basic instruction set, the assembler can be told to
-accept various extension mnemonics that extend the processor using the
+In addition to the basic instruction set, the assembler can be told to
+accept various extension mnemonics that extend the processor using the
co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
-is equivalent to specifying @code{-mcpu=ep9312}.
+is equivalent to specifying @code{-mcpu=ep9312}.
-Multiple extensions may be specified, separated by a @code{+}. The
+Multiple extensions may be specified, separated by a @code{+}. The
extensions should be specified in ascending alphabetical order.
-Extension mnemonics may also be removed from those the assembler accepts.
-This is done be prepending @code{no} to the option that adds the extension.
-Extensions that are removed should be listed after all extensions which have
-been added, again in ascending alphabetical order. For example,
+Some extensions may be restricted to particular architectures; this is
+documented in the list of extensions below.
+
+Extension mnemonics may also be removed from those the assembler accepts.
+This is done be prepending @code{no} to the option that adds the extension.
+Extensions that are removed should be listed after all extensions which have
+been added, again in ascending alphabetical order. For example,
@code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
-The following extensions are currently supported:
+The following extensions are currently supported:
+@code{bf16} (BFloat16 extensions for v8.6-A architecture),
+@code{i8mm} (Int8 Matrix Multiply extensions for v8.6-A architecture),
+@code{crc}
+@code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
+@code{dotprod} (Dot Product Extensions for v8.2-A architecture, implies @code{fp+simd}),
+@code{fp} (Floating Point Extensions for v8-A architecture),
+@code{fp16} (FP16 Extensions for v8.2-A architecture, implies @code{fp}),
+@code{fp16fml} (FP16 Floating Point Multiplication Variant Extensions for v8.2-A architecture, implies @code{fp16}),
+@code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
@code{iwmmxt},
@code{iwmmxt2},
+@code{xscale},
@code{maverick},
+@code{mp} (Multiprocessing Extensions for v7-A and v7-R
+architectures),
+@code{os} (Operating System for v6M architecture),
+@code{predres} (Execution and Data Prediction Restriction Instruction for
+v8-A architectures, added by default from v8.5-A),
+@code{sb} (Speculation Barrier Instruction for v8-A architectures, added by
+default from v8.5-A),
+@code{sec} (Security Extensions for v6K and v7-A architectures),
+@code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
+@code{virt} (Virtualization Extensions for v7-A architecture, implies
+@code{idiv}),
+@code{pan} (Privileged Access Never Extensions for v8-A architecture),
+@code{ras} (Reliability, Availability and Serviceability extensions
+for v8-A architecture),
+@code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
+@code{simd})
and
@code{xscale}.
-@cindex @code{-march=} command line option, ARM
+@cindex @code{-march=} command-line option, ARM
@item -march=@var{architecture}[+@var{extension}@dots{}]
This option specifies the target architecture. The assembler will issue
an error message if an attempt is made to assemble an instruction which
-will not execute on the target architecture. The following architecture
-names are recognized:
+will not execute on the target architecture. The following architecture
+names are recognized:
@code{armv1},
@code{armv2},
@code{armv2a},
@code{armv6j},
@code{armv6k},
@code{armv6z},
-@code{armv6zk},
+@code{armv6kz},
+@code{armv6-m},
+@code{armv6s-m},
@code{armv7},
@code{armv7-a},
+@code{armv7ve},
@code{armv7-r},
@code{armv7-m},
@code{armv7e-m},
-@code{iwmmxt}
+@code{armv8-a},
+@code{armv8.1-a},
+@code{armv8.2-a},
+@code{armv8.3-a},
+@code{armv8-r},
+@code{armv8.4-a},
+@code{armv8.5-a},
+@code{armv8-m.base},
+@code{armv8-m.main},
+@code{armv8.1-m.main},
+@code{armv8.6-a},
+@code{iwmmxt},
+@code{iwmmxt2}
and
@code{xscale}.
If both @code{-mcpu} and
@code{-march} are specified, the assembler will use
the setting for @code{-mcpu}.
-The architecture option can be extended with the same instruction set
-extension options as the @code{-mcpu} option.
-
-@cindex @code{-mfpu=} command line option, ARM
+The architecture option can be extended with a set extension options. These
+extensions are context sensitive, i.e. the same extension may mean different
+things when used with different architectures. When used together with a
+@code{-mfpu} option, the union of both feature enablement is taken.
+See their availability and meaning below:
+
+For @code{armv5te}, @code{armv5texp}, @code{armv5tej}, @code{armv6}, @code{armv6j}, @code{armv6k}, @code{armv6z}, @code{armv6kz}, @code{armv6zk}, @code{armv6t2}, @code{armv6kt2} and @code{armv6zt2}:
+
+@code{+fp}: Enables VFPv2 instructions.
+@code{+nofp}: Disables all FPU instrunctions.
+
+For @code{armv7}:
+
+@code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
+@code{+nofp}: Disables all FPU instructions.
+
+For @code{armv7-a}:
+
+@code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
+@code{+vfpv3-d16}: Alias for @code{+fp}.
+@code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers.
+@code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point
+conversion instructions and 16 double-word registers.
+@code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion
+instructions and 32 double-word registers.
+@code{+vfpv4-d16}: Enables VFPv4 instructions with 16 double-word registers.
+@code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers.
+@code{+simd}: Enables VFPv3 and NEONv1 instructions with 32 double-word
+registers.
+@code{+neon}: Alias for @code{+simd}.
+@code{+neon-vfpv3}: Alias for @code{+simd}.
+@code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and
+NEONv1 instructions with 32 double-word registers.
+@code{+neon-vfpv4}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32
+double-word registers.
+@code{+mp}: Enables Multiprocessing Extensions.
+@code{+sec}: Enables Security Extensions.
+@code{+nofp}: Disables all FPU and NEON instructions.
+@code{+nosimd}: Disables all NEON instructions.
+
+For @code{armv7ve}:
+
+@code{+fp}: Enables VFPv4 instructions with 16 double-word registers.
+@code{+vfpv4-d16}: Alias for @code{+fp}.
+@code{+vfpv3-d16}: Enables VFPv3 instructions with 16 double-word registers.
+@code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers.
+@code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point
+conversion instructions and 16 double-word registers.
+@code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion
+instructions and 32 double-word registers.
+@code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers.
+@code{+simd}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32
+double-word registers.
+@code{+neon-vfpv4}: Alias for @code{+simd}.
+@code{+neon}: Enables VFPv3 and NEONv1 instructions with 32 double-word
+registers.
+@code{+neon-vfpv3}: Alias for @code{+neon}.
+@code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and
+NEONv1 instructions with 32 double-word registers.
+double-word registers.
+@code{+nofp}: Disables all FPU and NEON instructions.
+@code{+nosimd}: Disables all NEON instructions.
+
+For @code{armv7-r}:
+
+@code{+fp.sp}: Enables single-precision only VFPv3 instructions with 16
+double-word registers.
+@code{+vfpv3xd}: Alias for @code{+fp.sp}.
+@code{+fp}: Enables VFPv3 instructions with 16 double-word registers.
+@code{+vfpv3-d16}: Alias for @code{+fp}.
+@code{+vfpv3xd-fp16}: Enables single-precision only VFPv3 and half
+floating-point conversion instructions with 16 double-word registers.
+@code{+vfpv3-d16-fp16}: Enables VFPv3 and half precision floating-point
+conversion instructions with 16 double-word registers.
+@code{+idiv}: Enables integer division instructions in ARM mode.
+@code{+nofp}: Disables all FPU instructions.
+
+For @code{armv7e-m}:
+
+@code{+fp}: Enables single-precision only VFPv4 instructions with 16
+double-word registers.
+@code{+vfpvf4-sp-d16}: Alias for @code{+fp}.
+@code{+fpv5}: Enables single-precision only VFPv5 instructions with 16
+double-word registers.
+@code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers.
+@code{+fpv5-d16"}: Alias for @code{+fp.dp}.
+@code{+nofp}: Disables all FPU instructions.
+
+For @code{armv8-m.main}:
+
+@code{+dsp}: Enables DSP Extension.
+@code{+fp}: Enables single-precision only VFPv5 instructions with 16
+double-word registers.
+@code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers.
+@code{+cdecp0} (CDE extensions for v8-m architecture with coprocessor 0),
+@code{+cdecp1} (CDE extensions for v8-m architecture with coprocessor 1),
+@code{+cdecp2} (CDE extensions for v8-m architecture with coprocessor 2),
+@code{+cdecp3} (CDE extensions for v8-m architecture with coprocessor 3),
+@code{+cdecp4} (CDE extensions for v8-m architecture with coprocessor 4),
+@code{+cdecp5} (CDE extensions for v8-m architecture with coprocessor 5),
+@code{+cdecp6} (CDE extensions for v8-m architecture with coprocessor 6),
+@code{+cdecp7} (CDE extensions for v8-m architecture with coprocessor 7),
+@code{+nofp}: Disables all FPU instructions.
+@code{+nodsp}: Disables DSP Extension.
+
+For @code{armv8.1-m.main}:
+
+@code{+dsp}: Enables DSP Extension.
+@code{+fp}: Enables single and half precision scalar Floating Point Extensions
+for Armv8.1-M Mainline with 16 double-word registers.
+@code{+fp.dp}: Enables double precision scalar Floating Point Extensions for
+Armv8.1-M Mainline, implies @code{+fp}.
+@code{+mve}: Enables integer only M-profile Vector Extension for
+Armv8.1-M Mainline, implies @code{+dsp}.
+@code{+mve.fp}: Enables Floating Point M-profile Vector Extension for
+Armv8.1-M Mainline, implies @code{+mve} and @code{+fp}.
+@code{+nofp}: Disables all FPU instructions.
+@code{+nodsp}: Disables DSP Extension.
+@code{+nomve}: Disables all M-profile Vector Extensions.
+
+For @code{armv8-a}:
+
+@code{+crc}: Enables CRC32 Extension.
+@code{+simd}: Enables VFP and NEON for Armv8-A.
+@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
+@code{+simd}.
+@code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
+@code{+predres}: Enables Execution and Data Prediction Restriction Instruction
+for Armv8-A.
+@code{+nofp}: Disables all FPU, NEON and Cryptography Extensions.
+@code{+nocrypto}: Disables Cryptography Extensions.
+
+For @code{armv8.1-a}:
+
+@code{+simd}: Enables VFP and NEON for Armv8.1-A.
+@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
+@code{+simd}.
+@code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
+@code{+predres}: Enables Execution and Data Prediction Restriction Instruction
+for Armv8-A.
+@code{+nofp}: Disables all FPU, NEON and Cryptography Extensions.
+@code{+nocrypto}: Disables Cryptography Extensions.
+
+For @code{armv8.2-a} and @code{armv8.3-a}:
+
+@code{+simd}: Enables VFP and NEON for Armv8.1-A.
+@code{+fp16}: Enables FP16 Extension for Armv8.2-A, implies @code{+simd}.
+@code{+fp16fml}: Enables FP16 Floating Point Multiplication Variant Extensions
+for Armv8.2-A, implies @code{+fp16}.
+@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
+@code{+simd}.
+@code{+dotprod}: Enables Dot Product Extensions for Armv8.2-A, implies
+@code{+simd}.
+@code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
+@code{+predres}: Enables Execution and Data Prediction Restriction Instruction
+for Armv8-A.
+@code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
+@code{+nocrypto}: Disables Cryptography Extensions.
+
+For @code{armv8.4-a}:
+
+@code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for
+Armv8.2-A.
+@code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication
+Variant Extensions for Armv8.2-A, implies @code{+simd}.
+@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
+@code{+simd}.
+@code{+sb}: Enables Speculation Barrier Instruction for Armv8-A.
+@code{+predres}: Enables Execution and Data Prediction Restriction Instruction
+for Armv8-A.
+@code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
+@code{+nocryptp}: Disables Cryptography Extensions.
+
+For @code{armv8.5-a}:
+
+@code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for
+Armv8.2-A.
+@code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication
+Variant Extensions for Armv8.2-A, implies @code{+simd}.
+@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies
+@code{+simd}.
+@code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions.
+@code{+nocryptp}: Disables Cryptography Extensions.
+
+
+@cindex @code{-mfpu=} command-line option, ARM
@item -mfpu=@var{floating-point-format}
This option specifies the floating point format to assemble for. The
assembler will issue an error message if an attempt is made to assemble
-an instruction which will not execute on the target floating point unit.
+an instruction which will not execute on the target floating point unit.
The following format options are recognized:
@code{softfpa},
@code{fpe},
@code{vfpv4},
@code{vfpv4-d16},
@code{fpv4-sp-d16},
+@code{fpv5-sp-d16},
+@code{fpv5-d16},
+@code{fp-armv8},
@code{arm1020t},
@code{arm1020e},
@code{arm1136jf-s},
@code{maverick},
@code{neon},
+@code{neon-vfpv3},
+@code{neon-fp16},
+@code{neon-vfpv4},
+@code{neon-fp-armv8},
+@code{crypto-neon-fp-armv8},
+@code{neon-fp-armv8.1}
and
-@code{neon-vfpv4}.
+@code{crypto-neon-fp-armv8.1}.
In addition to determining which instructions are assembled, this option
also affects the way in which the @code{.double} assembler directive behaves
when assembling little-endian code.
-The default is dependent on the processor selected. For Architecture 5 or
-later, the default is to assembler for VFP instructions; for earlier
+The default is dependent on the processor selected. For Architecture 5 or
+later, the default is to assemble for VFP instructions; for earlier
architectures the default is to assemble for FPA instructions.
-@cindex @code{-mthumb} command line option, ARM
+@cindex @code{-mfp16-format=} command-line option
+@item -mfp16-format=@var{format}
+This option specifies the half-precision floating point format to use
+when assembling floating point numbers emitted by the @code{.float16}
+directive.
+The following format options are recognized:
+@code{ieee},
+@code{alternative}.
+If @code{ieee} is specified then the IEEE 754-2008 half-precision floating
+point format is used, if @code{alternative} is specified then the Arm
+alternative half-precision format is used. If this option is set on the
+command line then the format is fixed and cannot be changed with
+the @code{float16_format} directive. If this value is not set then
+the IEEE 754-2008 format is used until the format is explicitly set with
+the @code{float16_format} directive.
+
+@cindex @code{-mthumb} command-line option, ARM
@item -mthumb
This option specifies that the assembler should start assembling Thumb
-instructions; that is, it should behave as though the file starts with a
+instructions; that is, it should behave as though the file starts with a
@code{.code 16} directive.
-@cindex @code{-mthumb-interwork} command line option, ARM
+@cindex @code{-mthumb-interwork} command-line option, ARM
@item -mthumb-interwork
This option specifies that the output generated by the assembler should
-be marked as supporting interworking.
+be marked as supporting interworking. It also affects the behaviour
+of the @code{ADR} and @code{ADRL} pseudo opcodes.
-@cindex @code{-mimplicit-it} command line option, ARM
+@cindex @code{-mimplicit-it} command-line option, ARM
@item -mimplicit-it=never
@itemx -mimplicit-it=always
@itemx -mimplicit-it=arm
code and are accepted in Thumb-2 code. If you omit this option, the
behavior is equivalent to @code{-mimplicit-it=arm}.
-@cindex @code{-mapcs-26} command line option, ARM
-@cindex @code{-mapcs-32} command line option, ARM
+@cindex @code{-mapcs-26} command-line option, ARM
+@cindex @code{-mapcs-32} command-line option, ARM
@item -mapcs-26
@itemx -mapcs-32
These options specify that the output generated by the assembler should
be marked as supporting the indicated version of the Arm Procedure.
Calling Standard.
-@cindex @code{-matpcs} command line option, ARM
+@cindex @code{-matpcs} command-line option, ARM
@item -matpcs
-This option specifies that the output generated by the assembler should
+This option specifies that the output generated by the assembler should
be marked as supporting the Arm/Thumb Procedure Calling Standard. If
enabled this option will cause the assembler to create an empty
debugging section in the object file called .arm.atpcs. Debuggers can
use this to determine the ABI being used by.
-@cindex @code{-mapcs-float} command line option, ARM
+@cindex @code{-mapcs-float} command-line option, ARM
@item -mapcs-float
This indicates the floating point variant of the APCS should be
used. In this variant floating point arguments are passed in FP
registers rather than integer registers.
-@cindex @code{-mapcs-reentrant} command line option, ARM
+@cindex @code{-mapcs-reentrant} command-line option, ARM
@item -mapcs-reentrant
This indicates that the reentrant variant of the APCS should be used.
This variant supports position independent code.
-@cindex @code{-mfloat-abi=} command line option, ARM
+@cindex @code{-mfloat-abi=} command-line option, ARM
@item -mfloat-abi=@var{abi}
This option specifies that the output generated by the assembler should be
marked as using specified floating point ABI.
and
@code{hard}.
-@cindex @code{-eabi=} command line option, ARM
+@cindex @code{-eabi=} command-line option, ARM
@item -meabi=@var{ver}
This option specifies which EABI version the produced object files should
conform to.
and
@code{5}.
-@cindex @code{-EB} command line option, ARM
+@cindex @code{-EB} command-line option, ARM
@item -EB
This option specifies that the output generated by the assembler should
be marked as being encoded for a big-endian processor.
-@cindex @code{-EL} command line option, ARM
+Note: If a program is being built for a system with big-endian data
+and little-endian instructions then it should be assembled with the
+@option{-EB} option, (all of it, code and data) and then linked with
+the @option{--be8} option. This will reverse the endianness of the
+instructions back to little-endian, but leave the data as big-endian.
+
+@cindex @code{-EL} command-line option, ARM
@item -EL
This option specifies that the output generated by the assembler should
be marked as being encoded for a little-endian processor.
-@cindex @code{-k} command line option, ARM
+@cindex @code{-k} command-line option, ARM
@cindex PIC code generation for ARM
@item -k
This option specifies that the output of the assembler should be marked
as position-independent code (PIC).
-@cindex @code{--fix-v4bx} command line option, ARM
+@cindex @code{--fix-v4bx} command-line option, ARM
@item --fix-v4bx
Allow @code{BX} instructions in ARMv4 code. This is intended for use with
the linker option of the same name.
-@cindex @code{-mwarn-deprecated} command line option, ARM
+@cindex @code{-mwarn-deprecated} command-line option, ARM
@item -mwarn-deprecated
@itemx -mno-warn-deprecated
Enable or disable warnings about using deprecated options or
features. The default is to warn.
+@cindex @code{-mccs} command-line option, ARM
+@item -mccs
+Turns on CodeComposer Studio assembly syntax compatibility mode.
+
+@cindex @code{-mwarn-syms} command-line option, ARM
+@item -mwarn-syms
+@itemx -mno-warn-syms
+Enable or disable warnings about symbols that match the names of ARM
+instructions. The default is to warn.
+
@end table
@code{unified} syntax, which can be selected via the @code{.syntax}
directive, and has the following main features:
-@table @bullet
+@itemize @bullet
@item
Immediate operands do not require a @code{#} prefix.
@item
All instructions set the flags if and only if they have an @code{s}
affix.
-@end table
+@end itemize
@node ARM-Chars
@subsection Special Characters
@cindex line comment character, ARM
@cindex ARM line comment character
-The presence of a @samp{@@} on a line indicates the start of a comment
-that extends to the end of the current line. If a @samp{#} appears as
-the first character of a line, the whole line is treated as a comment.
+The presence of a @samp{@@} anywhere on a line indicates the start of
+a comment that extends to the end of that line.
+
+If a @samp{#} appears as the first character of a line then the whole
+line is treated as a comment, but in this case the line could also be
+a logical line number directive (@pxref{Comments}) or a preprocessor
+control command (@pxref{Preprocessing}).
@cindex line separator, ARM
@cindex statement separator, ARM
@cindex register names, ARM
*TODO* Explain about ARM register naming, and the predefined names.
-@node ARM-Neon-Alignment
-@subsection NEON Alignment Specifiers
-
-@cindex alignment for NEON instructions
-Some NEON load/store instructions allow an optional address
-alignment qualifier.
-The ARM documentation specifies that this is indicated by
-@samp{@@ @var{align}}. However GAS already interprets
-the @samp{@@} character as a "line comment" start,
-so @samp{: @var{align}} is used instead. For example:
-
-@smallexample
- vld1.8 @{q0@}, [r0, :128]
-@end smallexample
-
-@node ARM Floating Point
-@section Floating Point
-
-@cindex floating point, ARM (@sc{ieee})
-@cindex ARM floating point (@sc{ieee})
-The ARM family uses @sc{ieee} floating-point numbers.
-
@node ARM-Relocations
@subsection ARM relocation generation
@code{TLSGD},
@code{TLSLDM},
@code{TLSLDO},
+@code{TLSDESC},
+@code{TLSCALL},
@code{GOTTPOFF},
@code{GOT_PREL}
and
@code{TPOFF}.
For compatibility with older toolchains the assembler also accepts
-@code{(PLT)} after branch targets. This will generate the deprecated
-@samp{R_ARM_PLT32} relocation.
+@code{(PLT)} after branch targets. On legacy targets this will
+generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
+targets it will encode either the @samp{R_ARM_CALL} or
+@samp{R_ARM_JUMP24} relocation, as appropriate.
@cindex MOVW and MOVT relocations, ARM
Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
MOVT r0, #:upper16:foo
@end smallexample
+Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
+@samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
+generated by prefixing the value with @samp{#:lower0_7:#},
+@samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
+respectively. For example to load the 32-bit address of foo into r0:
+
+@smallexample
+ MOVS r0, #:upper8_15:#foo
+ LSLS r0, r0, #8
+ ADDS r0, #:upper0_7:#foo
+ LSLS r0, r0, #8
+ ADDS r0, #:lower8_15:#foo
+ LSLS r0, r0, #8
+ ADDS r0, #:lower0_7:#foo
+@end smallexample
+
+@node ARM-Neon-Alignment
+@subsection NEON Alignment Specifiers
+
+@cindex alignment for NEON instructions
+Some NEON load/store instructions allow an optional address
+alignment qualifier.
+The ARM documentation specifies that this is indicated by
+@samp{@@ @var{align}}. However GAS already interprets
+the @samp{@@} character as a "line comment" start,
+so @samp{: @var{align}} is used instead. For example:
+
+@smallexample
+ vld1.8 @{q0@}, [r0, :128]
+@end smallexample
+
+@node ARM Floating Point
+@section Floating Point
+
+@cindex floating point, ARM (@sc{ieee})
+@cindex ARM floating point (@sc{ieee})
+The ARM family uses @sc{ieee} floating-point numbers.
+
@node ARM Directives
@section ARM Machine Directives
@c AAAAAAAAAAAAAAAAAAAAAAAAA
+@ifclear ELF
@cindex @code{.2byte} directive, ARM
@cindex @code{.4byte} directive, ARM
@cindex @code{.8byte} directive, ARM
@itemx .4byte @var{expression} [, @var{expression}]*
@itemx .8byte @var{expression} [, @var{expression}]*
These directives write 2, 4 or 8 byte values to the output section.
+@end ifclear
@cindex @code{.align} directive, ARM
@item .align @var{expression} [, @var{expression}]
@cindex @code{.arch} directive, ARM
@item .arch @var{name}
Select the target architecture. Valid values for @var{name} are the same as
-for the @option{-march} commandline option.
+for the @option{-march} command-line option without the instruction set
+extension.
-Specifying @code{.arch} clears any previously selected architecture
+Specifying @code{.arch} clears any previously selected architecture
extensions.
@cindex @code{.arch_extension} directive, ARM
@item .arch_extension @var{name}
-Add or remove an architecture extension to the target architecture. Valid
-values for @var{name} are the same as those accepted as architectural
-extensions by the @option{-mcpu} commandline option.
+Add or remove an architecture extension to the target architecture. Valid
+values for @var{name} are the same as those accepted as architectural
+extensions by the @option{-mcpu} and @option{-march} command-line options.
@code{.arch_extension} may be used multiple times to add or remove extensions
incrementally to the architecture being compiled for.
@item .arm
This performs the same action as @var{.code 32}.
-@anchor{arm_pad}
-@cindex @code{.pad} directive, ARM
-@item .pad #@var{count}
-Generate unwinder annotations for a stack adjustment of @var{count} bytes.
-A positive value indicates the function prologue allocated stack space by
-decrementing the stack pointer.
-
@c BBBBBBBBBBBBBBBBBBBBBBBBBB
@cindex @code{.bss} directive, ARM
@cindex @code{.cpu} directive, ARM
@item .cpu @var{name}
Select the target processor. Valid values for @var{name} are the same as
-for the @option{-mcpu} commandline option.
+for the @option{-mcpu} command-line option without the instruction set
+extension.
-Specifying @code{.cpu} clears any previously selected architecture
+Specifying @code{.cpu} clears any previously selected architecture
extensions.
@c DDDDDDDDDDDDDDDDDDDDDDDDDD
@code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
@code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
@code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
-@code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
+@code{Tag_Advanced_SIMD_arch}, @code{Tag_MVE_arch}, @code{Tag_PCS_config},
@code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
@code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
@code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
@code{number, "string"} depending on the tag.
Note - the following legacy values are also accepted by @var{tag}:
-@code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
+@code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
@code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
@cindex @code{.even} directive, ARM
@c FFFFFFFFFFFFFFFFFFFFFFFFFF
+@cindex @code{.float16} directive, ARM
+@item .float16 @var{value [,...,value_n]}
+Place the half precision floating point representation of one or more
+floating-point values into the current section. The exact format of the
+encoding is specified by @code{.float16_format}. If the format has not
+been explicitly set yet (either via the @code{.float16_format} directive or
+the command line option) then the IEEE 754-2008 format is used.
+
+@cindex @code{.float16_format} directive, ARM
+@item .float16_format @var{format}
+Set the format to use when encoding float16 values emitted by
+the @code{.float16} directive.
+Once the format has been set it cannot be changed.
+@code{format} should be one of the following: @code{ieee} (encode in
+the IEEE 754-2008 half precision format) or @code{alternative} (encode in
+the Arm alternative half precision format).
+
@anchor{arm_fnend}
@cindex @code{.fnend} directive, ARM
@item .fnend
@cindex @code{.fpu} directive, ARM
@item .fpu @var{name}
Select the floating-point unit to assemble for. Valid values for @var{name}
-are the same as for the @option{-mfpu} commandline option.
+are the same as for the @option{-mfpu} command-line option.
@c GGGGGGGGGGGGGGGGGGGGGGGGGG
@c HHHHHHHHHHHHHHHHHHHHHHHHHH
output section. These are not compatible with current ARM processors
or ABIs.
+@anchor{arm_pad}
@cindex @code{.pad} directive, ARM
@item .pad #@var{count}
Generate unwinder annotations for a stack adjustment of @var{count} bytes.
interworking is not going to be performed. The presence of this
directive also implies @code{.thumb}
-This directive is not neccessary when generating EABI objects. On these
+This directive is not necessary when generating EABI objects. On these
targets the encoding is implicit when generating Thumb code.
@cindex @code{.thumb_set} directive, ARM
the aliased symbol as being a thumb function entry point, in the same
way that the @code{.thumb_func} directive does.
+@cindex @code{.tlsdescseq} directive, ARM
+@item .tlsdescseq @var{tls-variable}
+This directive is used to annotate parts of an inlined TLS descriptor
+trampoline. Normally the trampoline is provided by the linker, and
+this directive is not needed.
+
@c UUUUUUUUUUUUUUUUUUUUUUUUUU
@cindex @code{.unreq} directive, ARM
@cindex @code{.unwind_raw} directive, ARM
@item .unwind_raw @var{offset}, @var{byte1}, @dots{}
-Insert one of more arbitary unwind opcode bytes, which are known to adjust
+Insert one of more arbitrary unwind opcode bytes, which are known to adjust
the stack pointer by @var{offset} bytes.
For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
@cindex opcodes for ARM
@code{@value{AS}} implements all the standard ARM opcodes. It also
implements several pseudo opcodes, including several synthetic load
-instructions.
+instructions.
@table @code
nothing. Currently it will evaluate to MOV r0, r0.
@cindex @code{LDR reg,=<label>} pseudo op, ARM
-@item LDR
+@item LDR
@smallexample
ldr <register> , = <expression>
@end smallexample
the ADR instruction, then an error will be generated. This instruction
will not make use of the literal pool.
+If @var{label} is a thumb function symbol, and thumb interworking has
+been enabled via the @option{-mthumb-interwork} option then the bottom
+bit of the value stored into @var{register} will be set. This allows
+the following sequence to work as expected:
+
+@smallexample
+ adr r0, thumb_function
+ blx r0
+@end smallexample
+
@cindex @code{ADRL reg,<label>} pseudo op, ARM
-@item ADRL
+@item ADRL
@smallexample
adrl <register> <label>
@end smallexample
(and section) as the ADRL instruction, then an error will be generated.
This instruction will not make use of the literal pool.
+If @var{label} is a thumb function symbol, and thumb interworking has
+been enabled via the @option{-mthumb-interwork} option then the bottom
+bit of the value stored into @var{register} will be set.
+
@end table
For information on the ARM or Thumb instruction sets, see @cite{ARM
@verbatim
void callee (int *);
-int
-caller ()
+int
+caller ()
{
int i;
callee (&i);
- return i;
+ return i;
}
@end verbatim
op appears immediately before the first instruction of the function
while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
op appears immediately after the last instruction of the function.
-These pseudo ops specify the range of the function.
+These pseudo ops specify the range of the function.
Only the order of the other pseudos ops (e.g., @code{.setfp} or
@code{.pad}) matters; their exact locations are irrelevant. In the
know more about the object-file format used to represent unwind
information, you may consult the @cite{Exception Handling ABI for the
ARM Architecture} available from @uref{http://infocenter.arm.com}.
+
projects / thirdparty / binutils-gdb.git / blobdiff