Update copyright years.

[thirdparty/gcc.git] / gcc / config / rs6000 / e500mc64.md

diff --git a/gcc/config/rs6000/e500mc64.md b/gcc/config/rs6000/e500mc64.md
index 45823347ab9e6908dacd7aaf89da74f2e87ef5dc..dc79d8b06d1808d40399e1da48d442ac94e6b53e 100644 (file)
--- a/gcc/config/rs6000/e500mc64.md
+++ b/gcc/config/rs6000/e500mc64.md
@@ -1,5 +1,5 @@
 ;; Pipeline description for Freescale PowerPC e500mc64 core.
-;;   Copyright (C) 2009-2014 Free Software Foundation, Inc.
+;;   Copyright (C) 2009-2021 Free Software Foundation, Inc.
 ;;   Contributed by Edmar Wienskoski (edmar@freescale.com)
 ;;
 ;; This file is part of GCC.
@@ -69,8 +69,8 @@
 
 ;; Simple SU insns.
 (define_insn_reservation "e500mc64_su" 1
-  (and (ior (eq_attr "type" "integer,insert,cntlz,exts")
-           (and (eq_attr "type" "add,logical")
+  (and (ior (eq_attr "type" "integer,insert,cntlz")
+           (and (eq_attr "type" "add,logical,exts")
                 (eq_attr "dot" "no"))
            (and (eq_attr "type" "shift")
                 (eq_attr "dot" "no")
@@ -79,8 +79,8 @@
   "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
 
 (define_insn_reservation "e500mc64_su2" 2
-  (and (ior (eq_attr "type" "cmp,compare,trap")
-           (and (eq_attr "type" "add,logical")
+  (and (ior (eq_attr "type" "cmp,trap")
+           (and (eq_attr "type" "add,logical,exts")
                 (eq_attr "dot" "yes"))
            (and (eq_attr "type" "shift")
                 (eq_attr "dot" "yes")
@@ -129,7 +129,7 @@
 
 ;; CR logical.
 (define_insn_reservation "e500mc64_cr_logical" 1
-  (and (eq_attr "type" "cr_logical,delayed_cr")
+  (and (eq_attr "type" "cr_logical")
        (eq_attr "cpu" "ppce500mc64"))
   "e500mc64_decode,e500mc64_bu,e500mc64_retire")
 
@@ -151,12 +151,6 @@
        (eq_attr "cpu" "ppce500mc64"))
   "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
 
-;; Brinc.
-(define_insn_reservation "e500mc64_brinc" 1
-  (and (eq_attr "type" "brinc")
-       (eq_attr "cpu" "ppce500mc64"))
-  "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
-
 ;; Loads.
 (define_insn_reservation "e500mc64_load" 3
   (and (eq_attr "type" "load,load_l,sync")