Update copyright years.

[thirdparty/gcc.git] / gcc / config / rs6000 / mpc.md

diff --git a/gcc/config/rs6000/mpc.md b/gcc/config/rs6000/mpc.md
index 57a6da03efe2e85ec638fe964505887057ab5826..40e9f00ab60468076e1f1054488c09faf0386d1f 100644 (file)
--- a/gcc/config/rs6000/mpc.md
+++ b/gcc/config/rs6000/mpc.md
@@ -1,11 +1,11 @@
 ;; Scheduling description for Motorola PowerPC processor cores.
-;;   Copyright (C) 2003 Free Software Foundation, Inc.
+;;   Copyright (C) 2003-2021 Free Software Foundation, Inc.
 ;;
 ;; This file is part of GCC.
 ;;
 ;; GCC is free software; you can redistribute it and/or modify it
 ;; under the terms of the GNU General Public License as published
-;; by the Free Software Foundation; either version 2, or (at your
+;; by the Free Software Foundation; either version 3, or (at your
 ;; option) any later version.
 ;;
 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
@@ -14,9 +14,8 @@
 ;; License for more details.
 ;;
 ;; You should have received a copy of the GNU General Public License
-;; along with GCC; see the file COPYING.  If not, write to the
-;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
-;; MA 02111-1307, USA.
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
 
 (define_automaton "mpc,mpcfp")
 (define_cpu_unit "iu_mpc,mciu_mpc" "mpc")
@@ -27,38 +26,52 @@
 ;; 505/801/821/823
 
 (define_insn_reservation "mpccore-load" 2
-  (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
+  (and (eq_attr "type" "load,load_l,store_c,sync")
        (eq_attr "cpu" "mpccore"))
   "lsu_mpc")
 
-(define_insn_reservation "mpccore-store" 1
-  (and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
+(define_insn_reservation "mpccore-store" 2
+  (and (eq_attr "type" "store,fpstore")
        (eq_attr "cpu" "mpccore"))
   "lsu_mpc")
 
 (define_insn_reservation "mpccore-fpload" 2
-  (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
+  (and (eq_attr "type" "fpload")
        (eq_attr "cpu" "mpccore"))
   "lsu_mpc")
 
 (define_insn_reservation "mpccore-integer" 1
-  (and (eq_attr "type" "integer")
+  (and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
+           (and (eq_attr "type" "add,logical,shift,exts")
+                (eq_attr "dot" "no")))
        (eq_attr "cpu" "mpccore"))
   "iu_mpc")
 
+(define_insn_reservation "mpccore-two" 1
+  (and (eq_attr "type" "two")
+       (eq_attr "cpu" "mpccore"))
+  "iu_mpc,iu_mpc")
+
+(define_insn_reservation "mpccore-three" 1
+  (and (eq_attr "type" "three")
+       (eq_attr "cpu" "mpccore"))
+  "iu_mpc,iu_mpc,iu_mpc")
+
 (define_insn_reservation "mpccore-imul" 2
-  (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
+  (and (eq_attr "type" "mul")
        (eq_attr "cpu" "mpccore"))
   "mciu_mpc")
 
 ; Divide latency varies greatly from 2-11, use 6 as average
 (define_insn_reservation "mpccore-idiv" 6
-  (and (eq_attr "type" "idiv")
+  (and (eq_attr "type" "div")
        (eq_attr "cpu" "mpccore"))
   "mciu_mpc*6")
 
 (define_insn_reservation "mpccore-compare" 3
-  (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare")
+  (and (ior (eq_attr "type" "cmp")
+           (and (eq_attr "type" "add,logical,shift,exts")
+                (eq_attr "dot" "yes")))
        (eq_attr "cpu" "mpccore"))
   "iu_mpc,nothing,bpu_mpc")
 
@@ -68,7 +81,7 @@
   "fpu_mpc,bpu_mpc")
 
 (define_insn_reservation "mpccore-fp" 4
-  (and (eq_attr "type" "fp")
+  (and (eq_attr "type" "fp,fpsimple")
        (eq_attr "cpu" "mpccore"))
   "fpu_mpc*2")
 
@@ -88,12 +101,12 @@
   "fpu_mpc*17")
 
 (define_insn_reservation "mpccore-mtjmpr" 4
-  (and (eq_attr "type" "mtjmpr")
+  (and (eq_attr "type" "mtjmpr,mfjmpr")
        (eq_attr "cpu" "mpccore"))
   "bpu_mpc")
 
 (define_insn_reservation "mpccore-jmpreg" 1
-  (and (eq_attr "type" "jmpreg,branch,cr_logical,delayed_cr,mfcr,mtcr")
+  (and (eq_attr "type" "jmpreg,branch,cr_logical,mfcr,mtcr,isync")
        (eq_attr "cpu" "mpccore"))
   "bpu_mpc")