gdb/riscv: better support for fflags and frm registers

[thirdparty/binutils-gdb.git] / gdb / features / riscv / 64bit-fpu.xml

diff --git a/gdb/features/riscv/64bit-fpu.xml b/gdb/features/riscv/64bit-fpu.xml
index ff42b4a21fbb294be927336b7c7846730e943688..68f523f0d60278ea0e587af476f017046336b486 100644 (file)
--- a/gdb/features/riscv/64bit-fpu.xml
+++ b/gdb/features/riscv/64bit-fpu.xml
@@ -50,7 +50,5 @@
   <reg name="ft10" bitsize="64" type="riscv_double"/>
   <reg name="ft11" bitsize="64" type="riscv_double"/>
 
-  <reg name="fflags" bitsize="32" type="int" regnum="66"/>
-  <reg name="frm" bitsize="32" type="int" regnum="67"/>
   <reg name="fcsr" bitsize="32" type="int" regnum="68"/>
 </feature>