/* Target-dependent header for the RISC-V architecture, for GDB, the
GNU Debugger.
- Copyright (C) 2018-2021 Free Software Foundation, Inc.
+ Copyright (C) 2018-2024 Free Software Foundation, Inc.
This file is part of GDB.
};
/* RISC-V specific per-architecture information. */
-struct riscv_gdbarch_tdep : gdbarch_tdep
+struct riscv_gdbarch_tdep : gdbarch_tdep_base
{
/* Features about the target hardware that impact how the gdbarch is
configured. Two gdbarch instances are compatible only if this field
/* ISA-specific data types. */
struct type *riscv_fpreg_d_type = nullptr;
+ /* The location of these registers, set to -2 by default so we don't
+ match against -1 which is frequently used to mean "all registers",
+ e.g. in the regcache supply/collect code. */
+ int fflags_regnum = -2;
+ int frm_regnum = -2;
+
/* Use for tracking unknown CSRs in the target description.
UNKNOWN_CSRS_FIRST_REGNUM is the number assigned to the first unknown
CSR. All other unknown CSRs will be assigned sequential numbers after
/* Return the expected next PC assuming FRAME is stopped at a syscall
instruction. */
- CORE_ADDR (*syscall_next_pc) (struct frame_info *frame) = nullptr;
+ CORE_ADDR (*syscall_next_pc) (const frame_info_ptr &frame) = nullptr;
};