Update years in copyright notice for the GDB files.

[thirdparty/binutils-gdb.git] / gdb / testsuite / gdb.xml / tdesc-regs.exp

diff --git a/gdb/testsuite/gdb.xml/tdesc-regs.exp b/gdb/testsuite/gdb.xml/tdesc-regs.exp
index 0922ca383829affe4ae6fbe25078037ed52a3321..7d054e3f2f3d0a60bfcdc7f66b5ef017e4d75a60 100644 (file)
--- a/gdb/testsuite/gdb.xml/tdesc-regs.exp
+++ b/gdb/testsuite/gdb.xml/tdesc-regs.exp
@@ -1,4 +1,4 @@
-# Copyright 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
+# Copyright 2007-2013 Free Software Foundation, Inc.
 
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -25,18 +25,16 @@ gdb_start
 
 set core-regs ""
 set regdir ""
+set architecture ""
 switch -glob -- [istarget] {
-    "*arm-*-*" {
-        set core-regs {arm-core.xml}
-    }
-    "xscale-*-*" {
+    "arm*-*-*" {
         set core-regs {arm-core.xml}
     }
     "*m68k-*-*" {
         set core-regs {m68k-core.xml}
     }
     "mips*-*-*" {
-       set core-regs {mips-cpu.xml mips-cp0.xml mips-fpu.xml}
+       set core-regs {mips-cpu.xml mips-cp0.xml mips-fpu.xml mips-dsp.xml}
     }
     "powerpc*-*-*" {
        set regdir "rs6000/"
@@ -55,6 +53,19 @@ switch -glob -- [istarget] {
        unsupported "register tests"
        return 0
     }
+    "tic6x-*-*" {
+       set core-regs {tic6x-core.xml}
+    }
+    "i?86-*-*" {
+       set architecture "i386"
+       set regdir "i386/"
+        set core-regs {32bit-core.xml 32bit-sse.xml}
+    }
+    "x86_64-*-*" {
+       set architecture "i386:x86-64"
+       set regdir "i386/"
+        set core-regs {64bit-core.xml 64bit-sse.xml}
+    }
 }
 
 # If no core registers were specified, assume this target does not
@@ -89,12 +100,16 @@ proc load_description { file errmsg } {
     global subdir
     global gdb_prompt
     global core-regs
+    global architecture
 
     file delete "$subdir/regs.xml"
     set ifd [open "$srcdir/$subdir/$file" r]
     set ofd [open "$subdir/regs.xml" w]
     while {[gets $ifd line] >= 0} {
        if {[regexp {<xi:include href="core-regs.xml"/>} $line]} {
+           if {! [string equal ${architecture} ""]} {
+               puts $ofd "  <architecture>${architecture}</architecture>"
+           }
            foreach src ${core-regs} {
                puts $ofd "  <xi:include href=\"$src\"/>"
            }
@@ -122,10 +137,15 @@ proc load_description { file errmsg } {
 load_description "extra-regs.xml" ""
 gdb_test "ptype \$extrareg" "type = (int|long|long long)"
 gdb_test "ptype \$uintreg" "type = uint32_t"
-gdb_test "ptype \$vecreg" "type = int8_t \\\[4\\\]"
+gdb_test "ptype \$vecreg" "type = int8_t __attribute__ \\(\\(vector_size\\(4\\)\\)\\)"
 gdb_test "ptype \$unionreg" \
     "type = union {\r\n *v4int8 v4;\r\n *v2int16 v2;\r\n}"
-gdb_test "ptype \$unionreg.v4" "type = int8_t \\\[4\\\]"
+gdb_test "ptype \$unionreg.v4" "type = int8_t __attribute__ \\(\\(vector_size\\(4\\)\\)\\)"
+gdb_test "ptype \$structreg" \
+    "type = struct struct1 {\r\n *v4int8 v4;\r\n *v2int16 v2;\r\n}"
+gdb_test "ptype \$structreg.v4" "type = int8_t __attribute__ \\(\\(vector_size\\(4\\)\\)\\)"
+gdb_test "ptype \$bitfields" \
+    "type = struct struct2 {\r\n *uint64_t f1 : 35;\r\n *uint64_t f2 : 1;\r\n}"
 
 load_description "core-only.xml" ""
 # The extra register from the previous description should be gone.