/* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
- Copyright (C) 2003, 2005, 2006, 2007, 2008, 2009
- Free Software Foundation, Inc.
+ Copyright (C) 2003-2013 Free Software Foundation, Inc.
This file is part of GDB.
#include "xtensa-config.h"
-static int xtensa_debug_level = 0;
+static unsigned int xtensa_debug_level = 0;
#define DEBUGWARN(args...) \
if (xtensa_debug_level > 0) \
#define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
#define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
+/* On TX, hardware can be configured without Exception Option.
+ There is no PS register in this case. Inside XT-GDB, let us treat
+ it as a virtual read-only register always holding the same value. */
+#define TX_PS 0x20
+
/* ABI-independent macros. */
#define ARG_NOF(gdbarch) \
(gdbarch_tdep (gdbarch)->call_abi \
#define PS_WOE (1<<18)
#define PS_EXC (1<<4)
-/* Convert a live A-register number to the corresponding AR-register number. */
+static int
+windowing_enabled (struct gdbarch *gdbarch, unsigned int ps)
+{
+ /* If we know CALL0 ABI is set explicitly, say it is Call0. */
+ if (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only)
+ return 0;
+
+ return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0);
+}
+
+/* Convert a live A-register number to the corresponding AR-register
+ number. */
static int
arreg_number (struct gdbarch *gdbarch, int a_regnum, ULONGEST wb)
{
return (areg > 15) ? -1 : areg;
}
-static inline int
-windowing_enabled (CORE_ADDR ps)
+/* Read Xtensa register directly from the hardware. */
+static unsigned long
+xtensa_read_register (int regnum)
{
- return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0);
+ ULONGEST value;
+
+ regcache_raw_read_unsigned (get_current_regcache (), regnum, &value);
+ return (unsigned long) value;
+}
+
+/* Write Xtensa register directly to the hardware. */
+static void
+xtensa_write_register (int regnum, ULONGEST value)
+{
+ regcache_raw_write_unsigned (get_current_regcache (), regnum, value);
}
/* Return the window size of the previous call to the function from which we
/* REGISTER INFORMATION */
+/* Find register by name. */
+static int
+xtensa_find_register_by_name (struct gdbarch *gdbarch, char *name)
+{
+ int i;
+
+ for (i = 0; i < gdbarch_num_regs (gdbarch)
+ + gdbarch_num_pseudo_regs (gdbarch);
+ i++)
+
+ if (strcasecmp (gdbarch_tdep (gdbarch)->regmap[i].name, name) == 0)
+ return i;
+
+ return -1;
+}
+
/* Returns the name of a register. */
static const char *
xtensa_register_name (struct gdbarch *gdbarch, int regnum)
if (tp == NULL)
{
- char *name = xmalloc (16);
+ char *name = xstrprintf ("int%d", size * 8);
tp = xmalloc (sizeof (struct ctype_cache));
tp->next = tdep->type_entries;
tdep->type_entries = tp;
tp->size = size;
-
- sprintf (name, "int%d", size * 8);
tp->virtual_type
- = arch_integer_type (gdbarch, size * 8, 1, xstrdup (name));
+ = arch_integer_type (gdbarch, size * 8, 1, name);
+ xfree (name);
}
reg->ctype = tp->virtual_type;
/* Read a tie state or mapped registers. Read the masked areas
of the registers and assemble them into a single value. */
-static void
+static enum register_status
xtensa_register_read_masked (struct regcache *regcache,
xtensa_register_t *reg, gdb_byte *buffer)
{
int r = mask->mask[i].reg_num;
if (r >= 0)
{
+ enum register_status status;
ULONGEST val;
- regcache_cooked_read_unsigned (regcache, r, &val);
+
+ status = regcache_cooked_read_unsigned (regcache, r, &val);
+ if (status != REG_VALID)
+ return status;
regval = (unsigned int) val;
}
else
buffer[i] = mem & 0xff;
mem >>= 8;
}
+
+ return REG_VALID;
}
/* Read pseudo registers. */
-static void
+static enum register_status
xtensa_pseudo_register_read (struct gdbarch *gdbarch,
struct regcache *regcache,
int regnum,
&& (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
{
gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
+ enum register_status status;
- regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf);
+ status = regcache_raw_read (regcache,
+ gdbarch_tdep (gdbarch)->wb_regnum,
+ buf);
+ if (status != REG_VALID)
+ return status;
regnum = arreg_number (gdbarch, regnum,
extract_unsigned_integer (buf, 4, byte_order));
}
/* We can always read non-pseudo registers. */
if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
- regcache_raw_read (regcache, regnum, buffer);
-
+ return regcache_raw_read (regcache, regnum, buffer);
/* We have to find out how to deal with priveleged registers.
Let's treat them as pseudo-registers, but we cannot read/write them. */
buffer[1] = (gdb_byte)0;
buffer[2] = (gdb_byte)0;
buffer[3] = (gdb_byte)0;
+ return REG_VALID;
}
/* Pseudo registers. */
else if (regnum >= 0
{
warning (_("cannot read register %s"),
xtensa_register_name (gdbarch, regnum));
- return;
+ return REG_VALID;
}
}
if (flags & xtTargetFlagsUseFetchStore)
{
warning (_("cannot read register"));
- return;
+ return REG_VALID;
}
/* On some targets (esp. simulators), we can always read the reg. */
else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
{
warning (_("cannot read register"));
- return;
+ return REG_VALID;
}
}
/* We can always read mapped registers. */
else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
- {
- xtensa_register_read_masked (regcache, reg, buffer);
- return;
- }
+ return xtensa_register_read_masked (regcache, reg, buffer);
/* Assume that we can read the register. */
- regcache_raw_read (regcache, regnum, buffer);
+ return regcache_raw_read (regcache, regnum, buffer);
}
else
internal_error (__FILE__, __LINE__,
&& (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
{
gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
- unsigned int wb;
regcache_raw_read (regcache,
gdbarch_tdep (gdbarch)->wb_regnum, buf);
static void
xtensa_init_reggroups (void)
{
+ int i;
+ char cpname[] = "cp0";
+
xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP);
xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP);
xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP);
- xtensa_cp[0] = reggroup_new ("cp0", USER_REGGROUP);
- xtensa_cp[1] = reggroup_new ("cp1", USER_REGGROUP);
- xtensa_cp[2] = reggroup_new ("cp2", USER_REGGROUP);
- xtensa_cp[3] = reggroup_new ("cp3", USER_REGGROUP);
- xtensa_cp[4] = reggroup_new ("cp4", USER_REGGROUP);
- xtensa_cp[5] = reggroup_new ("cp5", USER_REGGROUP);
- xtensa_cp[6] = reggroup_new ("cp6", USER_REGGROUP);
- xtensa_cp[7] = reggroup_new ("cp7", USER_REGGROUP);
+ for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
+ {
+ cpname[2] = '0' + i;
+ xtensa_cp[i] = reggroup_new (cpname, USER_REGGROUP);
+ }
}
static void
xtensa_register_group_t rg = reg->group;
int cp_number;
+ if (group == save_reggroup)
+ /* Every single register should be included into the list of registers
+ to be watched for changes while using -data-list-changed-registers. */
+ return 1;
+
/* First, skip registers that are not visible to this target
(unknown and unmapped registers when not using ISS). */
return rg & xtRegisterGroupFloat;
if (group == general_reggroup)
return rg & xtRegisterGroupGeneral;
- if (group == float_reggroup)
- return rg & xtRegisterGroupFloat;
if (group == system_reggroup)
return rg & xtRegisterGroupState;
if (group == vector_reggroup || group == xtensa_vectra_reggroup)
return rg & xtRegisterGroupVectra;
- if (group == save_reggroup || group == restore_reggroup)
+ if (group == restore_reggroup)
return (regnum < gdbarch_num_regs (gdbarch)
&& (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID);
- if ((cp_number = xtensa_coprocessor_register_group (group)) >= 0)
+ cp_number = xtensa_coprocessor_register_group (group);
+ if (cp_number >= 0)
return rg & (xtRegisterGroupCP0 << cp_number);
else
return 1;
struct gdbarch *gdbarch = get_regcache_arch (rc);
int i;
- DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...) \n", regnum);
+ DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...)\n", regnum);
if (regnum == gdbarch_pc_regnum (gdbarch) || regnum == -1)
regcache_raw_supply (rc, gdbarch_pc_regnum (gdbarch), (char *) ®s->pc);
size_t sect_size)
{
DEBUGTRACE ("xtensa_regset_from_core_section "
- "(..., sect_name==\"%s\", sect_size==%x) \n",
+ "(..., sect_name==\"%s\", sect_size==%x)\n",
sect_name, (unsigned int) sect_size);
if (strcmp (sect_name, ".reg") == 0
int callsize; /* Call size of this frame. */
int ws; /* WINDOWSTART of the previous frame. It keeps track of
life windows only. If there is no bit set for the
- window, that means it had been already spilled
+ window, that means it had been already spilled
because of window overflow. */
- /* Spilled A-registers from the previous frame.
- AREGS[i] == -1, if corresponding AR is alive. */
+ /* Addresses of spilled A-registers.
+ AREGS[i] == -1, if corresponding AR is alive. */
CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS];
} xtensa_windowed_frame_cache_t;
/* Call0 ABI Definitions. */
-#define C0_MAXOPDS 3 /* Maximum number of operands for prologue analysis. */
+#define C0_MAXOPDS 3 /* Maximum number of operands for prologue
+ analysis. */
#define C0_NREGS 16 /* Number of A-registers to track. */
#define C0_CLESV 12 /* Callee-saved registers are here and up. */
#define C0_SP 1 /* Register used as SP. */
typedef struct xtensa_c0reg
{
- int fr_reg; /* original register from which register content
- is derived, or C0_CONST, or C0_INEXP. */
- int fr_ofs; /* constant offset from reg, or immediate value. */
- int to_stk; /* offset from original SP to register (4-byte aligned),
- or C0_NOSTK if register has not been saved. */
+ int fr_reg; /* original register from which register content
+ is derived, or C0_CONST, or C0_INEXP. */
+ int fr_ofs; /* constant offset from reg, or immediate value. */
+ int to_stk; /* offset from original SP to register (4-byte aligned),
+ or C0_NOSTK if register has not been saved. */
} xtensa_c0reg_t;
-
/* Frame cache part for Call0 ABI. */
typedef struct xtensa_call0_frame_cache
{
- int c0_frmsz; /* Stack frame size. */
- int c0_hasfp; /* Current frame uses frame pointer. */
- int fp_regnum; /* A-register used as FP. */
- int c0_fp; /* Actual value of frame pointer. */
- xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */
+ int c0_frmsz; /* Stack frame size. */
+ int c0_hasfp; /* Current frame uses frame pointer. */
+ int fp_regnum; /* A-register used as FP. */
+ int c0_fp; /* Actual value of frame pointer. */
+ int c0_fpalign; /* Dinamic adjustment for the stack
+ pointer. It's an AND mask. Zero,
+ if alignment was not adjusted. */
+ int c0_old_sp; /* In case of dynamic adjustment, it is
+ a register holding unaligned sp.
+ C0_INEXP, when undefined. */
+ int c0_sp_ofs; /* If "c0_old_sp" was spilled it's a
+ stack offset. C0_NOSTK otherwise. */
+
+ xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */
} xtensa_call0_frame_cache_t;
typedef struct xtensa_frame_cache
{
CORE_ADDR base; /* Stack pointer of this frame. */
- CORE_ADDR pc; /* PC at the entry point to the function. */
- CORE_ADDR ra; /* The raw return address (without CALLINC). */
- CORE_ADDR ps; /* The PS register of this frame. */
- CORE_ADDR prev_sp; /* Stack Pointer of the previous frame. */
+ CORE_ADDR pc; /* PC of this frame at the function entry point. */
+ CORE_ADDR ra; /* The raw return address of this frame. */
+ CORE_ADDR ps; /* The PS register of the previous (older) frame. */
+ CORE_ADDR prev_sp; /* Stack Pointer of the previous (older) frame. */
int call0; /* It's a call0 framework (else windowed). */
union
{
cache->c0.c0_hasfp = 0;
cache->c0.fp_regnum = -1;
cache->c0.c0_fp = -1;
+ cache->c0.c0_fpalign = 0;
+ cache->c0.c0_old_sp = C0_INEXP;
+ cache->c0.c0_sp_ofs = C0_NOSTK;
for (i = 0; i < C0_NREGS; i++)
{
return frame_id_build (fp + SP_ALIGNMENT, pc);
}
+/* Returns true, if instruction to execute next is unique to Xtensa Window
+ Interrupt Handlers. It can only be one of L32E, S32E, RFWO, or RFWU. */
+
+static int
+xtensa_window_interrupt_insn (struct gdbarch *gdbarch, CORE_ADDR pc)
+{
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
+ unsigned int insn = read_memory_integer (pc, 4, byte_order);
+ unsigned int code;
+
+ if (byte_order == BFD_ENDIAN_BIG)
+ {
+ /* Check, if this is L32E or S32E. */
+ code = insn & 0xf000ff00;
+ if ((code == 0x00009000) || (code == 0x00009400))
+ return 1;
+ /* Check, if this is RFWU or RFWO. */
+ code = insn & 0xffffff00;
+ return ((code == 0x00430000) || (code == 0x00530000));
+ }
+ else
+ {
+ /* Check, if this is L32E or S32E. */
+ code = insn & 0x00ff000f;
+ if ((code == 0x090000) || (code == 0x490000))
+ return 1;
+ /* Check, if this is RFWU or RFWO. */
+ code = insn & 0x00ffffff;
+ return ((code == 0x00003400) || (code == 0x00003500));
+ }
+}
+
/* Returns the best guess about which register is a frame pointer
for the function containing CURRENT_PC. */
-#define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
+#define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
+#define XTENSA_ISA_BADPC ((CORE_ADDR)0) /* Bad PC value. */
static unsigned int
xtensa_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR current_pc)
ba = ia;
bt = (ba + XTENSA_ISA_BSZ) < current_pc
? ba + XTENSA_ISA_BSZ : current_pc;
- read_memory (ba, ibuf, bt - ba);
+ if (target_read_memory (ba, ibuf, bt - ba) != 0)
+ RETURN_FP;
}
xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
unsigned int register_operand;
/* Possible candidate for setting frame pointer
- from A1. This is what we are looking for. */
+ from A1. This is what we are looking for. */
if (xtensa_operand_get_field (isa, opc, 1, ifmt,
is, slot, ®ister_operand) != 0)
®ister_operand) != 0)
RETURN_FP;
- fp_regnum = gdbarch_tdep (gdbarch)->a0_base + register_operand;
+ fp_regnum
+ = gdbarch_tdep (gdbarch)->a0_base + register_operand;
RETURN_FP;
}
}
cache->base = SP (or best guess about FP) of this frame;
cache->pc = entry-PC (entry point of the frame function);
- cache->prev_sp = SP of the previous frame.
-*/
+ cache->prev_sp = SP of the previous frame. */
static void
call0_frame_cache (struct frame_info *this_frame,
- xtensa_frame_cache_t *cache,
- CORE_ADDR pc, CORE_ADDR litbase);
+ xtensa_frame_cache_t *cache, CORE_ADDR pc);
+
+static void
+xtensa_window_interrupt_frame_cache (struct frame_info *this_frame,
+ xtensa_frame_cache_t *cache,
+ CORE_ADDR pc);
static struct xtensa_frame_cache *
xtensa_frame_cache (struct frame_info *this_frame, void **this_cache)
struct gdbarch *gdbarch = get_frame_arch (this_frame);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
unsigned int fp_regnum;
- char op1;
- int windowed;
+ int windowed, ps_regnum;
if (*this_cache)
return *this_cache;
- ps = get_frame_register_unsigned (this_frame, gdbarch_ps_regnum (gdbarch));
- windowed = windowing_enabled (ps);
+ pc = get_frame_register_unsigned (this_frame, gdbarch_pc_regnum (gdbarch));
+ ps_regnum = gdbarch_ps_regnum (gdbarch);
+ ps = (ps_regnum >= 0
+ ? get_frame_register_unsigned (this_frame, ps_regnum) : TX_PS);
+
+ windowed = windowing_enabled (gdbarch, ps);
/* Get pristine xtensa-frame. */
cache = xtensa_alloc_frame_cache (windowed);
*this_cache = cache;
- pc = get_frame_register_unsigned (this_frame, gdbarch_pc_regnum (gdbarch));
-
if (windowed)
{
+ char op1;
+
/* Get WINDOWBASE, WINDOWSTART, and PS registers. */
wb = get_frame_register_unsigned (this_frame,
gdbarch_tdep (gdbarch)->wb_regnum);
just about to execute ENTRY. SP hasn't been set yet.
We can assume any frame size, because it does not
matter, and, let's fake frame base in cache. */
- cache->base = cache->prev_sp + 16;
+ cache->base = cache->prev_sp - 16;
cache->pc = pc;
cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff);
(gdbarch, gdbarch_tdep (gdbarch)->a0_base + 1,
cache->wd.wb);
- cache->prev_sp = get_frame_register_unsigned (this_frame, regnum);
+ cache->prev_sp = xtensa_read_register (regnum);
}
}
}
- else /* Call0 framework. */
+ else if (xtensa_window_interrupt_insn (gdbarch, pc))
{
- unsigned int litbase_regnum = gdbarch_tdep (gdbarch)->litbase_regnum;
- CORE_ADDR litbase = (litbase_regnum == -1)
- ? 0 : get_frame_register_unsigned (this_frame, litbase_regnum);
+ /* Execution stopped inside Xtensa Window Interrupt Handler. */
- call0_frame_cache (this_frame, cache, pc, litbase);
+ xtensa_window_interrupt_frame_cache (this_frame, cache, pc);
+ /* Everything was set already, including cache->base. */
+ return cache;
+ }
+ else /* Call0 framework. */
+ {
+ call0_frame_cache (this_frame, cache, pc);
fp_regnum = cache->c0.fp_regnum;
}
return cache;
}
+static int xtensa_session_once_reported = 1;
+
+/* Report a problem with prologue analysis while doing backtracing.
+ But, do it only once to avoid annoyng repeated messages. */
+
+static void
+warning_once (void)
+{
+ if (xtensa_session_once_reported == 0)
+ warning (_("\
+\nUnrecognised function prologue. Stack trace cannot be resolved. \
+This message will not be repeated in this session.\n"));
+
+ xtensa_session_once_reported = 1;
+}
+
+
static void
xtensa_frame_this_id (struct frame_info *this_frame,
void **this_cache,
spe = cache->c0.c0_fp
- cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs;
- return frame_unwind_got_memory (this_frame, regnum, spe + stkofs);
+ return frame_unwind_got_memory (this_frame, regnum,
+ spe + stkofs);
}
}
}
xtensa_unwind =
{
NORMAL_FRAME,
+ default_frame_unwind_stop_reason,
xtensa_frame_this_id,
xtensa_frame_prev_register,
NULL,
/* On Xtensa, we can return up to 4 words (or 2 for call12). */
if (len > (callsize > 8 ? 8 : 16))
internal_error (__FILE__, __LINE__,
- _("cannot extract return value of %d bytes long"), len);
+ _("cannot extract return value of %d bytes long"),
+ len);
/* Get the register offset of the return
register (A2) in the caller window. */
static enum return_value_convention
xtensa_return_value (struct gdbarch *gdbarch,
- struct type *func_type,
+ struct value *function,
struct type *valtype,
struct regcache *regcache,
gdb_byte *readbuf,
int align; /* alignment */
union
{
- int offset; /* stack offset if on stack */
- int regno; /* regno if in register */
+ int offset; /* stack offset if on stack. */
+ int regno; /* regno if in register. */
} u;
};
{
struct value *arg = args[i];
struct type *arg_type = check_typedef (value_type (arg));
- fprintf_unfiltered (gdb_stdlog, "%2d: 0x%lx %3d ",
- i, (unsigned long) arg, TYPE_LENGTH (arg_type));
+ fprintf_unfiltered (gdb_stdlog, "%2d: %s %3d ", i,
+ host_address_to_string (arg),
+ TYPE_LENGTH (arg_type));
switch (TYPE_CODE (arg_type))
{
case TYPE_CODE_INT:
fprintf_unfiltered (gdb_stdlog, "%3d", TYPE_CODE (arg_type));
break;
}
- fprintf_unfiltered (gdb_stdlog, " 0x%lx\n",
- (unsigned long) value_contents (arg));
+ fprintf_unfiltered (gdb_stdlog, " %s\n",
+ host_address_to_string (value_contents (arg)));
}
}
if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
{
+ ULONGEST val;
+
ra = (bp_addr & 0x3fffffff) | 0x40000000;
- regcache_raw_read (regcache, gdbarch_ps_regnum (gdbarch), buf);
- ps = extract_unsigned_integer (buf, 4, byte_order) & ~0x00030000;
+ regcache_raw_read_unsigned (regcache, gdbarch_ps_regnum (gdbarch), &val);
+ ps = (unsigned long) val & ~0x00030000;
regcache_cooked_write_unsigned
(regcache, gdbarch_tdep (gdbarch)->a0_base + 4, ra);
regcache_cooked_write_unsigned (regcache,
/* Call0 ABI support routines. */
+/* Return true, if PC points to "ret" or "ret.n". */
+
+static int
+call0_ret (CORE_ADDR start_pc, CORE_ADDR finish_pc)
+{
+#define RETURN_RET goto done
+ xtensa_isa isa;
+ xtensa_insnbuf ins, slot;
+ char ibuf[XTENSA_ISA_BSZ];
+ CORE_ADDR ia, bt, ba;
+ xtensa_format ifmt;
+ int ilen, islots, is;
+ xtensa_opcode opc;
+ const char *opcname;
+ int found_ret = 0;
+
+ isa = xtensa_default_isa;
+ gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
+ ins = xtensa_insnbuf_alloc (isa);
+ slot = xtensa_insnbuf_alloc (isa);
+ ba = 0;
+
+ for (ia = start_pc, bt = ia; ia < finish_pc ; ia += ilen)
+ {
+ if (ia + xtensa_isa_maxlength (isa) > bt)
+ {
+ ba = ia;
+ bt = (ba + XTENSA_ISA_BSZ) < finish_pc
+ ? ba + XTENSA_ISA_BSZ : finish_pc;
+ if (target_read_memory (ba, ibuf, bt - ba) != 0 )
+ RETURN_RET;
+ }
+
+ xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
+ ifmt = xtensa_format_decode (isa, ins);
+ if (ifmt == XTENSA_UNDEFINED)
+ RETURN_RET;
+ ilen = xtensa_format_length (isa, ifmt);
+ if (ilen == XTENSA_UNDEFINED)
+ RETURN_RET;
+ islots = xtensa_format_num_slots (isa, ifmt);
+ if (islots == XTENSA_UNDEFINED)
+ RETURN_RET;
+
+ for (is = 0; is < islots; ++is)
+ {
+ if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
+ RETURN_RET;
+
+ opc = xtensa_opcode_decode (isa, ifmt, is, slot);
+ if (opc == XTENSA_UNDEFINED)
+ RETURN_RET;
+
+ opcname = xtensa_opcode_name (isa, opc);
+
+ if ((strcasecmp (opcname, "ret.n") == 0)
+ || (strcasecmp (opcname, "ret") == 0))
+ {
+ found_ret = 1;
+ RETURN_RET;
+ }
+ }
+ }
+ done:
+ xtensa_insnbuf_free(isa, slot);
+ xtensa_insnbuf_free(isa, ins);
+ return found_ret;
+}
+
/* Call0 opcode class. Opcodes are preclassified according to what they
mean for Call0 prologue analysis, and their number of significant operands.
The purpose of this is to simplify prologue analysis by separating
instruction decoding (libisa) from the semantics of prologue analysis. */
-typedef enum {
+typedef enum
+{
c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */
c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */
c0opc_flow, /* Flow control insn. */
c0opc_break, /* Debugger software breakpoints. */
c0opc_add, /* Adding two registers. */
c0opc_addi, /* Adding a register and an immediate. */
+ c0opc_and, /* Bitwise "and"-ing two registers. */
c0opc_sub, /* Subtracting a register from a register. */
c0opc_mov, /* Moving a register to a register. */
c0opc_movi, /* Moving an immediate to a register. */
c0opc_l32r, /* Loading a literal. */
c0opc_s32i, /* Storing word at fixed offset from a base register. */
+ c0opc_rwxsr, /* RSR, WRS, or XSR instructions. */
+ c0opc_l32e, /* L32E instruction. */
+ c0opc_s32e, /* S32E instruction. */
+ c0opc_rfwo, /* RFWO instruction. */
+ c0opc_rfwu, /* RFWU instruction. */
c0opc_NrOf /* Number of opcode classifications. */
} xtensa_insn_kind;
+/* Return true, if OPCNAME is RSR, WRS, or XSR instruction. */
+
+static int
+rwx_special_register (const char *opcname)
+{
+ char ch = *opcname++;
+
+ if ((ch != 'r') && (ch != 'w') && (ch != 'x'))
+ return 0;
+ if (*opcname++ != 's')
+ return 0;
+ if (*opcname++ != 'r')
+ return 0;
+ if (*opcname++ != '.')
+ return 0;
+
+ return 1;
+}
/* Classify an opcode based on what it means for Call0 prologue analysis. */
opclass = c0opc_break;
else if (strcasecmp (opcname, "entry") == 0)
opclass = c0opc_entry;
+ else if (strcasecmp (opcname, "rfwo") == 0)
+ opclass = c0opc_rfwo;
+ else if (strcasecmp (opcname, "rfwu") == 0)
+ opclass = c0opc_rfwu;
else if (xtensa_opcode_is_branch (isa, opc) > 0
|| xtensa_opcode_is_jump (isa, opc) > 0
|| xtensa_opcode_is_loop (isa, opc) > 0
else if (strcasecmp (opcname, "add") == 0
|| strcasecmp (opcname, "add.n") == 0)
opclass = c0opc_add;
+ else if (strcasecmp (opcname, "and") == 0)
+ opclass = c0opc_and;
else if (strcasecmp (opcname, "addi") == 0
|| strcasecmp (opcname, "addi.n") == 0
|| strcasecmp (opcname, "addmi") == 0)
else if (strcasecmp (opcname, "s32i") == 0
|| strcasecmp (opcname, "s32i.n") == 0)
opclass = c0opc_s32i;
+ else if (strcasecmp (opcname, "l32e") == 0)
+ opclass = c0opc_l32e;
+ else if (strcasecmp (opcname, "s32e") == 0)
+ opclass = c0opc_s32e;
+ else if (rwx_special_register (opcname))
+ opclass = c0opc_rwxsr;
return opclass;
}
be within a bundle. Updates the destination register tracking info
accordingly. The pc is needed only for pc-relative load instructions
(eg. l32r). The SP register number is needed to identify stores to
- the stack frame. */
+ the stack frame. Returns 0, if analysis was succesfull, non-zero
+ otherwise. */
-static void
-call0_track_op (struct gdbarch *gdbarch,
- xtensa_c0reg_t dst[], xtensa_c0reg_t src[],
+static int
+call0_track_op (struct gdbarch *gdbarch, xtensa_c0reg_t dst[], xtensa_c0reg_t src[],
xtensa_insn_kind opclass, int nods, unsigned odv[],
- CORE_ADDR pc, CORE_ADDR litbase, int spreg)
+ CORE_ADDR pc, int spreg, xtensa_frame_cache_t *cache)
{
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
- unsigned litaddr, litval;
+ unsigned litbase, litaddr, litval;
switch (opclass)
{
break;
case c0opc_add:
/* 3 operands: dst, src1, src2. */
- gdb_assert (nods == 3);
+ gdb_assert (nods == 3);
if (src[odv[1]].fr_reg == C0_CONST)
{
dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
}
else dst[odv[0]].fr_reg = C0_INEXP;
break;
+ case c0opc_and:
+ /* 3 operands: dst, src1, src2. */
+ gdb_assert (nods == 3);
+ if (cache->c0.c0_fpalign == 0)
+ {
+ /* Handle dynamic stack alignment. */
+ if ((src[odv[0]].fr_reg == spreg) && (src[odv[1]].fr_reg == spreg))
+ {
+ if (src[odv[2]].fr_reg == C0_CONST)
+ cache->c0.c0_fpalign = src[odv[2]].fr_ofs;
+ break;
+ }
+ else if ((src[odv[0]].fr_reg == spreg)
+ && (src[odv[2]].fr_reg == spreg))
+ {
+ if (src[odv[1]].fr_reg == C0_CONST)
+ cache->c0.c0_fpalign = src[odv[1]].fr_ofs;
+ break;
+ }
+ /* else fall through. */
+ }
+ if (src[odv[1]].fr_reg == C0_CONST)
+ {
+ dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
+ dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs & src[odv[1]].fr_ofs;
+ }
+ else if (src[odv[2]].fr_reg == C0_CONST)
+ {
+ dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
+ dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs & src[odv[2]].fr_ofs;
+ }
+ else dst[odv[0]].fr_reg = C0_INEXP;
+ break;
case c0opc_sub:
/* 3 operands: dst, src1, src2. */
gdb_assert (nods == 3);
case c0opc_mov:
/* 2 operands: dst, src [, src]. */
gdb_assert (nods == 2);
+ /* First, check if it's a special case of saving unaligned SP
+ to a spare register in case of dynamic stack adjustment.
+ But, only do it one time. The second time could be initializing
+ frame pointer. We don't want to overwrite the first one. */
+ if ((odv[1] == spreg) && (cache->c0.c0_old_sp == C0_INEXP))
+ cache->c0.c0_old_sp = odv[0];
+
dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs;
break;
case c0opc_l32r:
/* 2 operands: dst, literal offset. */
gdb_assert (nods == 2);
+ /* litbase = xtensa_get_litbase (pc); can be also used. */
+ litbase = (gdbarch_tdep (gdbarch)->litbase_regnum == -1)
+ ? 0 : xtensa_read_register
+ (gdbarch_tdep (gdbarch)->litbase_regnum);
litaddr = litbase & 1
? (litbase & ~1) + (signed)odv[1]
: (pc + 3 + (signed)odv[1]) & ~3;
case c0opc_s32i:
/* 3 operands: value, base, offset. */
gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS);
+ /* First, check if it's a spill for saved unaligned SP,
+ when dynamic stack adjustment was applied to this frame. */
+ if ((cache->c0.c0_fpalign != 0) /* Dynamic stack adjustment. */
+ && (odv[1] == spreg) /* SP usage indicates spill. */
+ && (odv[0] == cache->c0.c0_old_sp)) /* Old SP register spilled. */
+ cache->c0.c0_sp_ofs = odv[2];
+
if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */
&& (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */
&& src[odv[0]].fr_reg >= 0 /* Value is from a register. */
dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2];
}
break;
+ /* If we end up inside Window Overflow / Underflow interrupt handler
+ report an error because these handlers should have been handled
+ already in a different way. */
+ case c0opc_l32e:
+ case c0opc_s32e:
+ case c0opc_rfwo:
+ case c0opc_rfwu:
+ return 1;
default:
- gdb_assert (0);
+ return 1;
}
+ return 0;
}
-/* Analyze prologue of the function at start address to determine if it uses
+/* Analyze prologue of the function at start address to determine if it uses
the Call0 ABI, and if so track register moves and linear modifications
- in the prologue up to the PC or just beyond the prologue, whichever is first.
- An 'entry' instruction indicates non-Call0 ABI and the end of the prologue.
- The prologue may overlap non-prologue instructions but is guaranteed to end
- by the first flow-control instruction (jump, branch, call or return).
- Since an optimized function may move information around and change the
- stack frame arbitrarily during the prologue, the information is guaranteed
- valid only at the point in the function indicated by the PC.
+ in the prologue up to the PC or just beyond the prologue, whichever is
+ first. An 'entry' instruction indicates non-Call0 ABI and the end of the
+ prologue. The prologue may overlap non-prologue instructions but is
+ guaranteed to end by the first flow-control instruction (jump, branch,
+ call or return). Since an optimized function may move information around
+ and change the stack frame arbitrarily during the prologue, the information
+ is guaranteed valid only at the point in the function indicated by the PC.
May be used to skip the prologue or identify the ABI, w/o tracking.
Returns: Address of first instruction after prologue, or PC (whichever
pc Program counter to stop at. Use 0 to continue to end of prologue.
If 0, avoids infinite run-on in corrupt code memory by bounding
the scan to the end of the function if that can be determined.
- nregs Number of general registers to track (size of rt[] array).
+ nregs Number of general registers to track.
InOut args:
- rt[] Array[nregs] of xtensa_c0reg structures for register tracking info.
- If NULL, registers are not tracked.
- Output args:
- call0 If != NULL, *call0 is set non-zero if Call0 ABI used, else 0
- (more accurately, non-zero until 'entry' insn is encountered).
+ cache Xtensa frame cache.
Note that these may produce useful results even if decoding fails
because they begin with default assumptions that analysis may change. */
static CORE_ADDR
call0_analyze_prologue (struct gdbarch *gdbarch,
- CORE_ADDR start, CORE_ADDR pc, CORE_ADDR litbase,
- int nregs, xtensa_c0reg_t rt[], int *call0)
+ CORE_ADDR start, CORE_ADDR pc,
+ int nregs, xtensa_frame_cache_t *cache)
{
CORE_ADDR ia; /* Current insn address in prologue. */
CORE_ADDR ba = 0; /* Current address at base of insn buffer. */
Assume we may be in the prologue until we hit a flow control instr. */
rtmp = NULL;
- body_pc = INT_MAX;
+ body_pc = UINT_MAX;
end_pc = 0;
/* Find out, if we have an information about the prologue from DWARF. */
else
body_pc = min (pc, body_pc);
- if (call0 != NULL)
- *call0 = 1;
-
- if (rt != NULL)
- {
- rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t));
- /* rt is already initialized in xtensa_alloc_frame_cache(). */
- }
- else nregs = 0;
+ cache->call0 = 1;
+ rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t));
if (!xtensa_default_isa)
xtensa_default_isa = xtensa_isa_init (0, 0);
{
ba = ia;
bt = (ba + XTENSA_ISA_BSZ) < body_pc ? ba + XTENSA_ISA_BSZ : body_pc;
- read_memory (ba, ibuf, bt - ba);
+ if (target_read_memory (ba, ibuf, bt - ba) != 0 )
+ error (_("Unable to read target memory ..."));
}
/* Decode format information. */
register changes do not take effect within this bundle. */
for (j = 0; j < nregs; ++j)
- rtmp[j] = rt[j];
+ rtmp[j] = cache->c0.c0_rt[j];
for (is = 0; is < islots; ++is)
{
case c0opc_uninteresting:
continue;
- case c0opc_flow:
+ case c0opc_flow: /* Flow control instructions stop analysis. */
+ case c0opc_rwxsr: /* RSR, WSR, XSR instructions stop analysis. */
goto done;
case c0opc_entry:
- if (call0 != NULL)
- *call0 = 0;
+ cache->call0 = 0;
ia += ilen; /* Skip over 'entry' insn. */
goto done;
default:
- if (call0 != NULL)
- *call0 = 1;
+ cache->call0 = 1;
}
/* Only expected opcodes should get this far. */
- if (rt == NULL)
- continue;
/* Extract and decode the operands. */
nods = xtensa_opcode_num_operands (isa, opc);
if (opclass == c0opc_mov && nods == 3)
{
if (odv[2] == odv[1])
- nods = 2;
+ {
+ nods = 2;
+ if ((odv[0] == 1) && (odv[1] != 1))
+ /* OR A1, An, An , where n != 1.
+ This means we are inside epilogue already. */
+ goto done;
+ }
else
{
opclass = c0opc_uninteresting;
}
/* Track register movement and modification for this operation. */
- call0_track_op (gdbarch, rt, rtmp, opclass,
- nods, odv, ia, litbase, 1);
+ fail = call0_track_op (gdbarch, cache->c0.c0_rt, rtmp,
+ opclass, nods, odv, ia, 1, cache);
+ if (fail)
+ goto done;
}
}
done:
(unsigned)ia, fail ? "failed" : "succeeded");
xtensa_insnbuf_free(isa, slot);
xtensa_insnbuf_free(isa, ins);
- return fail ? 0 : ia;
+ return fail ? XTENSA_ISA_BADPC : ia;
}
/* Initialize frame cache for the current frame in CALL0 ABI. */
static void
call0_frame_cache (struct frame_info *this_frame,
- xtensa_frame_cache_t *cache, CORE_ADDR pc, CORE_ADDR litbase)
+ xtensa_frame_cache_t *cache, CORE_ADDR pc)
{
struct gdbarch *gdbarch = get_frame_arch (this_frame);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
CORE_ADDR start_pc; /* The beginning of the function. */
CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */
CORE_ADDR sp, fp, ra;
- int fp_regnum, c0_hasfp, c0_frmsz, prev_sp, to_stk;
+ int fp_regnum = C0_SP, c0_hasfp = 0, c0_frmsz = 0, prev_sp = 0, to_stk;
+ sp = get_frame_register_unsigned
+ (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
+ fp = sp; /* Assume FP == SP until proven otherwise. */
+
/* Find the beginning of the prologue of the function containing the PC
and analyze it up to the PC or the end of the prologue. */
if (find_pc_partial_function (pc, NULL, &start_pc, NULL))
{
- body_pc = call0_analyze_prologue (gdbarch, start_pc, pc, litbase,
- C0_NREGS,
- &cache->c0.c0_rt[0],
- &cache->call0);
+ body_pc = call0_analyze_prologue (gdbarch, start_pc, pc, C0_NREGS, cache);
+
+ if (body_pc == XTENSA_ISA_BADPC)
+ {
+ warning_once ();
+ ra = 0;
+ goto finish_frame_analysis;
+ }
}
- sp = get_frame_register_unsigned
- (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
- fp = sp; /* Assume FP == SP until proven otherwise. */
-
/* Get the frame information and FP (if used) at the current PC.
If PC is in the prologue, the prologue analysis is more reliable
- than DWARF info. We don't not know for sure if PC is in the prologue,
- but we know no calls have yet taken place, so we can almost
+ than DWARF info. We don't not know for sure, if PC is in the prologue,
+ but we do know no calls have yet taken place, so we can almost
certainly rely on the prologue analysis. */
if (body_pc <= pc)
start_pc = pc;
}
- prev_sp = fp + c0_frmsz;
+ if (cache->c0.c0_fpalign)
+ {
+ /* This frame has a special prologue with a dynamic stack adjustment
+ to force an alignment, which is bigger than standard 16 bytes. */
+
+ CORE_ADDR unaligned_sp;
+
+ if (cache->c0.c0_old_sp == C0_INEXP)
+ /* This can't be. Prologue code should be consistent.
+ Unaligned stack pointer should be saved in a spare register. */
+ {
+ warning_once ();
+ ra = 0;
+ goto finish_frame_analysis;
+ }
+
+ if (cache->c0.c0_sp_ofs == C0_NOSTK)
+ /* Saved unaligned value of SP is kept in a register. */
+ unaligned_sp = get_frame_register_unsigned
+ (this_frame, gdbarch_tdep (gdbarch)->a0_base + cache->c0.c0_old_sp);
+ else
+ /* Get the value from stack. */
+ unaligned_sp = (CORE_ADDR)
+ read_memory_integer (fp + cache->c0.c0_sp_ofs, 4, byte_order);
+
+ prev_sp = unaligned_sp + c0_frmsz;
+ }
+ else
+ prev_sp = fp + c0_frmsz;
/* Frame size from debug info or prologue tracking does not account for
alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
{
fp = get_frame_register_unsigned (this_frame, fp_regnum);
- /* Recalculate previous SP. */
- prev_sp = fp + c0_frmsz;
/* Update the stack frame size. */
c0_frmsz += fp - sp;
}
&& cache->c0.c0_rt[C0_RA].fr_ofs == 0)
{
/* Special case for terminating backtrace at a function that wants to
- be seen as the outermost. Such a function will clear it's RA (A0)
+ be seen as the outermost one. Such a function will clear it's RA (A0)
register to 0 in the prologue instead of saving its original value. */
ra = 0;
}
too bad. */
int i;
- for (i = 0;
- (i < C0_NREGS) &&
- (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA);
+ for (i = 0;
+ (i < C0_NREGS)
+ && (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA);
++i);
if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA)
i = C0_RA;
else ra = 0;
}
+ finish_frame_analysis:
cache->pc = start_pc;
cache->ra = ra;
/* RA == 0 marks the outermost frame. Do not go past it. */
cache->c0.c0_fp = fp;
}
+static CORE_ADDR a0_saved;
+static CORE_ADDR a7_saved;
+static CORE_ADDR a11_saved;
+static int a0_was_saved;
+static int a7_was_saved;
+static int a11_was_saved;
+
+/* Simulate L32E instruction: AT <-- ref (AS + offset). */
+static void
+execute_l32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
+{
+ int atreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + at, wb);
+ int asreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + as, wb);
+ CORE_ADDR addr = xtensa_read_register (asreg) + offset;
+ unsigned int spilled_value
+ = read_memory_unsigned_integer (addr, 4, gdbarch_byte_order (gdbarch));
+
+ if ((at == 0) && !a0_was_saved)
+ {
+ a0_saved = xtensa_read_register (atreg);
+ a0_was_saved = 1;
+ }
+ else if ((at == 7) && !a7_was_saved)
+ {
+ a7_saved = xtensa_read_register (atreg);
+ a7_was_saved = 1;
+ }
+ else if ((at == 11) && !a11_was_saved)
+ {
+ a11_saved = xtensa_read_register (atreg);
+ a11_was_saved = 1;
+ }
+
+ xtensa_write_register (atreg, spilled_value);
+}
+
+/* Simulate S32E instruction: AT --> ref (AS + offset). */
+static void
+execute_s32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
+{
+ int atreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + at, wb);
+ int asreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + as, wb);
+ CORE_ADDR addr = xtensa_read_register (asreg) + offset;
+ ULONGEST spilled_value = xtensa_read_register (atreg);
+
+ write_memory_unsigned_integer (addr, 4,
+ gdbarch_byte_order (gdbarch),
+ spilled_value);
+}
+
+#define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN 200
+
+typedef enum
+{
+ xtWindowOverflow,
+ xtWindowUnderflow,
+ xtNoExceptionHandler
+} xtensa_exception_handler_t;
+
+/* Execute instruction stream from current PC until hitting RFWU or RFWO.
+ Return type of Xtensa Window Interrupt Handler on success. */
+static xtensa_exception_handler_t
+execute_code (struct gdbarch *gdbarch, CORE_ADDR current_pc, CORE_ADDR wb)
+{
+ xtensa_isa isa;
+ xtensa_insnbuf ins, slot;
+ char ibuf[XTENSA_ISA_BSZ];
+ CORE_ADDR ia, bt, ba;
+ xtensa_format ifmt;
+ int ilen, islots, is;
+ xtensa_opcode opc;
+ int insn_num = 0;
+ int fail = 0;
+ void (*func) (struct gdbarch *, int, int, int, CORE_ADDR);
+
+ int at, as, offset;
+
+ /* WindowUnderflow12 = true, when inside _WindowUnderflow12. */
+ int WindowUnderflow12 = (current_pc & 0x1ff) >= 0x140;
+
+ isa = xtensa_default_isa;
+ gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
+ ins = xtensa_insnbuf_alloc (isa);
+ slot = xtensa_insnbuf_alloc (isa);
+ ba = 0;
+ ia = current_pc;
+ bt = ia;
+
+ a0_was_saved = 0;
+ a7_was_saved = 0;
+ a11_was_saved = 0;
+
+ while (insn_num++ < XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN)
+ {
+ if (ia + xtensa_isa_maxlength (isa) > bt)
+ {
+ ba = ia;
+ bt = (ba + XTENSA_ISA_BSZ);
+ if (target_read_memory (ba, ibuf, bt - ba) != 0)
+ return xtNoExceptionHandler;
+ }
+ xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
+ ifmt = xtensa_format_decode (isa, ins);
+ if (ifmt == XTENSA_UNDEFINED)
+ return xtNoExceptionHandler;
+ ilen = xtensa_format_length (isa, ifmt);
+ if (ilen == XTENSA_UNDEFINED)
+ return xtNoExceptionHandler;
+ islots = xtensa_format_num_slots (isa, ifmt);
+ if (islots == XTENSA_UNDEFINED)
+ return xtNoExceptionHandler;
+ for (is = 0; is < islots; ++is)
+ {
+ if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
+ return xtNoExceptionHandler;
+ opc = xtensa_opcode_decode (isa, ifmt, is, slot);
+ if (opc == XTENSA_UNDEFINED)
+ return xtNoExceptionHandler;
+ switch (call0_classify_opcode (isa, opc))
+ {
+ case c0opc_illegal:
+ case c0opc_flow:
+ case c0opc_entry:
+ case c0opc_break:
+ /* We expect none of them here. */
+ return xtNoExceptionHandler;
+ case c0opc_l32e:
+ func = execute_l32e;
+ break;
+ case c0opc_s32e:
+ func = execute_s32e;
+ break;
+ case c0opc_rfwo: /* RFWO. */
+ /* Here, we return from WindowOverflow handler and,
+ if we stopped at the very beginning, which means
+ A0 was saved, we have to restore it now. */
+ if (a0_was_saved)
+ {
+ int arreg = arreg_number (gdbarch,
+ gdbarch_tdep (gdbarch)->a0_base,
+ wb);
+ xtensa_write_register (arreg, a0_saved);
+ }
+ return xtWindowOverflow;
+ case c0opc_rfwu: /* RFWU. */
+ /* Here, we return from WindowUnderflow handler.
+ Let's see if either A7 or A11 has to be restored. */
+ if (WindowUnderflow12)
+ {
+ if (a11_was_saved)
+ {
+ int arreg = arreg_number (gdbarch,
+ gdbarch_tdep (gdbarch)->a0_base + 11,
+ wb);
+ xtensa_write_register (arreg, a11_saved);
+ }
+ }
+ else if (a7_was_saved)
+ {
+ int arreg = arreg_number (gdbarch,
+ gdbarch_tdep (gdbarch)->a0_base + 7,
+ wb);
+ xtensa_write_register (arreg, a7_saved);
+ }
+ return xtWindowUnderflow;
+ default: /* Simply skip this insns. */
+ continue;
+ }
+
+ /* Decode arguments for L32E / S32E and simulate their execution. */
+ if ( xtensa_opcode_num_operands (isa, opc) != 3 )
+ return xtNoExceptionHandler;
+ if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot, &at))
+ return xtNoExceptionHandler;
+ if (xtensa_operand_decode (isa, opc, 0, &at))
+ return xtNoExceptionHandler;
+ if (xtensa_operand_get_field (isa, opc, 1, ifmt, is, slot, &as))
+ return xtNoExceptionHandler;
+ if (xtensa_operand_decode (isa, opc, 1, &as))
+ return xtNoExceptionHandler;
+ if (xtensa_operand_get_field (isa, opc, 2, ifmt, is, slot, &offset))
+ return xtNoExceptionHandler;
+ if (xtensa_operand_decode (isa, opc, 2, &offset))
+ return xtNoExceptionHandler;
+
+ (*func) (gdbarch, at, as, offset, wb);
+ }
+
+ ia += ilen;
+ }
+ return xtNoExceptionHandler;
+}
+
+/* Handle Window Overflow / Underflow exception frames. */
+
+static void
+xtensa_window_interrupt_frame_cache (struct frame_info *this_frame,
+ xtensa_frame_cache_t *cache,
+ CORE_ADDR pc)
+{
+ struct gdbarch *gdbarch = get_frame_arch (this_frame);
+ CORE_ADDR ps, wb, ws, ra;
+ int epc1_regnum, i, regnum;
+ xtensa_exception_handler_t eh_type;
+
+ /* Read PS, WB, and WS from the hardware. Note that PS register
+ must be present, if Windowed ABI is supported. */
+ ps = xtensa_read_register (gdbarch_ps_regnum (gdbarch));
+ wb = xtensa_read_register (gdbarch_tdep (gdbarch)->wb_regnum);
+ ws = xtensa_read_register (gdbarch_tdep (gdbarch)->ws_regnum);
+
+ /* Execute all the remaining instructions from Window Interrupt Handler
+ by simulating them on the remote protocol level. On return, set the
+ type of Xtensa Window Interrupt Handler, or report an error. */
+ eh_type = execute_code (gdbarch, pc, wb);
+ if (eh_type == xtNoExceptionHandler)
+ error (_("\
+Unable to decode Xtensa Window Interrupt Handler's code."));
+
+ cache->ps = ps ^ PS_EXC; /* Clear the exception bit in PS. */
+ cache->call0 = 0; /* It's Windowed ABI. */
+
+ /* All registers for the cached frame will be alive. */
+ for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
+ cache->wd.aregs[i] = -1;
+
+ if (eh_type == xtWindowOverflow)
+ cache->wd.ws = ws ^ (1 << wb);
+ else /* eh_type == xtWindowUnderflow. */
+ cache->wd.ws = ws | (1 << wb);
+
+ cache->wd.wb = (ps & 0xf00) >> 8; /* Set WB to OWB. */
+ regnum = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base,
+ cache->wd.wb);
+ ra = xtensa_read_register (regnum);
+ cache->wd.callsize = WINSIZE (ra);
+ cache->prev_sp = xtensa_read_register (regnum + 1);
+ /* Set regnum to a frame pointer of the frame being cached. */
+ regnum = xtensa_scan_prologue (gdbarch, pc);
+ regnum = arreg_number (gdbarch,
+ gdbarch_tdep (gdbarch)->a0_base + regnum,
+ cache->wd.wb);
+ cache->base = get_frame_register_unsigned (this_frame, regnum);
+
+ /* Read PC of interrupted function from EPC1 register. */
+ epc1_regnum = xtensa_find_register_by_name (gdbarch,"epc1");
+ if (epc1_regnum < 0)
+ error(_("Unable to read Xtensa register EPC1"));
+ cache->ra = xtensa_read_register (epc1_regnum);
+ cache->pc = get_frame_func (this_frame);
+}
+
/* Skip function prologue.
prologue_sal = find_pc_line (start_pc, 0);
if (prologue_sal.line != 0) /* Found debug info. */
{
- /* In Call0, it is possible to have a function with only one instruction
- ('ret') resulting from a 1-line optimized function that does nothing.
- In that case, prologue_sal.end may actually point to the start of the
- next function in the text section, causing a breakpoint to be set at
- the wrong place. Check if the end address is in a different function,
- and if so return the start PC. We know we have symbol info. */
+ /* In Call0, it is possible to have a function with only one instruction
+ ('ret') resulting from a one-line optimized function that does nothing.
+ In that case, prologue_sal.end may actually point to the start of the
+ next function in the text section, causing a breakpoint to be set at
+ the wrong place. Check, if the end address is within a different
+ function, and if so return the start PC. We know we have symbol
+ information. */
CORE_ADDR end_func;
+ if ((gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only)
+ && call0_ret (start_pc, prologue_sal.end))
+ return start_pc;
+
find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL);
if (end_func != start_pc)
return start_pc;
}
/* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
- body_pc = call0_analyze_prologue (gdbarch, start_pc, 0, 0, 0, NULL, NULL);
+ body_pc = call0_analyze_prologue (gdbarch, start_pc, 0, 0,
+ xtensa_alloc_frame_cache (0));
return body_pc != 0 ? body_pc : start_pc;
}
/* Verify our configuration. */
xtensa_verify_config (gdbarch);
+ xtensa_session_once_reported = 0;
/* Pseudo-Register read/write. */
set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read);
set_gdbarch_register_name (gdbarch, xtensa_register_name);
set_gdbarch_register_type (gdbarch, xtensa_register_type);
- /* To call functions from GDB using dummy frame */
+ /* To call functions from GDB using dummy frame. */
set_gdbarch_push_dummy_call (gdbarch, xtensa_push_dummy_call);
set_gdbarch_believe_pcc_promotion (gdbarch, 1);
gdbarch_register (bfd_arch_xtensa, xtensa_gdbarch_init, xtensa_dump_tdep);
xtensa_init_reggroups ();
- add_setshow_zinteger_cmd ("xtensa",
- class_maintenance,
- &xtensa_debug_level, _("\
-Set Xtensa debugging."), _("\
-Show Xtensa debugging."), _("\
+ add_setshow_zuinteger_cmd ("xtensa",
+ class_maintenance,
+ &xtensa_debug_level,
+ _("Set Xtensa debugging."),
+ _("Show Xtensa debugging."), _("\
When non-zero, Xtensa-specific debugging is enabled. \
Can be 1, 2, 3, or 4 indicating the level of debugging."),
- NULL,
- NULL,
- &setdebuglist, &showdebuglist);
+ NULL,
+ NULL,
+ &setdebuglist, &showdebuglist);
}
projects / thirdparty / binutils-gdb.git / blobdiff