#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 4
-#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTD, 5
+#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(4)
+#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(5)
/* PMECC & PMERRLOC */
#define CONFIG_ATMEL_NAND_HWECC