+2008-11-18 Catherine Moore <clm@codesourcery.com>
+
+ * arm.h (FPU_NEON_FP16): New.
+ (FPU_ARCH_NEON_FP16): New.
+
+2008-11-06 Chao-ying Fu <fu@mips.com>
+
+ * mips.h: Doucument '1' for 5-bit sync type.
+
+2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
+
+ * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
+ IA64_RS_CR.
+
+2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
+
+2008-07-30 Michael J. Eager <eager@eagercon.com>
+
+ * ppc.h (PPC_OPCODE_405): Define.
+ (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
+
+2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc.h (ppc_cpu_t): New typedef.
+ (struct powerpc_opcode <flags>): Use it.
+ (struct powerpc_operand <insert, extract>): Likewise.
+ (struct powerpc_macro <flags>): Likewise.
+
+2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
+
+ * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
+ Update comment before MIPS16 field descriptors to mention MIPS16.
+ (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
+ BBIT.
+ (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
+ New bit masks and shift counts for cins and exts.
+
+ * mips.h: Document new field descriptors +Q.
+ (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
+
+2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
+
+ * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
+ (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
+
+2008-04-14 Edmar Wienskoski <edmar@freescale.com>
+
+ * ppc.h: (PPC_OPCODE_E500MC): New.
+
+2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386.h (MAX_OPERANDS): Set to 5.
+ (MAX_MNEM_SIZE): Changed to 20.
+
+2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
+
+ * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
+
+2008-03-09 Paul Brook <paul@codesourcery.com>
+
+ * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
+
+2008-03-04 Paul Brook <paul@codesourcery.com>
+
+ * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
+ (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
+ (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
+
+2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
+ Nick Clifton <nickc@redhat.com>
+
+ PR 3134
+ * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
+ with a 32-bit displacement but without the top bit of the 4th byte
+ set.
+
+2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
+
+ * cr16.h (cr16_num_optab): Declared.
+
+2008-02-14 Hakan Ardo <hakan@debian.org>
+
+ PR gas/2626
+ * avr.h (AVR_ISA_2xxe): Define.
+
+2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
+
+ * mips.h: Update copyright.
+ (INSN_CHIP_MASK): New macro.
+ (INSN_OCTEON): New macro.
+ (CPU_OCTEON): New macro.
+ (OPCODE_IS_MEMBER): Handle Octeon instructions.
+
+2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
+
+ * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
+
+2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
+
+ * avr.h (AVR_ISA_USB162): Add new opcode set.
+ (AVR_ISA_AVR3): Likewise.
+
+2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
+
+ * mips.h (INSN_LOONGSON_2E): New.
+ (INSN_LOONGSON_2F): New.
+ (CPU_LOONGSON_2E): New.
+ (CPU_LOONGSON_2F): New.
+ (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
+
+2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
+
+ * mips.h (INSN_ISA*): Redefine certain values as an
+ enumeration. Update comments.
+ (mips_isa_table): New.
+ (ISA_MIPS*): Redefine to match enumeration.
+ (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
+ values.
+
+2007-08-08 Ben Elliston <bje@au.ibm.com>
+
+ * ppc.h (PPC_OPCODE_PPCPS): New.
+
+2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
+
+ * m68k.h: Document j K & E.
+
+2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
+
+ * cr16.h: New file for CR16 target.
+
+2007-05-02 Alan Modra <amodra@bigpond.net.au>
+
+ * ppc.h (PPC_OPERAND_PLUS1): Update comment.
+
+2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
+
+ * m68k.h (mcfisa_c): New.
+ (mcfusp, mcf_mask): Adjust.
+
+2007-04-20 Alan Modra <amodra@bigpond.net.au>
+
+ * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
+ (num_powerpc_operands): Declare.
+ (PPC_OPERAND_SIGNED et al): Redefine as hex.
+ (PPC_OPERAND_PLUS1): Define.
+
+2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386.h (REX_MODE64): Renamed to ...
+ (REX_W): This.
+ (REX_EXTX): Renamed to ...
+ (REX_R): This.
+ (REX_EXTY): Renamed to ...
+ (REX_X): This.
+ (REX_EXTZ): Renamed to ...
+ (REX_B): This.
+
+2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386.h: Add entries from config/tc-i386.h and move tables
+ to opcodes/i386-opc.h.
+
+2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386.h (FloatDR): Removed.
+ (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
+
+2007-03-01 Alan Modra <amodra@bigpond.net.au>
+
+ * spu-insns.h: Add soma double-float insns.
+
+2007-02-20 Thiemo Seufer <ths@mips.com>
+ Chao-Ying Fu <fu@mips.com>
+
+ * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
+ (INSN_DSPR2): Add flag for DSP R2 instructions.
+ (M_BALIGN): New macro.
+
+2007-02-14 Alan Modra <amodra@bigpond.net.au>
+
+ * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
+ and Seg3ShortFrom with Shortform.
+
+2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/4027
+ * i386.h (i386_optab): Put the real "test" before the pseudo
+ one.
+
+2007-01-08 Kazu Hirata <kazu@codesourcery.com>
+
+ * m68k.h (m68010up): OR fido_a.
+
+2006-12-25 Kazu Hirata <kazu@codesourcery.com>
+
+ * m68k.h (fido_a): New.
+
+2006-12-24 Kazu Hirata <kazu@codesourcery.com>
+
+ * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
+ mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
+ values.
+
+2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
+
+2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
+
+ * score-inst.h (enum score_insn_type): Add Insn_internal.
+
+2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
+ Yukishige Shibata <shibata@rd.scei.sony.co.jp>
+ Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
+ Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
+ Alan Modra <amodra@bigpond.net.au>
+
+ * spu-insns.h: New file.
+ * spu.h: New file.
+
+2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
+
+ * ppc.h (PPC_OPCODE_CELL): Define.
+
+2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
+
+ * i386.h : Modify opcode to support for the change in POPCNT opcode
+ in amdfam10 architecture.
+
+2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386.h: Replace CpuMNI with CpuSSSE3.
+
+2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
+ Joseph Myers <joseph@codesourcery.com>
+ Ian Lance Taylor <ian@wasabisystems.com>
+ Ben Elliston <bje@wasabisystems.com>
+
+ * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
+
+2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
+
+ * score-datadep.h: New file.
+ * score-inst.h: New file.
+
+2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
+ movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
+ movdq2q and movq2dq.
+
+2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
+ Michael Meissner <michael.meissner@amd.com>
+
+ * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
+
+2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386.h (i386_optab): Add "nop" with memory reference.
+
+2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386.h (i386_optab): Update comment for 64bit NOP.
+
+2006-06-06 Ben Elliston <bje@au.ibm.com>
+ Anton Blanchard <anton@samba.org>
+
+ * ppc.h (PPC_OPCODE_POWER6): Define.
+ Adjust whitespace.
+
+2006-06-05 Thiemo Seufer <ths@mips.com>
+
+ * mips.h: Improve description of MT flags.
+
+2006-05-25 Richard Sandiford <richard@codesourcery.com>
+
+ * m68k.h (mcf_mask): Define.
+
+2006-05-05 Thiemo Seufer <ths@mips.com>
+ David Ung <davidu@mips.com>
+
+ * mips.h (enum): Add macro M_CACHE_AB.
+
+2006-05-04 Thiemo Seufer <ths@mips.com>
+ Nigel Stephens <nigel@mips.com>
+ David Ung <davidu@mips.com>
+
+ * mips.h: Add INSN_SMARTMIPS define.
+
+2006-04-30 Thiemo Seufer <ths@mips.com>
+ David Ung <davidu@mips.com>
+
+ * mips.h: Defines udi bits and masks. Add description of
+ characters which may appear in the args field of udi
+ instructions.
+
+2006-04-26 Thiemo Seufer <ths@networkno.de>
+
+ * mips.h: Improve comments describing the bitfield instruction
+ fields.
+
+2006-04-26 Julian Brown <julian@codesourcery.com>
+
+ * arm.h (FPU_VFP_EXT_V3): Define constant.
+ (FPU_NEON_EXT_V1): Likewise.
+ (FPU_VFP_HARD): Update.
+ (FPU_VFP_V3): Define macro.
+ (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
+
+2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
+
+ * avr.h (AVR_ISA_PWMx): New.
+
+2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
+
+ * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
+ cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
+ cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
+ cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
+ cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
+
+2006-03-10 Paul Brook <paul@codesourcery.com>
+
+ * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
+
+2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
+
+ * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
+ first. Correct mask of bb "B" opcode.
+
+2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386.h (i386_optab): Support Intel Merom New Instructions.
+
+2006-02-24 Paul Brook <paul@codesourcery.com>
+
+ * arm.h: Add V7 feature bits.
+
+2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
+
+ * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
+
+2006-01-31 Paul Brook <paul@codesourcery.com>
+ Richard Earnshaw <rearnsha@arm.com>
+
+ * arm.h: Use ARM_CPU_FEATURE.
+ (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
+ (arm_feature_set): Change to a structure.
+ (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
+ ARM_FEATURE): New macros.
+
+2005-12-07 Hans-Peter Nilsson <hp@axis.com>
+
+ * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
+ (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
+ (ADD_PC_INCR_OPCODE): Don't define.
+
+2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/1874
+ * i386.h (i386_optab): Add 64bit support for monitor and mwait.
+
+2005-11-14 David Ung <davidu@mips.com>
+
+ * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
+ instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
+ save/restore encoding of the args field.
+
+2005-10-28 Dave Brolley <brolley@redhat.com>
+
+ Contribute the following changes:
+ 2005-02-16 Dave Brolley <brolley@redhat.com>
+
+ * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
+ cgen_isa_mask_* to cgen_bitset_*.
+ * cgen.h: Likewise.
+
+ 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
+
+ * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
+ (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
+ (CGEN_CPU_TABLE): Make isas a ponter.
+
+ 2003-09-29 Dave Brolley <brolley@redhat.com>
+
+ * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
+ (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
+ (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
+
+ 2002-12-13 Dave Brolley <brolley@redhat.com>
+
+ * cgen.h (symcat.h): #include it.
+ (cgen-bitset.h): #include it.
+ (CGEN_ATTR_VALUE_TYPE): Now a union.
+ (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
+ (CGEN_ATTR_ENTRY): 'value' now unsigned.
+ (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
+ * cgen-bitset.h: New file.
+
+2005-09-30 Catherine Moore <clm@cm00re.com>
+
+ * bfin.h: New file.
+
+2005-10-24 Jan Beulich <jbeulich@novell.com>
+
+ * ia64.h (enum ia64_opnd): Move memory operand out of set of
+ indirect operands.
+
+2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
+
+ * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
+ Add FLAG_STRICT to pa10 ftest opcode.
+
+2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
+
+ * hppa.h (pa_opcodes): Remove lha entries.
+
+2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
+
+ * hppa.h (FLAG_STRICT): Revise comment.
+ (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
+ before corresponding pa11 opcodes. Add strict pa10 register-immediate
+ entries for "fdc".
+
+2005-09-30 Catherine Moore <clm@cm00re.com>
+
+ * bfin.h: New file.
+
+2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
+
+ * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
+
+2005-09-06 Chao-ying Fu <fu@mips.com>
+
+ * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
+ OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
+ define.
+ Document !, $, *, &, g, +t, +T operand formats for MT instructions.
+ (INSN_ASE_MASK): Update to include INSN_MT.
+ (INSN_MT): New define for MT ASE.
+
+2005-08-25 Chao-ying Fu <fu@mips.com>
+
+ * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
+ OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
+ OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
+ OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
+ OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
+ Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
+ instructions.
+ (INSN_DSP): New define for DSP ASE.
+
+2005-08-18 Alan Modra <amodra@bigpond.net.au>
+
+ * a29k.h: Delete.
+
+2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
+
+ * ppc.h (PPC_OPCODE_E300): Define.
+
+2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
+
+ * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
+
+2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
+
+ PR gas/336
+ * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
+ and pitlb.
+
+2005-07-27 Jan Beulich <jbeulich@novell.com>
+
+ * i386.h (i386_optab): Add comment to movd. Use LongMem for all
+ movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
+ Add movq-s as 64-bit variants of movd-s.
+
+2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
+
+ * hppa.h: Fix punctuation in comment.
+
+ * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
+ implicit space-register addressing. Set space-register bits on opcodes
+ using implicit space-register addressing. Add various missing pa20
+ long-immediate opcodes. Remove various opcodes using implicit 3-bit
+ space-register addressing. Use "fE" instead of "fe" in various
+ fstw opcodes.
+
+2005-07-18 Jan Beulich <jbeulich@novell.com>
+
+ * i386.h (i386_optab): Operands of aam and aad are unsigned.
+
+2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386.h (i386_optab): Support Intel VMX Instructions.
+
+2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
+
+ * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
+
2005-07-05 Jan Beulich <jbeulich@novell.com>
* i386.h (i386_optab): Add new insns.
FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
fnstsw.
+2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
+
+ * m68k.h (m68008, m68ec030, m68882): Remove.
+ (m68k_mask): New.
+ (cpu_m68k, cpu_cf): New.
+ (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
+ mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
+
2005-01-25 Alexandre Oliva <aoliva@redhat.com>
2004-11-10 Alexandre Oliva <aoliva@redhat.com>
projects / thirdparty / binutils-gdb.git / blobdiff