/* Opcode table header for m680[01234]0/m6888[12]/m68851.
- Copyright 1989, 1991, 1992, 1993, 1994, 1995 Free Software Foundation.
+ Copyright (C) 1989-2021 Free Software Foundation, Inc.
-This file is part of GDB, GAS, and the GNU binutils.
+ This file is part of GDB, GAS, and the GNU binutils.
-GDB, GAS, and the GNU binutils are free software; you can redistribute
-them and/or modify them under the terms of the GNU General Public
-License as published by the Free Software Foundation; either version
-1, or (at your option) any later version.
+ GDB, GAS, and the GNU binutils are free software; you can redistribute
+ them and/or modify them under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either version 3,
+ or (at your option) any later version.
-GDB, GAS, and the GNU binutils are distributed in the hope that they
-will be useful, but WITHOUT ANY WARRANTY; without even the implied
-warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
-the GNU General Public License for more details.
+ GDB, GAS, and the GNU binutils are distributed in the hope that they
+ will be useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ the GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this file; see the file COPYING. If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this file; see the file COPYING3. If not, write to the Free
+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+ 02110-1301, USA. */
/* These are used as bit flags for the arch field in the m68k_opcode
structure. */
#define _m68k_undef 0
-#define m68000 0x001
-#define m68008 m68000 /* synonym for -m68000. otherwise unused. */
-#define m68010 0x002
-#define m68020 0x004
-#define m68030 0x008
-#define m68ec030 m68030 /* similar enough to -m68030 to ignore differences;
- gas will deal with the few differences. */
-#define m68040 0x010
-/* there is no 68050 */
-#define m68060 0x020
-#define m68881 0x040
-#define m68882 m68881 /* synonym for -m68881. otherwise unused. */
-#define m68851 0x080
-#define cpu32 0x100 /* e.g., 68332 */
-#define mcf5200 0x200
-/* start-sanitize-coldfire */
-#define mcfmac 0x400 /* coldfire multiply accumlate module */
-#define mcfdiv 0x800 /* coldfire integer division module */
-/* end-sanitize-coldfire */
-
- /* handy aliases */
-#define m68040up (m68040 | m68060)
-#define m68030up (m68030 | m68040up)
-#define m68020up (m68020 | m68030up)
-#define m68010up (m68010 | cpu32 | m68020up)
-#define m68000up (m68000 | m68010up)
-
-#define mfloat (m68881 | m68882 | m68040 | m68060)
+#define m68000 0x001
+#define m68010 0x002
+#define m68020 0x004
+#define m68030 0x008
+#define m68040 0x010
+#define m68060 0x020
+#define m68881 0x040
+#define m68851 0x080
+#define cpu32 0x100 /* e.g., 68332 */
+#define fido_a 0x200
+#define m68k_mask 0x3ff
+
+#define mcfmac 0x400 /* ColdFire MAC. */
+#define mcfemac 0x800 /* ColdFire EMAC. */
+#define cfloat 0x1000 /* ColdFire FPU. */
+#define mcfhwdiv 0x2000 /* ColdFire hardware divide. */
+
+#define mcfisa_a 0x4000 /* ColdFire ISA_A. */
+#define mcfisa_aa 0x8000 /* ColdFire ISA_A+. */
+#define mcfisa_b 0x10000 /* ColdFire ISA_B. */
+#define mcfisa_c 0x20000 /* ColdFire ISA_C. */
+#define mcfusp 0x40000 /* ColdFire USP instructions. */
+#define mcf_mask 0x7e400
+
+/* Handy aliases. */
+#define m68040up (m68040 | m68060)
+#define m68030up (m68030 | m68040up)
+#define m68020up (m68020 | m68030up)
+#define m68010up (m68010 | cpu32 | fido_a | m68020up)
+#define m68000up (m68000 | m68010up)
+
+#define mfloat (m68881 | m68040 | m68060)
#define mmmu (m68851 | m68030 | m68040 | m68060)
/* The structure used to hold information for an opcode. */
{
/* The opcode name. */
const char *name;
+ /* The pseudo-size of the instruction(in bytes). Used to determine
+ number of bytes necessary to disassemble the instruction. */
+ unsigned int size;
/* The opcode itself. */
unsigned long opcode;
/* The mask used by the disassembler. */
The args field is a string containing two characters for each
operand of the instruction. The first specifies the kind of
- operand; the second, the place it is stored. */
+ operand; the second, the place it is stored.
+
+ If the first char of args is '.', it indicates that the opcode is
+ two words. This is only necessary when the match field does not
+ have any bits set in the second opcode word. Such a '.' is skipped
+ for operand processing. */
/* Kinds of operands:
- Characters used: AaBCcDdFfIJkLlMOQRrSsTtUVWXYZ0123|*~%;@!&$?/#^+-
+ Characters used: AaBbCcDdEeFfGgHIiJjKkLlMmnOopQqRrSsTtUuVvWwXxYyZz01234|*~%;@!&$?/<>#^+-
D data register only. Stored as 3 bits.
A address register only. Stored as 3 bits.
C the CCR. No need to store it; this is just for filtering validity.
S the SR. No need to store, just as with CCR.
U the USP. No need to store, just as with CCR.
+ E the MAC ACC. No need to store, just as with CCR.
+ e the EMAC ACC[0123].
+ G the MAC/EMAC MACSR. No need to store, just as with CCR.
+ g the EMAC ACCEXT{01,23}.
+ H the MASK. No need to store, just as with CCR.
+ i the MAC/EMAC scale factor.
I Coprocessor ID. Not printed if 1. The Coprocessor ID is always
extracted from the 'd' field of word one, which means that an extended
Possible values:
0x000 SFC Source Function Code reg [60, 40, 30, 20, 10]
0x001 DFC Data Function Code reg [60, 40, 30, 20, 10]
- 0x002 CACR Cache Control Register [60, 40, 30, 20]
+ 0x002 CACR Cache Control Register [60, 40, 30, 20, mcf]
0x003 TC MMU Translation Control [60, 40]
0x004 ITT0 Instruction Transparent
Translation reg 0 [60, 40]
Translation reg 1 [60, 40]
0x008 BUSCR Bus Control Register [60]
0x800 USP User Stack Pointer [60, 40, 30, 20, 10]
- 0x801 VBR Vector Base reg [60, 40, 30, 20, 10]
+ 0x801 VBR Vector Base reg [60, 40, 30, 20, 10, mcf]
0x802 CAAR Cache Address Register [ 30, 20]
0x803 MSP Master Stack Pointer [ 40, 30, 20]
0x804 ISP Interrupt Stack Pointer [ 40, 30, 20]
0xC04 RAMBAR0 RAM Base Address Register 0 [520X]
0xC05 RAMBAR1 RAM Base Address Register 0 [520X]
0xC0F MBAR0 RAM Base Address Register 0 [520X]
+ 0xC04 FLASHBAR FLASH Base Address Register [mcf528x]
+ 0xC05 RAMBAR Static RAM Base Address Register [mcf528x]
L Register list of the type d0-d7/a0-a7 etc.
(New! Improved! Can also hold fp0-fp7, as well!)
for both caches. Used in cinv and cpush. Always
stored in position "d".
+ u Any register, with ``upper'' or ``lower'' specification. Used
+ in the mac instructions with size word.
+
The remainder are all stored as 6 bits using an address mode and a
register number; they differ in which addressing modes they match.
- * all (modes 0-6,7.*)
+ * all (modes 0-6,7.0-4)
~ alterable memory (modes 2-6,7.0,7.1)
- (not 0,1,7.~)
+ (not 0,1,7.2-4)
% alterable (modes 0-6,7.0,7.1)
- (not 7.~)
- ; data (modes 0,2-6,7.*)(not 1)
- @ data, but not immediate (modes 0,2-6,7.? ? ?)
- (not 1,7.?)
- This may really be ;,
- the 68020 book says it is
- ! control (modes 2,5,6,7.*-)
+ (not 7.2-4)
+ ; data (modes 0,2-6,7.0-4)
+ (not 1)
+ @ data, but not immediate (modes 0,2-6,7.0-3)
+ (not 1,7.4)
+ ! control (modes 2,5,6,7.0-3)
(not 0,1,3,4,7.4)
& alterable control (modes 2,5,6,7.0,7.1)
- (not 0,1,7.? ? ?)
+ (not 0,1,3,4,7.2-4)
$ alterable data (modes 0,2-6,7.0,7.1)
- (not 1,7.~)
+ (not 1,7.2-4)
? alterable control, or data register (modes 0,2,5,6,7.0,7.1)
- (not 1,3,4,7.~)
- / control, or data register (modes 0,2,5,6,7.0,7.1,7.2,7.3)
+ (not 1,3,4,7.2-4)
+ / control, or data register (modes 0,2,5,6,7.0-3)
(not 1,3,4,7.4)
- ` control, plus pre-dec, not simple indir. (modes 4,5,6,7.*-)
- (not 0,1,2,3,7.4)
> *save operands (modes 2,4,5,6,7.0,7.1)
- < *restore operands (modes 2,3,5,6,7.0,7.1,7.2,7.3)
+ (not 0,1,3,7.2-4)
+ < *restore operands (modes 2,3,5,6,7.0-3)
+ (not 0,1,4,7.4)
coldfire move operands:
m (modes 0-4)
n (modes 5,7.2)
- o (modes 6,7.0,7.1,7.3)
+ o (modes 6,7.0,7.1,7.3,7.4)
p (modes 0-5)
- coldfire bset/bclr/btst operands:
+ coldfire bset/bclr/btst/mulsl/mulul operands:
q (modes 0,2-5)
v (modes 0,2-5,7.0,7.1)
-*/
-
-/* For the 68851: */
-/*
- I didn't use much imagination in choosing the
+ b (modes 0,2-5,7.2)
+ w (modes 2-5,7.2)
+ y (modes 2,5)
+ z (modes 2,5,7.2)
+ x mov3q immediate operand.
+ j coprocessor ET operand.
+ K coprocessor command number.
+ 4 (modes 2,3,4,5)
+ */
+
+/* For the 68851: */
+/* I didn't use much imagination in choosing the
following codes, so many of them aren't very
mnemonic. -rab
*/
/* Places to put an operand, for non-general operands:
+ Characters used: BbCcDdFfGgHhIijkLlMmNnostWw123456789/
+
s source, low bits of first word.
d dest, shifted 9 in first word
1 second word, shifted 12
7 second word, shifted 7
8 second word, shifted 10
9 second word, shifted 5
+ E second word, shifted 9
D store in both place 1 and place 3; for divul and divsl.
B first word, low byte, for branch displacements
W second word (entire), for branch displacements
C floating point coprocessor constant - 7 bits. Also used for static
K-factors...
j Movec register #, stored in 12 low bits of second word.
+ m For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word
+ and remaining 3 bits of register shifted 9 bits in first word.
+ Indicate upper/lower in 1 bit shifted 7 bits in second word.
+ Use with `R' or `u' format.
+ n `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split
+ with MSB shifted 6 bits in first word and remaining 3 bits of
+ register shifted 9 bits in first word. No upper/lower
+ indication is done.) Use with `R' or `u' format.
+ o For M[S]ACw; 4 bits shifted 12 in second word (like `1').
+ Indicate upper/lower in 1 bit shifted 7 bits in second word.
+ Use with `R' or `u' format.
+ M For M[S]ACw; 4 bits in low bits of first word. Indicate
+ upper/lower in 1 bit shifted 6 bits in second word. Use with
+ `R' or `u' format.
+ N For M[S]ACw; 4 bits in low bits of second word. Indicate
+ upper/lower in 1 bit shifted 6 bits in second word. Use with
+ `R' or `u' format.
+ h shift indicator (scale factor), 1 bit shifted 10 in second word
Places to put operand, for general operands:
d destination, shifted 6 bits in first word
F double precision float, low bit of 1st word, immediate uses 8 bytes
x extended precision float, low bit of 1st word, immediate uses 12 bytes
p packed float, low bit of 1st word, immediate uses 12 bytes
+ G EMAC accumulator, load (bit 4 2nd word, !bit8 first word)
+ H EMAC accumulator, non load (bit 4 2nd word, bit 8 first word)
+ F EMAC ACCx
+ f EMAC ACCy
+ I MAC/EMAC scale factor
+ / Like 's', but set 2nd word, bit 5 if trailing_ampersand set
+ ] first word, bit 10
*/
extern const struct m68k_opcode m68k_opcodes[];
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