/* mips.h. Mips opcode list for GDB, the GNU debugger.
- Copyright (C) 1993-2016 Free Software Foundation, Inc.
+ Copyright (C) 1993-2021 Free Software Foundation, Inc.
Contributed by Ralph Campbell and OSF
Commented and modified by Ian Lance Taylor, Cygnus Support
code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
only use ten bits). An optional two-operand form of break/sdbbp
allows the lower ten bits to be set too, and MIPS32 and later
- architectures allow 20 bits to be set with a signal operand
- (using CODE20).
+ architectures allow 20 bits to be set with a single operand for
+ the sdbbp instruction (using CODE20).
The syscall instruction uses CODE20.
/* $pc, which has no encoding in the architectural instruction. */
OP_PC,
+ /* $28, which has no encoding in the MIPS16e architectural instruction. */
+ OP_REG28,
+
/* A 4-bit XYZW channel mask or 2-bit XYZW index; the size determines
which. */
OP_VU0_SUFFIX,
also be used in some contexts. */
OP_REG_COPRO,
+ /* Coprocessor control registers $0-$31. Mnemonic names like c1_fcsr can
+ also be used in some contexts. */
+ OP_REG_CONTROL,
+
/* Hardware registers $0-$31. Mnemonic names like hwr_cpunum can
also be used in some contexts. */
OP_REG_HW,
unsigned int shift;
/* True if the operand should be printed as hex rather than decimal. */
- bfd_boolean print_hex;
+ bool print_hex;
};
/* Uses a lookup table to describe a small integer operand. */
const int *int_map;
/* True if the operand should be printed as hex rather than decimal. */
- bfd_boolean print_hex;
+ bool print_hex;
};
/* An operand that encodes the most significant bit position of a bitfield.
/* True if the operand encodes MSB directly, false if it encodes
MSB - LSB. */
- bfd_boolean add_lsb;
+ bool add_lsb;
/* The maximum value of MSB + 1. */
unsigned int opsize;
{
struct mips_operand root;
- bfd_boolean greater_than_ok;
- bfd_boolean less_than_ok;
- bfd_boolean equal_ok;
- bfd_boolean zero_ok;
+ bool greater_than_ok;
+ bool less_than_ok;
+ bool equal_ok;
+ bool zero_ok;
};
/* Describes an operand that encodes a pair of registers. */
/* Return true if the assembly syntax allows OPERAND to be omitted. */
-static inline bfd_boolean
+static inline bool
mips_optional_operand_p (const struct mips_operand *operand)
{
return (operand->type == OP_OPTIONAL_REG
/* Return true if MO is an instruction that requires 32-bit encoding. */
-static inline bfd_boolean
+static inline bool
mips_opcode_32bit_p (const struct mips_opcode *mo)
{
return mo->mask >> 16 != 0;
"H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
"P" 5 bit performance-monitor register (OP_*_PERFREG)
"e" 5 bit vector register byte specifier (OP_*_VECBYTE)
+ "g" 5 bit control destination register (OP_*_RD)
"%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
Macro instructions:
"$" 1 bit load high flag (OP_*_MT_H)
"*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
"&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
- "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
+ "y" 5 bit control target register (OP_*_RT)
"+t" 5 bit coprocessor 0 destination register (OP_*_RT)
MCU ASE usage:
"+S" Length-minus-one field of cins/exts. Requires msb position
of the field to be <= 63.
- Loongson-3A:
+ Loongson-ext ASE:
"+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A)
"+b" 8-bit signed offset in bit 3 (OP_*_OFFSET_B)
"+c" 9-bit signed offset in bit 6 (OP_*_OFFSET_C)
"+z" 5-bit rz register (OP_*_RZ)
"+Z" 5-bit fz register (OP_*_FZ)
+ interAptiv MR2:
+ "-m" register list for SAVE/RESTORE instruction
+
Enhanced VA Scheme:
"+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET)
"-A" symbolic offset (-262144 .. 262143) << 2 at bit 0
"-B" symbolic offset (-131072 .. 131071) << 3 at bit 0
+ GINV ASE usage:
+ "+\" 2 bit Global TLB invalidate type at bit 8
+
Other:
"()" parens surrounding optional value
"," separates operands
"1234567890"
"%[]<>(),+-:'@!#$*&\~"
"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
- "abcdefghijklopqrstuvwxz"
+ "abcdef hijkl opqrstuvwxyz"
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
"1234567890"
- "~!@#$%^&*|:'";"
+ "~!@#$%^&*|:'";\"
"ABCEFGHIJKLMNOPQRSTUVWXZ"
"abcdefghijklmnopqrstuvwxyz"
Extension character sequences used so far ("-" followed by the
following), for quick reference when adding more:
"AB"
- "abdstuvwxy"
+ "abdmstuvwxy"
*/
/* These are the bits which may be set in the pinfo field of an
#define INSN2_VU0_CHANNEL_SUFFIX 0x00004000
/* Instruction has a forbidden slot. */
#define INSN2_FORBIDDEN_SLOT 0x00008000
+/* Opcode table entry is for a short MIPS16 form only. An extended
+ encoding may still exist, but with a separate opcode table entry
+ required. In disassembly the presence of this flag in an otherwise
+ successful match against an extended instruction encoding inhibits
+ matching against any subsequent short table entry even if it does
+ not have this flag set. A table entry matching the full extended
+ encoding is needed or otherwise the final EXTEND entry will apply,
+ for the disassembly of the prefix only. */
+#define INSN2_SHORT_ONLY 0x00010000
/* Masks used to mark instructions to indicate which MIPS ISA level
they were introduced in. INSN_ISA_MASK masks an enumeration that
#undef ISAF
/* Masks used for Chip specific instructions. */
-#define INSN_CHIP_MASK 0xc3ff4f60
+#define INSN_CHIP_MASK 0xc7ff4f60
/* Cavium Networks Octeon instructions. */
#define INSN_OCTEON 0x00000800
#define INSN_LOONGSON_2E 0x40000000
/* ST Microelectronics Loongson 2F. */
#define INSN_LOONGSON_2F 0x80000000
-/* Loongson 3A. */
-#define INSN_LOONGSON_3A 0x00000400
/* RMI Xlr instruction */
#define INSN_XLR 0x00000020
+/* Imagination interAptiv MR2. */
+#define INSN_INTERAPTIV_MR2 0x04000000
/* DSP ASE */
#define ASE_DSP 0x00000001
#define ASE_XPA 0x00002000
/* DSP R3 Module. */
#define ASE_DSPR3 0x00004000
+/* MIPS16e2 ASE. */
+#define ASE_MIPS16E2 0x00008000
+/* MIPS16e2 MT ASE instructions. */
+#define ASE_MIPS16E2_MT 0x00010000
+/* The Virtualization ASE has eXtended Physical Addressing (XPA)
+ instructions which are only valid when both ASEs are enabled. */
+#define ASE_XPA_VIRT 0x00020000
+/* Cyclic redundancy check (CRC) ASE. */
+#define ASE_CRC 0x00040000
+#define ASE_CRC64 0x00080000
+/* Global INValidate Extension. */
+#define ASE_GINV 0x00100000
+/* Loongson MultiMedia extensions Instructions (MMI). */
+#define ASE_LOONGSON_MMI 0x00200000
+/* Loongson Content Address Memory (CAM). */
+#define ASE_LOONGSON_CAM 0x00400000
+/* Loongson EXTensions (EXT) instructions. */
+#define ASE_LOONGSON_EXT 0x00800000
+/* Loongson EXTensions R2 (EXT2) instructions. */
+#define ASE_LOONGSON_EXT2 0x01000000
+/* The Enhanced VA Scheme (EVA) extension has instructions which are
+ only valid for the R6 ISA. */
+#define ASE_EVA_R6 0x02000000
/* MIPS ISA defines, use instead of hardcoding ISA level. */
#define CPU_SB1 12310201 /* octal 'SB', 01. */
#define CPU_LOONGSON_2E 3001
#define CPU_LOONGSON_2F 3002
-#define CPU_LOONGSON_3A 3003
+#define CPU_GS464 3003
+#define CPU_GS464E 3004
+#define CPU_GS264E 3005
#define CPU_OCTEON 6501
#define CPU_OCTEONP 6601
#define CPU_OCTEON2 6502
#define CPU_OCTEON3 6503
#define CPU_XLR 887682 /* decimal 'XLR' */
+#define CPU_INTERAPTIV_MR2 736550 /* decimal 'IA2' */
/* Return true if the given CPU is included in INSN_* mask MASK. */
-static inline bfd_boolean
+static inline bool
cpu_is_member (int cpu, unsigned int mask)
{
switch (cpu)
case CPU_LOONGSON_2F:
return (mask & INSN_LOONGSON_2F) != 0;
- case CPU_LOONGSON_3A:
- return (mask & INSN_LOONGSON_3A) != 0;
-
case CPU_OCTEON:
return (mask & INSN_OCTEON) != 0;
case CPU_XLR:
return (mask & INSN_XLR) != 0;
- case CPU_MIPS32R6:
- return (mask & INSN_ISA_MASK) == INSN_ISA32R6;
-
- case CPU_MIPS64R6:
- return ((mask & INSN_ISA_MASK) == INSN_ISA32R6)
- || ((mask & INSN_ISA_MASK) == INSN_ISA64R6);
+ case CPU_INTERAPTIV_MR2:
+ return (mask & INSN_INTERAPTIV_MR2) != 0;
default:
- return FALSE;
+ return false;
}
}
+/* Return true if the given ISA is included in INSN_* mask MASK. */
+
+static inline bool
+isa_is_member (int isa, unsigned int mask)
+{
+ isa &= INSN_ISA_MASK;
+ mask &= INSN_ISA_MASK;
+
+ if (isa == 0)
+ return false;
+
+ if (mask == 0)
+ return false;
+
+ if (((mips_isa_table[isa - 1] >> (mask - 1)) & 1) == 0)
+ return false;
+
+ return true;
+}
+
/* Test for membership in an ISA including chip specific ISAs. INSN
is pointer to an element of the opcode table; ISA is the specified
ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
test, or zero if no CPU specific ISA test is desired. Return true
if instruction INSN is available to the given ISA and CPU. */
-static inline bfd_boolean
+static inline bool
opcode_is_member (const struct mips_opcode *insn, int isa, int ase, int cpu)
{
- if (!cpu_is_member (cpu, insn->exclusions))
- {
- /* Test for ISA level compatibility. */
- if ((isa & INSN_ISA_MASK) != 0
- && (insn->membership & INSN_ISA_MASK) != 0
- && ((mips_isa_table[(isa & INSN_ISA_MASK) - 1]
- >> ((insn->membership & INSN_ISA_MASK) - 1)) & 1) != 0)
- return TRUE;
-
- /* Test for ASE compatibility. */
- if ((ase & insn->ase) != 0)
- return TRUE;
-
- /* Test for processor-specific extensions. */
- if (cpu_is_member (cpu, insn->membership))
- return TRUE;
- }
- return FALSE;
+ /* Test for ISA level exclusion. */
+ if (isa_is_member (isa, insn->exclusions))
+ return false;
+
+ /* Test for processor-specific exclusion. */
+ if (cpu_is_member (cpu, insn->exclusions))
+ return false;
+
+ /* Test for ISA level compatibility. */
+ if (isa_is_member (isa, insn->membership))
+ return true;
+
+ /* Test for ASE compatibility. */
+ if ((ase & insn->ase) != 0)
+ return true;
+
+ /* Test for processor-specific extensions. */
+ if (cpu_is_member (cpu, insn->membership))
+ return true;
+
+ return false;
}
/* This is a list of macro expanded instructions.
M_LI_SS,
M_LL_AB,
M_LLD_AB,
+ M_LLDP_AB,
M_LLE_AB,
+ M_LLWP_AB,
+ M_LLWPE_AB,
M_LQ_AB,
M_LW_AB,
M_LWE_AB,
M_SAAD_AB,
M_SC_AB,
M_SCD_AB,
+ M_SCDP_AB,
M_SCE_AB,
+ M_SCWP_AB,
+ M_SCWPE_AB,
M_SD_AB,
M_SDC1_AB,
M_SDC2_AB,
"Z" 3 bit register (MIPS16OP_*_MOVE32Z)
"v" 3 bit same register as source and destination (MIPS16OP_*_RX)
"w" 3 bit same register as source and destination (MIPS16OP_*_RY)
- "0" zero register ($0)
+ "." zero register ($0)
"S" stack pointer ($sp or $29)
"P" program counter
"R" return address register ($ra or $31)
"X" 5 bit MIPS register (MIPS16OP_*_REGR32)
"Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
+ "0" 5-bit ASMACRO p0 immediate
+ "1" 3-bit ASMACRO p1 immediate
+ "2" 3-bit ASMACRO p2 immediate
+ "3" 5-bit ASMACRO p3 immediate
+ "4" 3-bit ASMACRO p4 immediate
"6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
"a" 26 bit jump address
"i" likewise, but flips bit 0
"e" 11 bit extension value
"l" register list for entry instruction
"L" register list for exit instruction
+ ">" 5-bit SYNC code
+ "9" 9-bit signed immediate
+ "G" global pointer ($gp or $28)
+ "N" 5-bit coprocessor register
+ "O" 3-bit sel field for MFC0/MTC0
+ "Q" 5-bit hardware register
+ "T" 5-bit CACHE opcode or PREF hint
+ "b" 5-bit INS/EXT position, which becomes LSB
+ Enforces: 0 <= pos < 32.
+ "c" 5-bit INS size, which becomes MSB
+ Requires that "b" occurs first to set position.
+ Enforces: 0 < (pos+size) <= 32.
+ "d" 5-bit EXT size, which becomes MSBD
+ Requires that "b" occurs first to set position.
+ Enforces: 0 < (pos+size) <= 32.
+ "n" 2-bit immediate (1 .. 4)
+ "o" 5-bit unsigned immediate * 16
+ "r" 3-bit register
+ "s" 3-bit ASMACRO select immediate
+ "u" 16-bit unsigned immediate
"I" an immediate value used for macros
"<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
"[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
"]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
- "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
"5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
+ "F" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
"H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
"W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
"D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
"A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
"B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
"E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
- "m" 7 bit register list for save instruction (18 bit extended)
- "M" 7 bit register list for restore instruction (18 bit extended)
+ "m" 7 bit register list for SAVE/RESTORE instruction (18 bit extended)
Characters used so far, for quick reference when adding more:
- " 456 8 0"
- "[]<"
- "ABCDE HI KLM P RS UVWXYZ"
- "a e ijklm pq vwxyz"
+ "0123456 89"
+ ".[]<>"
+ "ABCDEFGHI KL NOPQRSTUVWXYZ"
+ "abcde ijklmnopqrs uvwxyz"
*/
/* Save/restore encoding for the args field when all 4 registers are
either saved as arguments or saved/restored as statics. */
-#define MIPS16_ALL_ARGS 0xe
-#define MIPS16_ALL_STATICS 0xb
+#define MIPS_SVRS_ALL_ARGS 0xe
+#define MIPS_SVRS_ALL_STATICS 0xb
/* The following flags have the same value for the mips16 opcode
table:
FP_D (never used)
*/
-extern const struct mips_operand *decode_mips16_operand (char, bfd_boolean);
+extern const struct mips_operand *decode_mips16_operand (char, bool);
extern const struct mips_opcode mips16_opcodes[];
extern const int bfd_mips16_num_opcodes;
"E" 5-bit target register (MICROMIPSOP_*_RT)
"G" 5-bit source register (MICROMIPSOP_*_RS)
"H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL)
+ "g" 5-bit control source register (MICROMIPSOP_*_RS)
Macro instructions:
"A" general 32 bit expression
"12345678 0"
"<>(),+-.@\^|~"
"ABCDEFGHI KLMN RST V "
- "abcd f hijklmnopqrstuvw yz"
+ "abcd fghijklmnopqrstuvw yz"
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
projects / thirdparty / binutils-gdb.git / blobdiff