/* ppc.h -- Header file for PowerPC opcode table
- Copyright (C) 1994-2017 Free Software Foundation, Inc.
+ Copyright (C) 1994-2020 Free Software Foundation, Inc.
Written by Ian Lance Taylor, Cygnus Support
This file is part of GDB, GAS, and the GNU binutils.
/* The opcode itself. Those bits which will be filled in with
operands are zeroes. */
- unsigned long opcode;
+ uint64_t opcode;
/* The opcode mask. This is used by the disassembler. This is a
mask containing ones indicating those bits which must match the
opcode field, and zeroes indicating those bits which need not
match (and are presumably filled in by operands). */
- unsigned long mask;
+ uint64_t mask;
/* One bit flags for the opcode. These are used to indicate which
specific processors support the instructions. The defined values
in the order in which the disassembler should consider
instructions. */
extern const struct powerpc_opcode powerpc_opcodes[];
-extern const int powerpc_num_opcodes;
+extern const unsigned int powerpc_num_opcodes;
+extern const struct powerpc_opcode prefix_opcodes[];
+extern const unsigned int prefix_num_opcodes;
extern const struct powerpc_opcode vle_opcodes[];
-extern const int vle_num_opcodes;
+extern const unsigned int vle_num_opcodes;
+extern const struct powerpc_opcode spe2_opcodes[];
+extern const unsigned int spe2_num_opcodes;
/* Values defined for the flags field of a struct powerpc_opcode. */
/* Opcode is only supported by Power8 architecture. */
#define PPC_OPCODE_POWER8 0x1000000000ull
-/* Opcode is supported by ppc750cl. */
+/* Opcode is supported by ppc750cl/Gekko/Broadway. */
#define PPC_OPCODE_750 0x2000000000ull
/* Opcode is supported by ppc7450. */
/* Opcode is supported by PowerPC LSP */
#define PPC_OPCODE_LSP 0x80000000000ull
+/* Opcode is only supported by Freescale SPE2 APU. */
+#define PPC_OPCODE_SPE2 0x100000000000ull
+
+/* Opcode is supported by EFS2. */
+#define PPC_OPCODE_EFS2 0x200000000000ull
+
+/* Opcode is only supported by powerxx architecture. */
+#define PPC_OPCODE_POWERXX 0x400000000000ull
+
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
/* A macro to convert a VLE opcode to a VLE opcode segment. */
#define VLE_OP_TO_SEG(i) ((i) >> 1)
+
+/* A macro to extract the extended opcode from a SPE2 instruction. */
+#define SPE2_XOP(i) ((i) & 0x7ff)
+
+/* A macro to convert a SPE2 extended opcode to a SPE2 xopcode segment. */
+#define SPE2_XOP_TO_SEG(i) ((i) >> 7)
+
+/* A macro to extract the prefix word from an 8-byte PREFIX instruction. */
+#define PPC_GET_PREFIX(i) (((i) >> 32) & ((1LL << 32) - 1))
+
+/* A macro to extract the suffix word from an 8-byte PREFIX instruction. */
+#define PPC_GET_SUFFIX(i) ((i) & ((1LL << 32) - 1))
+
+/* A macro to determine whether insn I is an 8-byte prefix instruction. */
+#define PPC_PREFIX_P(i) (PPC_OP (PPC_GET_PREFIX (i)) == 0x1)
+
+/* A macro used to hash 8-byte PREFIX instructions. */
+#define PPC_PREFIX_SEG(i) (PPC_OP (i) >> 1)
+
\f
/* The operands table is an array of struct powerpc_operand. */
struct powerpc_operand
{
/* A bitmask of bits in the operand. */
- unsigned int bitm;
+ uint64_t bitm;
/* The shift operation to be applied to the operand. No shift
is made if this is zero. For positive values, the operand
If this field is not NULL, then simply call it with the
instruction and the operand value. It will return the new value
- of the instruction. If the ERRMSG argument is not NULL, then if
- the operand value is illegal, *ERRMSG will be set to a warning
- string (the operand will be inserted in any case). If the
- operand value is legal, *ERRMSG will be unchanged (most operands
- can accept any value). */
- unsigned long (*insert)
- (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);
+ of the instruction. If the operand value is illegal, *ERRMSG
+ will be set to a warning string (the operand will be inserted in
+ any case). If the operand value is legal, *ERRMSG will be
+ unchanged (most operands can accept any value). */
+ uint64_t (*insert)
+ (uint64_t instruction, int64_t op, ppc_cpu_t dialect, const char **errmsg);
/* Extraction function. This is used by the disassembler. To
extract this operand type from an instruction, check this field.
is the result).
If this field is not NULL, then simply call it with the
- instruction value. It will return the value of the operand. If
- the INVALID argument is not NULL, *INVALID will be set to
- non-zero if this operand type can not actually be extracted from
- this operand (i.e., the instruction does not match). If the
- operand is valid, *INVALID will not be changed. */
- long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid);
+ instruction value. It will return the value of the operand.
+ *INVALID will be set to one by the extraction function if this
+ operand type can not be extracted from this operand (i.e., the
+ instruction does not match). If the operand is valid, *INVALID
+ will not be changed. *INVALID will always be non-negative when
+ used to extract a field from an instruction.
+
+ The extraction function is also called by both the assembler and
+ disassembler if an operand is optional, in which case the
+ function should return the default value of the operand.
+ *INVALID is negative in this case, and is the negative count of
+ omitted optional operands up to and including this operand. */
+ int64_t (*extract) (uint64_t instruction, ppc_cpu_t dialect, int *invalid);
/* One bit syntax flags. */
unsigned long flags;
#define PPC_OPERAND_CR_BIT (0x20)
/* This is a CR FIELD that does not use symbolic names (unless
- -mregnames is in effect). */
+ -mregnames is in effect). If both PPC_OPERAND_CR_BIT and
+ PPC_OPERAND_CR_REG are set then treat the field as per
+ PPC_OPERAND_CR_BIT for assembly, but as if neither of these
+ bits are set for disassembly. */
#define PPC_OPERAND_CR_REG (0x40)
/* This operand names a special purpose register. */
/* Valid range of operand is 0..n rather than 0..n-1. */
#define PPC_OPERAND_PLUS1 (0x20000)
-/* This operand does not actually exist in the assembler input. This
- is used to support extended mnemonics such as mr, for which two
- operands fields are identical. The assembler should call the
- insert function with any op value. The disassembler should call
- the extract function, ignore the return value, and check the value
- placed in the valid argument. */
-#define PPC_OPERAND_FAKE (0x40000)
-
/* This operand is optional, and is zero if omitted. This is used for
example, in the optional BF field in the comparison instructions. The
assembler must count the number of operands remaining on the line,
out regardless of the PPC_OPERAND_OPTIONAL field. */
#define PPC_OPERAND_NEXT (0x100000)
-/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
- is omitted, then the value it should use for the operand is stored
- in the SHIFT field of the immediatly following operand field. */
-#define PPC_OPERAND_OPTIONAL_VALUE (0x200000)
-
/* This flag is only used with PPC_OPERAND_OPTIONAL. The operand is
only optional when generating 32-bit code. */
#define PPC_OPERAND_OPTIONAL32 (0x400000)
extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
-static inline long
-ppc_optional_operand_value (const struct powerpc_operand *operand)
+static inline int64_t
+ppc_optional_operand_value (const struct powerpc_operand *operand,
+ uint64_t insn,
+ ppc_cpu_t dialect,
+ int num_optional)
{
- if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0)
- return (operand+1)->shift;
+ if (operand->extract)
+ return (*operand->extract) (insn, dialect, &num_optional);
return 0;
}
/* PowerPC VLE insns. */
+#define E_OPCODE_MASK 0xfc00f800
+
/* Form I16L, uses 16A relocs. */
#define E_OR2I_INSN 0x7000C000
#define E_AND2I_DOT_INSN 0x7000C800
#define E_CMPH16I_INSN 0x7000B000
#define E_CMPHL16I_INSN 0x7000B800
+#define E_LI_INSN 0x70000000
+#define E_LI_MASK 0xfc008000
+
#ifdef __cplusplus
}
#endif
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