New Cell SPU port.

[thirdparty/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index e87e62a760f1a17614b3fa6e4154d277d314714a..016292ef70776b2e07e08198e478ad5cf6a2f0b3 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,84 @@
+2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
+           Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
+           Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
+           Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
+           Alan Modra  <amodra@bigpond.net.au>
+
+       * spu-dis.c: New file.
+       * spu-opc.c: New file.
+       * configure.in: Add SPU support.
+       * disassemble.c: Likewise.
+       * Makefile.am: Likewise.  Run "make dep-am".
+       * Makefile.in: Regenerate.
+       * configure: Regenerate.
+       * po/POTFILES.in: Regenerate.
+
+2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
+
+       * ppc-opc.c (CELL): New define.
+       (powerpc_opcodes): Enable hrfid for Cell.  Add ldbrx and stdbrx,
+       cell specific instructions.  Add {st,l}x{r,l}{,l} cell specific
+       VMX instructions.
+       * ppc-dis.c (powerpc_dialect): Handle cell.
+
+2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
+
+       * i386-dis.c (dis386): Add support for the change in POPCNT opcode in 
+       amdfam10 architecture.
+       (PREGRP37): NEW.
+       (print_insn): Disallow REP prefix for POPCNT.
+        
+2006-10-20  Andrew Stubbs  <andrew.stubbs@st.com>
+
+       * sh-dis.c (print_insn_sh): Remove 0x from output to prevent GDB
+       duplicating it.
+
+2006-10-18  Dave Brolley  <brolley@redhat.com>
+
+       * configure.in (BFD_MACHINES): Add cgen-bitset.lo for bfd_sh_arch.
+       * configure: Regenerated.
+
+2006-09-29  Alan Modra  <amodra@bigpond.net.au>
+
+       * po/POTFILES.in: Regenerate.
+
+2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
+            Joseph Myers  <joseph@codesourcery.com>
+            Ian Lance Taylor  <ian@wasabisystems.com>
+            Ben Elliston  <bje@wasabisystems.com>
+
+       * arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
+       only be used with the default multiply-add operation, so if N is
+       set, don't bother printing X.  Add new iwmmxt instructions.
+       (IWMMXT_INSN_COUNT): Update.
+       (iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
+       with a 'c' suffix.
+       (print_insn_coprocessor): Check for iWMMXt2.  Handle format
+       specifiers 'r', 'i'.
+
+2006-09-24  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
+
+       PR binutils/3100
+       * i386-dis.c (prefix_user_table): Fix the second operand of
+       maskmovdqu instruction to allow only %xmm register instead of
+       both %xmm register and memory.
+
+2006-09-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR binutils/3235
+       * i386-dis.c (OP_OFF64): Get 32bit offset if there is an
+       address size prefix.
+
+2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
+
+       * score-dis.c: New file.
+       * score-opc.h: New file.
+       * Makefile.am: Add Score files.
+       * Makefile.in: Regenerate.
+       * configure.in: Add support for Score target.
+       * configure: Regenerate.
+       * disassemble.c: Add support for Score target.
+
 2006-09-16  Nick Clifton  <nickc@redhat.com>
            Pedro Alves  <pedro_alves@portugalmail.pt>
 
@@ -19,6 +100,7 @@
 
 2006-08-04  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 
+       PR binutils/3000
        * i386-dis.c (MXC,EMC): Define.
        (OP_MXC): New function to handle cvt* (convert instructions) between
        %xmm and %mm register correctly.
@@ -67,7 +149,6 @@
        prefix for non-string instructions.
        (print_insn): Ditto.
 
-
 2006-07-05  Julian Brown  <julian@codesourcery.com>
 
        * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.