-2020-08-28 Alan Modra <amodra@gmail.com>
-
- PR 26449
- PR 26450
- * cgen-ibld.in (insert_1): Use 1UL in forming mask.
- (extract_normal): Likewise.
- (insert_normal): Likewise, and move past zero length test.
- (put_insn_int_value): Handle mask for zero length, use 1UL.
- * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
- * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
- * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
- * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
-
-2020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
-
- * csky-dis.c (CSKY_DEFAULT_ISA): Define.
- (csky_dis_info): Add member isa.
- (csky_find_inst_info): Skip instructions that do not belong to
- current CPU.
- (csky_get_disassembler): Get infomation from attribute section.
- (print_insn_csky): Set defualt ISA flag.
- * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
- * csky-opc.h (struct csky_opcode): Change isa_flag16 and
- isa_flag32'type to unsigned 64 bits.
-
-2020-08-26 Jose E. Marchesi <jemarch@gnu.org>
-
- * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
-
-2020-08-26 David Faust <david.faust@oracle.com>
-
- * bpf-desc.c: Regenerate.
- * bpf-desc.h: Likewise.
- * bpf-opc.c: Likewise.
- * bpf-opc.h: Likewise.
- * disassemble.c (disassemble_init_for_target): Set bits for xBPF
- ISA when appropriate.
-
-2020-08-25 Alan Modra <amodra@gmail.com>
-
- PR 26504
- * vax-dis.c (parse_disassembler_options): Always add at least one
- to entry_addr_total_slots.
-
-2020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
-
- * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
- in other CPUs to speed up disassembling.
- * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
- Change plsli.u16 to plsli.16, change sync's operand format.
-
-2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
-
- * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
-
-2020-08-21 Nick Clifton <nickc@redhat.com>
-
- * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
- symbols.
-
-2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
-
- * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
-
-2020-08-19 Alan Modra <amodra@gmail.com>
-
- * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
- vcmpuq and xvtlsbb.
-
-2020-08-18 Peter Bergner <bergner@linux.ibm.com>
-
- * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
- <xvcvbf16spn>: ...to this.
-
-2020-08-12 Alex Coplan <alex.coplan@arm.com>
-
- * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
-
-2020-08-12 Nick Clifton <nickc@redhat.com>
-
- * po/sr.po: Updated Serbian translation.
-
-2020-08-11 Alan Modra <amodra@gmail.com>
-
- * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
-
-2020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
-
- * aarch64-opc.c (aarch64_print_operand):
- (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
- (aarch64_sys_reg_supported_p): Function removed.
- (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
- (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
- into this function.
-
-2020-08-10 Alan Modra <amodra@gmail.com>
-
- * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
- instructions.
-
-2020-08-10 Alan Modra <amodra@gmail.com>
-
- * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
- Enable icbt for power5, miso for power8.
-
-2020-08-10 Alan Modra <amodra@gmail.com>
-
- * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
- mtvsrd, and similarly for mfvsrd.
-
-2020-08-04 Christian Groessler <chris@groessler.org>
- Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
-
- * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
- opcodes (special "out" to absolute address).
- * z8k-opc.h: Regenerate.
-
-2020-07-30 H.J. Lu <hongjiu.lu@intel.com>
-
- PR gas/26305
- * i386-opc.h (Prefix_Disp8): New.
- (Prefix_Disp16): Likewise.
- (Prefix_Disp32): Likewise.
- (Prefix_Load): Likewise.
- (Prefix_Store): Likewise.
- (Prefix_VEX): Likewise.
- (Prefix_VEX3): Likewise.
- (Prefix_EVEX): Likewise.
- (Prefix_REX): Likewise.
- (Prefix_NoOptimize): Likewise.
- * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
- * i386-tbl.h: Regenerated.
-
-2020-07-29 Andreas Arnez <arnez@linux.ibm.com>
-
- * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
- default case with abort() instead of printing an error message and
- continuing, to avoid a maybe-uninitialized warning.
-
-2020-07-24 Nick Clifton <nickc@redhat.com>
-
- * po/de.po: Updated German translation.
-
-2020-07-21 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (OP_E_memory): Revert previous change.
-
-2020-07-15 H.J. Lu <hongjiu.lu@intel.com>
-
- PR gas/26237
- * i386-dis.c (OP_E_memory): Don't display eiz with no scale
- without base nor index registers.
-
-2020-07-15 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (putop): Move 'V' and 'W' handling.
-
-2020-07-15 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (dis386): Adjust 'V' description. Use P-based
- construct for push/pop of register.
- (putop): Honor cond when handling 'P'. Drop handling of plain
- 'V'.
-
-2020-07-15 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
- description. Drop '&' description. Use P for push of immediate,
- pushf/popf, enter, and leave. Use %LP for lret/retf.
- (dis386_twobyte): Use P for push/pop of fs/gs.
- (reg_table): Use P for push/pop. Use @ for near call/jmp.
- (x86_64_table): Use P for far call/jmp.
- (putop): Drop handling of 'U' and '&'. Move and adjust handling
- of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
- labels.
- (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
- and dqw_mode (unconditional).
-
-2020-07-14 H.J. Lu <hongjiu.lu@intel.com>
-
- PR gas/26237
- * i386-dis.c (OP_E_memory): Without base nor index registers,
- 32-bit displacement to 64 bits.
-
-2020-07-14 Claudiu Zissulescu <claziss@gmail.com>
-
- * arc-dis.c (print_insn_arc): Detect and emit a warning when a
- faulty double register pair is detected.
-
-2020-07-14 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
-
-2020-07-14 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (OP_R, Rm): Delete.
- (MOD_0F24, MOD_0F26): Rename to ...
- (X86_64_0F24, X86_64_0F26): ... respectively.
- (dis386): Update 'L' and 'Z' comments.
- (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
- table references.
- (mod_table): Move opcode 0F24 and 0F26 entries ...
- (x86_64_table): ... here.
- (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
- 'Z' case block.
-
-2020-07-14 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (Rd, Rdq, MaskR): Delete.
- (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
- MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
- MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
- MOD_EVEX_0F387C): New enumerators.
- (reg_table): Use Edq for rdssp.
- (prefix_table): Use Edq for incssp.
- (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
- kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
- ktest*, and kshift*. Use Edq / MaskE for kmov*.
- * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
- * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
- 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
- * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
- 0F3828_P_1 and 0F3838_P_1.
- * i386-dis-evex-w.h: Reference mod_table[] for opcodes
- 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
-
-2020-07-14 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
- PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
- PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
- PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
- PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
- PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
- (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
- VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
- VEX_LEN_0F38F3_R_3_P_0): Rename to ...
- (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
- VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
- (reg_table, prefix_table, three_byte_table, vex_table,
- vex_len_table, mod_table, rm_table): Replace / remove respective
- entries.
- (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
- of PREFIX_DATA in used_prefixes.
-
-2020-07-14 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
- MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
- MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
- MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
- (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
- MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
- (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
- VEX_W_0F3A33_L_0): Delete.
- (dis386): Adjust "BW" description.
- (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
- 0F3A31, 0F3A32, and 0F3A33.
- (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
- entries.
- (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
- entries.
-
-2020-07-14 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
- PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
- PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
- PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
- PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
- PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
- PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
- PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
- PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
- PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
- PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
- PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
- PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
- PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
- PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
- PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
- PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
- PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
- PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
- PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
- PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
- PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
- PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
- PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
- PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
- PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
- PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
- PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
- PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
- PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
- PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
- PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
- PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
- PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
- PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
- PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
- PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
- PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
- PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
- PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
- PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
- PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
- PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
- PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
- PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
- PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
- PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
- PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
- PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
- PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
- PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
- PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
- PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
- PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
- PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
- PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
- PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
- PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
- PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
- PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
- PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
- PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
- PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
- PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
- PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
- PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
- PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
- PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
- PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
- PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
- PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
- PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
- PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
- PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
- PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
- PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
- PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
- PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
- PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
- PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
- PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
- PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
- PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
- PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
- PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
- PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
- PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
- PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
- PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
- PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
- PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
- PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
- PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
- PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
- PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
- PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
- PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
- PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
- PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
- PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
- PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
- PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
- PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
- PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
- PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
- PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
- PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
- PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
- PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
- PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
- PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
- PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
- PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
- PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
- PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
- PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
- PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
- PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
- PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
- PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
- PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
- PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
- PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
- PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
- PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
- PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
- PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
- PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
- PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
- PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
- PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
- PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
- PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
- PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
- PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
- PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
- PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
- PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
- PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
- PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
- PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
- PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
- PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
- PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
- PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
- PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
- PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
- PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
- PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
- PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
- PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
- PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
- PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
- PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
- PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
- PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
- PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
- (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
- MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
- MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
- MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
- MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
- MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
- MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
- MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
- MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
- MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
- MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
- MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
- MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
- MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
- MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
- VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
- VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
- VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
- VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
- VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
- VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
- VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
- VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
- VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
- VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
- VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
- VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
- VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
- EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
- EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
- EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
- EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
- EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
- EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
- EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
- EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
- EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
- EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
- EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
- EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
- EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
- EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
- EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
- EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
- EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
- EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
- EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
- EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
- EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
- EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
- EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
- EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
- EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
- EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
- EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
- VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
- VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
- VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
- VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
- VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
- VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
- VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
- VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
- VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
- VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
- VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
- VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
- VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
- VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
- VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
- VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
- VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
- VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
- EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
- EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
- EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
- EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
- EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
- EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
- EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
- EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
- EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
- EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
- EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
- EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
- EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
- EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
- EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
- EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
- EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
- EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
- EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
- EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
- EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
- EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
- EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
- EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
- EVEX_W_0F3A72_P_2): Rename to ...
- (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
- MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
- MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
- MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
- MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
- MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
- MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
- MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
- MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
- MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
- MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
- VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
- VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
- VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
- VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
- VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
- VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
- VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
- VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
- VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
- EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
- EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
- EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
- EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
- EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
- EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
- EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
- EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
- EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
- EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
- EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
- EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
- EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
- EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
- EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
- EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
- EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
- EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
- EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
- EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
- EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
- EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
- EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
- EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
- EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
- VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
- VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
- VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
- VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
- VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
- VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
- VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
- VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
- VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
- VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
- VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
- VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
- VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
- EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
- EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
- EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
- EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
- EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
- EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
- EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
- EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
- EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
- EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
- EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
- EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
- EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
- EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
- respectively.
- (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
- vex_w_table, mod_table): Replace / remove respective entries.
- (print_insn): Move up dp->prefix_requirement handling. Handle
- PREFIX_DATA.
- * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
- i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
- Replace / remove respective entries.
-
-2020-07-14 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
- PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
- (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
- vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
- Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
- the latter two.
- * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
- 0F2C, 0F2D, 0F2E, and 0F2F.
- * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
- 0F2F table entries.
-
-2020-07-14 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (OP_VexR, VexScalarR): New.
- (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
- XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
- need_vex_reg): Delete.
- (prefix_table): Replace VexScalar by VexScalarR and
- XMVexScalar by XMScalar for vmovss and vmovsd. Replace
- EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
- (vex_len_table): Replace EXqVexScalarS by EXqS.
- (get_valid_dis386): Don't set need_vex_reg.
- (print_insn): Don't initialize need_vex_reg.
- (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
- q_scalar_swap_mode cases.
- (OP_EX): Don't check for d_scalar_swap_mode and
- q_scalar_swap_mode.
- (OP_VEX): Done check need_vex_reg.
- * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
- XMVexScalar by XMScalar for vmovss and vmovsd. Replace
- EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
-
-2020-07-14 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
- (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
- VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
- VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
- (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
- VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
- VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
- VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
- (vex_table): Replace Vex128 by Vex.
- (vex_len_table): Likewise. Adjust referenced enum names.
- (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
- referenced enum names.
- (OP_VEX): Drop vex128_mode and vex256_mode cases.
- * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
-
-2020-07-14 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (dis386): "LW" description now applies to "DQ".
- (putop): Handle "DQ". Don't handle "LW" anymore.
- (prefix_table, mod_table): Replace %LW by %DQ.
- * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
-
-2020-07-14 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
- dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
- d_scalar_swap_mode case handling. Move shift adjsutment into
- the case its applicable to.
-
-2020-07-14 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
- (EXbScalar, EXwScalar): Fold to ...
- (EXbwUnit): ... this.
- (b_scalar_mode, w_scalar_mode): Fold to ...
- (bw_unit_mode): ... this.
- (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
- w_scalar_mode handling by bw_unit_mode one.
- * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
- ...
- * i386-dis-evex-prefix.h: ... here.
-
-2020-07-14 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (PCMPESTR_Fixup): Delete.
- (dis386): Adjust "LQ" description.
- (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
- cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
- PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
- vpcmpestrm, and vpcmpestri.
- (putop): Honor "cond" when handling LQ.
- * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
- vcvtsi2ss and vcvtusi2ss.
- * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
- vcvtsi2sd and vcvtusi2sd.
-
-2020-07-14 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (VCMP_Fixup, VCMP): Delete.
- (simd_cmp_op): Add const.
- (vex_cmp_op): Move up and drop initial 8 entries. Add const.
- (CMP_Fixup): Handle VEX case.
- (prefix_table): Replace VCMP by CMP.
- * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
-
-2020-07-14 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (MOVBE_Fixup): Delete.
- (Mv): Define.
- (prefix_table): Use Mv for movbe entries.
-
-2020-07-14 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (CRC32_Fixup): Delete.
- (prefix_table): Use Eb/Ev for crc32 entries.
-
-2020-07-14 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
- Conditionalize invocations of "USED_REX (0)".
-
-2020-07-14 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
- CH, DH, BH, AX, DX): Delete.
- (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
- eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
- dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
-
-2020-07-10 Lili Cui <lili.cui@intel.com>
-
- * i386-dis.c (TMM): New.
- (EXtmm): Likewise.
- (VexTmm): Likewise.
- (MVexSIBMEM): Likewise.
- (tmm_mode): Likewise.
- (vex_sibmem_mode): Likewise.
- (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
- (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
- (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
- (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
- (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
- (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
- (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
- (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
- (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
- (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
- (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
- (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
- (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
- (PREFIX_VEX_0F3849_X86_64): Likewise.
- (PREFIX_VEX_0F384B_X86_64): Likewise.
- (PREFIX_VEX_0F385C_X86_64): Likewise.
- (PREFIX_VEX_0F385E_X86_64): Likewise.
- (X86_64_VEX_0F3849): Likewise.
- (X86_64_VEX_0F384B): Likewise.
- (X86_64_VEX_0F385C): Likewise.
- (X86_64_VEX_0F385E): Likewise.
- (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
- (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
- (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
- (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
- (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
- (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
- (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
- (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
- (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
- (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
- (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
- (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
- (VEX_W_0F3849_X86_64_P_0): Likewise.
- (VEX_W_0F3849_X86_64_P_2): Likewise.
- (VEX_W_0F3849_X86_64_P_3): Likewise.
- (VEX_W_0F384B_X86_64_P_1): Likewise.
- (VEX_W_0F384B_X86_64_P_2): Likewise.
- (VEX_W_0F384B_X86_64_P_3): Likewise.
- (VEX_W_0F385C_X86_64_P_1): Likewise.
- (VEX_W_0F385E_X86_64_P_0): Likewise.
- (VEX_W_0F385E_X86_64_P_1): Likewise.
- (VEX_W_0F385E_X86_64_P_2): Likewise.
- (VEX_W_0F385E_X86_64_P_3): Likewise.
- (names_tmm): Likewise.
- (att_names_tmm): Likewise.
- (intel_operand_size): Handle void_mode.
- (OP_XMM): Handle tmm_mode.
- (OP_EX): Likewise.
- (OP_VEX): Likewise.
- * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
- CpuAMX_BF16 and CpuAMX_TILE.
- (operand_type_shorthands): Add RegTMM.
- (operand_type_init): Likewise.
- (operand_types): Add Tmmword.
- (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
- (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
- * i386-opc.h (CpuAMX_INT8): New.
- (CpuAMX_BF16): Likewise.
- (CpuAMX_TILE): Likewise.
- (SIBMEM): Likewise.
- (Tmmword): Likewise.
- (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
- (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
- (i386_operand_type): Add tmmword.
- * i386-opc.tbl: Add AMX instructions.
- * i386-reg.tbl: Add AMX registers.
- * i386-init.h: Regenerated.
- * i386-tbl.h: Likewise.
-
-2020-07-08 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
- (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
- Rename to ...
- (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
- REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
- respectively.
- (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
- VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
- VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
- VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
- VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
- VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
- VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
- VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
- VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
- VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
- VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
- VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
- VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
- VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
- VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
- VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
- VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
- VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
- VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
- VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
- VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
- VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
- VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
- VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
- VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
- VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
- VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
- VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
- VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
- VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
- VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
- VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
- VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
- VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
- VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
- VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
- (reg_table): Re-order XOP entries. Adjust their operands.
- (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
- 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
- 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
- 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
- 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
- 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
- entries by references ...
- (vex_len_table): ... to resepctive new entries here. For several
- new and existing entries reference ...
- (vex_w_table): ... new entries here.
- (mod_table): New MOD_VEX_0FXOP_09_12 entry.
-
-2020-07-08 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (XMVexScalarI4): Define.
- (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
- VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
- VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
- (vex_len_table): Move scalar FMA4 entries ...
- (prefix_table): ... here.
- (OP_REG_VexI4): Handle scalar_mode.
- * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
- * i386-tbl.h: Re-generate.
-
-2020-07-08 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
- Vex_2src_2): Delete.
- (OP_VexW, VexW): New.
- (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
- for shifts and rotates by register.
-
-2020-07-08 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
- VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
- OP_EX_VexReg): Delete.
- (OP_VexI4, VexI4): New.
- (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
- (prefix_table): ... here.
- (print_insn): Drop setting of vex_w_done.
-
-2020-07-08 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
- (prefix_table, vex_len_table): Replace operands for FMA4 insns.
- (xop_table): Replace operands of 4-operand insns.
- (OP_REG_VexI4): Move VEX.W based operand swaping here.
-
-2020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
-
- * arc-opc.c (insert_rbd): New function.
- (RBD): Define.
- (RBDdup): Likewise.
- * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
- instructions.
-
-2020-07-07 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
- EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
- EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
- EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
- Delete.
- (putop): Handle "BW".
- * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
- 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
- and 0F3A3F ...
- * i386-dis-evex-prefix.h: ... here.
-
-2020-07-06 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
- (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
- VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
- VEX_W_0FXOP_09_83): New enumerators.
- (xop_table): Reference the above.
- (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
- (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
- VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
- (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
-
-2020-07-06 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (EVEX_W_0F3838_P_1,
- EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
- EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
- EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
- EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
- EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
- (putop): Centralize management of last[]. Delete SAVE_LAST.
- * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
- 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
- 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
- * i386-dis-evex-prefix.h: here.
-
-2020-07-06 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
- MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
- MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
- MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
- enumerators.
- (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
- EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
- EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
- EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
- (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
- EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
- EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
- EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
- these, respectively.
- * i386-dis-evex-len.h: Adjust comments.
- * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
- MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
- MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
- MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
- MOD_EVEX_0F385B_P_2_W_1 table entries.
- * i386-dis-evex-w.h: Reference mod_table[] for
- EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
- EVEX_W_0F385B_P_2.
-
-2020-07-06 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
- vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
- EXymm.
- (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
- Likewise. Mark 256-bit entries invalid.
-
-2020-07-06 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
- PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
- PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
- PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
- PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
- PREFIX_EVEX_0F382B): Delete.
- (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
- EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
- EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
- EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
- EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
- to ...
- (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
- EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
- EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
- EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
- respectively.
- * i386-dis-evex.h (evex_table): Reference VEX_W table entries
- for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
- 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
- * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
- PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
- PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
- PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
- PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
- PREFIX_EVEX_0F382B): Remove table entries.
- * i386-dis-evex-w.h: Reference VEX table entries for opcodes
- 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
- 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
-
-2020-07-06 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
- EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
- enumerators.
- * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
- EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
- EVEX_LEN_0F3A01_P_2_W_1 table entries.
- * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
- entries.
-
-2020-07-06 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
- EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
- EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
- EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
- * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
- EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
- EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
- EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
- * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
- entries.
-
-2020-07-06 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
- (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
- (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
- respectively.
- (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
- entries.
- * i386-dis-evex.h (evex_table): Reference VEX table entry for
- opcode 0F3A1D.
- * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
- entry.
- * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
-
-2020-07-06 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
- PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
- PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
- PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
- PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
- PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
- PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
- PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
- PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
- PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
- PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
- PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
- PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
- PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
- PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
- PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
- PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
- PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
- PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
- PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
- PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
- PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
- PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
- PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
- PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
- PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
- PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
- EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
- EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
- EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
- (prefix_table): Add EXxEVexR to FMA table entries.
- (OP_Rounding): Move abort() invocation.
- * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
- 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
- 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
- 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
- 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
- 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
- 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
- 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
- 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
- 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
- 0F3ACE, 0F3ACF.
- * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
- PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
- PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
- PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
- PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
- PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
- PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
- PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
- PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
- PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
- PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
- PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
- PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
- PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
- PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
- PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
- PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
- PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
- PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
- PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
- PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
- PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
- PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
- PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
- PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
- PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
- PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
- Delete table entries.
- * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
- EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
- EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
- Likewise.
-
-2020-07-06 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (EXqScalarS): Delete.
- (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
- * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
-
-2020-07-06 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (safe-ctype.h): Include.
- (EXdScalar, EXqScalar): Delete.
- (d_scalar_mode, q_scalar_mode): Delete.
- (prefix_table, vex_len_table): Use EXxmm_md in place of
- EXdScalar and EXxmm_mq in place of EXqScalar.
- (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
- d_scalar_mode and q_scalar_mode.
- * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
- (vmovsd): Use EXxmm_mq.
-
-2020-07-06 Yuri Chornoivan <yurchor@ukr.net>
-
- PR 26204
- * arc-dis.c: Fix spelling mistake.
- * po/opcodes.pot: Regenerate.
-
-2020-07-06 Nick Clifton <nickc@redhat.com>
-
- * po/pt_BR.po: Updated Brazilian Portugugese translation.
- * po/uk.po: Updated Ukranian translation.
-
-2020-07-04 Nick Clifton <nickc@redhat.com>
-
- * configure: Regenerate.
- * po/opcodes.pot: Regenerate.
-
-2020-07-04 Nick Clifton <nickc@redhat.com>
-
- Binutils 2.35 branch created.
-
-2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-gen.c (opcode_modifiers): Add VexSwapSources.
- * i386-opc.h (VexSwapSources): New.
- (i386_opcode_modifier): Add vexswapsources.
- * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
- with two source operands swapped.
- * i386-tbl.h: Regenerated.
-
-2020-06-30 Nelson Chu <nelson.chu@sifive.com>
-
- * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
- unprivileged CSR can also be initialized.
-
-2020-06-29 Alan Modra <amodra@gmail.com>
-
- * arm-dis.c: Use C style comments.
- * cr16-opc.c: Likewise.
- * ft32-dis.c: Likewise.
- * moxie-opc.c: Likewise.
- * tic54x-dis.c: Likewise.
- * s12z-opc.c: Remove useless comment.
- * xgate-dis.c: Likewise.
-
-2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-opc.tbl: Add a blank line.
-
-2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
- (VecSIB128): Renamed to ...
- (VECSIB128): This.
- (VecSIB256): Renamed to ...
- (VECSIB256): This.
- (VecSIB512): Renamed to ...
- (VECSIB512): This.
- (VecSIB): Renamed to ...
- (SIB): This.
- (i386_opcode_modifier): Replace vecsib with sib.
- * i386-opc.tbl (VecSIB128): New.
- (VecSIB256): Likewise.
- (VecSIB512): Likewise.
- Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
- and VecSIB512, respectively.
-
-2020-06-26 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c: Adjust description of I macro.
- (x86_64_table): Drop use of I.
- (float_mem): Replace use of I.
- (putop): Remove handling of I. Adjust setting/clearing of "alt".
-
-2020-06-26 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c: (print_insn): Avoid straight assignment to
- priv.orig_sizeflag when processing -M sub-options.
-
-2020-06-25 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c: Adjust description of J macro.
- (dis386, x86_64_table, mod_table): Replace J.
- (putop): Remove handling of J.
-
-2020-06-25 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
-
-2020-06-25 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c: Adjust description of "LQ" macro.
- (dis386_twobyte): Use LQ for sysret.
- (putop): Adjust handling of LQ.
-
-2020-06-22 Nelson Chu <nelson.chu@sifive.com>
-
- * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
- * riscv-dis.c: Include elfxx-riscv.h.
-
-2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (prefix_table): Revert the last vmgexit change.
-
-2020-06-17 Lili Cui <lili.cui@intel.com>
-
- * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
-
-2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
-
- PR gas/26115
- * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
- * i386-opc.tbl: Likewise.
- * i386-tbl.h: Regenerated.
-
-2020-06-12 Nelson Chu <nelson.chu@sifive.com>
-
- * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
-
-2020-06-11 Alex Coplan <alex.coplan@arm.com>
-
- * aarch64-opc.c (SYSREG): New macro for describing system registers.
- (SR_CORE): Likewise.
- (SR_FEAT): Likewise.
- (SR_RNG): Likewise.
- (SR_V8_1): Likewise.
- (SR_V8_2): Likewise.
- (SR_V8_3): Likewise.
- (SR_V8_4): Likewise.
- (SR_PAN): Likewise.
- (SR_RAS): Likewise.
- (SR_SSBS): Likewise.
- (SR_SVE): Likewise.
- (SR_ID_PFR2): Likewise.
- (SR_PROFILE): Likewise.
- (SR_MEMTAG): Likewise.
- (SR_SCXTNUM): Likewise.
- (aarch64_sys_regs): Refactor to store feature information in the table.
- (aarch64_sys_reg_supported_p): Collapse logic for system registers
- that now describe their own features.
- (aarch64_pstatefield_supported_p): Likewise.
-
-2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (prefix_table): Fix a typo in comments.
-
-2020-06-09 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (rex_ignored): Delete.
- (ckprefix): Drop rex_ignored initialization.
- (get_valid_dis386): Drop setting of rex_ignored.
- (print_insn): Drop checking of rex_ignored. Don't record data
- size prefix as used with VEX-and-alike encodings.
-
-2020-06-09 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
- MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
- (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
- (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
- (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
- VEX_0F12, and VEX_0F16.
- (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
- VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
- (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
- from movlps and movhlps. New MOD_0F12_PREFIX_2,
- MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
- MOD_VEX_0F16_PREFIX_2 entries.
-
-2020-06-09 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
- MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
- (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
- PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
- PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
- PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
- EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
- EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
- EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
- EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
- EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
- EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
- EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
- EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
- EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
- EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
- EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
- EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
- EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
- EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
- EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
- EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
- EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
- EVEX_W_0FC6_P_2): Delete.
- (print_insn): Add EVEX.W vs embedded prefix consistency check
- to prefix validation.
- * i386-dis-evex.h (evex_table): Don't further descend for
- vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
- and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
- and 0F2B.
- * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
- * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
- vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
- vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
- 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
- Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
- PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
- PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
- PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
- * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
- EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
- EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
- EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
- EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
- EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
- EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
- EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
- EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
- EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
- EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
- EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
- EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
- EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
- EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
- EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
- EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
- EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
-
-2020-06-09 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
- vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
- (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
- vmovmskpX.
- (print_insn): Drop pointless check against bad_opcode. Split
- prefix validation into legacy and VEX-and-alike parts.
- (putop): Re-work 'X' macro handling.
-
-2020-06-09 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (MOD_0F51): Rename to ...
- (MOD_0F50): ... this.
-
-2020-06-08 Alex Coplan <alex.coplan@arm.com>
-
- * arm-dis.c (arm_opcodes): Add dfb.
- (thumb32_opcodes): Add dfb.
-
-2020-06-08 Jan Beulich <jbeulich@suse.com>
-
- * i386-opc.h (reg_entry): Const-qualify reg_name field.
-
-2020-06-06 Alan Modra <amodra@gmail.com>
-
- * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
-
-2020-06-05 Alan Modra <amodra@gmail.com>
-
- * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
- size is large enough.
-
-2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- * disassemble.c (disassemble_init_for_target): Set endian_code for
- bpf targets.
- * bpf-desc.c: Regenerate.
- * bpf-opc.c: Likewise.
- * bpf-dis.c: Likewise.
-
-2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
- (cgen_put_insn_value): Likewise.
- (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
- * cgen-dis.in (print_insn): Likewise.
- * cgen-ibld.in (insert_1): Likewise.
- (insert_1): Likewise.
- (insert_insn_normal): Likewise.
- (extract_1): Likewise.
- * bpf-dis.c: Regenerate.
- * bpf-ibld.c: Likewise.
- * bpf-ibld.c: Likewise.
- * cgen-dis.in: Likewise.
- * cgen-ibld.in: Likewise.
- * cgen-opc.c: Likewise.
- * epiphany-dis.c: Likewise.
- * epiphany-ibld.c: Likewise.
- * fr30-dis.c: Likewise.
- * fr30-ibld.c: Likewise.
- * frv-dis.c: Likewise.
- * frv-ibld.c: Likewise.
- * ip2k-dis.c: Likewise.
- * ip2k-ibld.c: Likewise.
- * iq2000-dis.c: Likewise.
- * iq2000-ibld.c: Likewise.
- * lm32-dis.c: Likewise.
- * lm32-ibld.c: Likewise.
- * m32c-dis.c: Likewise.
- * m32c-ibld.c: Likewise.
- * m32r-dis.c: Likewise.
- * m32r-ibld.c: Likewise.
- * mep-dis.c: Likewise.
- * mep-ibld.c: Likewise.
- * mt-dis.c: Likewise.
- * mt-ibld.c: Likewise.
- * or1k-dis.c: Likewise.
- * or1k-ibld.c: Likewise.
- * xc16x-dis.c: Likewise.
- * xc16x-ibld.c: Likewise.
- * xstormy16-dis.c: Likewise.
- * xstormy16-ibld.c: Likewise.
-
-2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
-
- * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
- (print_insn_): Handle instruction endian.
- * bpf-dis.c: Regenerate.
- * bpf-desc.c: Regenerate.
- * epiphany-dis.c: Likewise.
- * epiphany-desc.c: Likewise.
- * fr30-dis.c: Likewise.
- * fr30-desc.c: Likewise.
- * frv-dis.c: Likewise.
- * frv-desc.c: Likewise.
- * ip2k-dis.c: Likewise.
- * ip2k-desc.c: Likewise.
- * iq2000-dis.c: Likewise.
- * iq2000-desc.c: Likewise.
- * lm32-dis.c: Likewise.
- * lm32-desc.c: Likewise.
- * m32c-dis.c: Likewise.
- * m32c-desc.c: Likewise.
- * m32r-dis.c: Likewise.
- * m32r-desc.c: Likewise.
- * mep-dis.c: Likewise.
- * mep-desc.c: Likewise.
- * mt-dis.c: Likewise.
- * mt-desc.c: Likewise.
- * or1k-dis.c: Likewise.
- * or1k-desc.c: Likewise.
- * xc16x-dis.c: Likewise.
- * xc16x-desc.c: Likewise.
- * xstormy16-dis.c: Likewise.
- * xstormy16-desc.c: Likewise.
-
-2020-06-03 Nick Clifton <nickc@redhat.com>
-
- * po/sr.po: Updated Serbian translation.
-
-2020-06-03 Nelson Chu <nelson.chu@sifive.com>
-
- * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
- (riscv_get_priv_spec_class): Likewise.
-
-2020-06-01 Alan Modra <amodra@gmail.com>
-
- * bpf-desc.c: Regenerate.
-
-2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
- David Faust <david.faust@oracle.com>
-
- * bpf-desc.c: Regenerate.
- * bpf-opc.h: Likewise.
- * bpf-opc.c: Likewise.
- * bpf-dis.c: Likewise.
-
-2020-05-28 Alan Modra <amodra@gmail.com>
-
- * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
- values.
-
-2020-05-28 Alan Modra <amodra@gmail.com>
-
- * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
- immediates.
- (print_insn_ns32k): Revert last change.
-
-2020-05-28 Nick Clifton <nickc@redhat.com>
-
- * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
- static.
-
-2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
-
- Fix extraction of signed constants in nios2 disassembler (again).
-
- * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
- extractions of signed fields.
-
-2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
-
- * s390-opc.txt: Relocate vector load/store instructions with
- additional alignment parameter and change architecture level
- constraint from z14 to z13.
-
-2020-05-21 Alan Modra <amodra@gmail.com>
-
- * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
- * sparc-dis.c: Likewise.
- * tic4x-dis.c: Likewise.
- * xtensa-dis.c: Likewise.
- * bpf-desc.c: Regenerate.
- * epiphany-desc.c: Regenerate.
- * fr30-desc.c: Regenerate.
- * frv-desc.c: Regenerate.
- * ip2k-desc.c: Regenerate.
- * iq2000-desc.c: Regenerate.
- * lm32-desc.c: Regenerate.
- * m32c-desc.c: Regenerate.
- * m32r-desc.c: Regenerate.
- * mep-asm.c: Regenerate.
- * mep-desc.c: Regenerate.
- * mt-desc.c: Regenerate.
- * or1k-desc.c: Regenerate.
- * xc16x-desc.c: Regenerate.
- * xstormy16-desc.c: Regenerate.
-
-2020-05-20 Nelson Chu <nelson.chu@sifive.com>
-
- * riscv-opc.c (riscv_ext_version_table): The table used to store
- all information about the supported spec and the corresponding ISA
- versions. Currently, only Zicsr is supported to verify the
- correctness of Z sub extension settings. Others will be supported
- in the future patches.
- (struct isa_spec_t, isa_specs): List for all supported ISA spec
- classes and the corresponding strings.
- (riscv_get_isa_spec_class): New function. Get the corresponding ISA
- spec class by giving a ISA spec string.
- * riscv-opc.c (struct priv_spec_t): New structure.
- (struct priv_spec_t priv_specs): List for all supported privilege spec
- classes and the corresponding strings.
- (riscv_get_priv_spec_class): New function. Get the corresponding
- privilege spec class by giving a spec string.
- (riscv_get_priv_spec_name): New function. Get the corresponding
- privilege spec string by giving a CSR version class.
- * riscv-dis.c: Updated since DECLARE_CSR is changed.
- * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
- according to the chosen version. Build a hash table riscv_csr_hash to
- store the valid CSR for the chosen pirv verison. Dump the direct
- CSR address rather than it's name if it is invalid.
- (parse_riscv_dis_option_without_args): New function. Parse the options
- without arguments.
- (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
- parse the options without arguments first, and then handle the options
- with arguments. Add the new option -Mpriv-spec, which has argument.
- * riscv-dis.c (print_riscv_disassembler_options): Add description
- about the new OBJDUMP option.
-
-2020-05-19 Peter Bergner <bergner@linux.ibm.com>
-
- * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
- WC values on POWER10 sync, dcbf and wait instructions.
- (insert_pl, extract_pl): New functions.
- (L2OPT, LS, WC): Use insert_ls and extract_ls.
- (LS3): New , 3-bit L for sync.
- (LS3, L3OPT): New, 3-bit L for sync and dcbf.
- (SC2, PL): New, 2-bit SC and PL for sync and wait.
- (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
- (XOPL3, XWCPL, XSYNCLS): New opcode macros.
- (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
- plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
- <wait>: Enable PL operand on POWER10.
- <dcbf>: Enable L3OPT operand on POWER10.
- <sync>: Enable SC2 operand on POWER10.
-
-2020-05-19 Stafford Horne <shorne@gmail.com>
-
- PR 25184
- * or1k-asm.c: Regenerate.
- * or1k-desc.c: Regenerate.
- * or1k-desc.h: Regenerate.
- * or1k-dis.c: Regenerate.
- * or1k-ibld.c: Regenerate.
- * or1k-opc.c: Regenerate.
- * or1k-opc.h: Regenerate.
- * or1k-opinst.c: Regenerate.
-
-2020-05-11 Alan Modra <amodra@gmail.com>
-
- * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
- xsmaxcqp, xsmincqp.
-
-2020-05-11 Alan Modra <amodra@gmail.com>
-
- * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
- stxvrbx, stxvrhx, stxvrwx, stxvrdx.
-
-2020-05-11 Alan Modra <amodra@gmail.com>
-
- * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
-
-2020-05-11 Alan Modra <amodra@gmail.com>
-
- * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
- vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
-
-2020-05-11 Peter Bergner <bergner@linux.ibm.com>
-
- * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
- mnemonics.
-
-2020-05-11 Alan Modra <amodra@gmail.com>
-
- * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
- (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
- vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
- (prefix_opcodes): Add xxeval.
-
-2020-05-11 Alan Modra <amodra@gmail.com>
-
- * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
- xxgenpcvwm, xxgenpcvdm.
-
-2020-05-11 Alan Modra <amodra@gmail.com>
-
- * ppc-opc.c (MP, VXVAM_MASK): Define.
- (VXVAPS_MASK): Use VXVA_MASK.
- (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
- vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
- vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
- vcntmbb, vcntmbh, vcntmbw, vcntmbd.
-
-2020-05-11 Alan Modra <amodra@gmail.com>
- Peter Bergner <bergner@linux.ibm.com>
-
- * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
- New functions.
- (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
- YMSK2, XA6a, XA6ap, XB6a entries.
- (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
- (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
- (PPCVSX4): Define.
- (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
- xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
- xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
- xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
- xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
- xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
- xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
- (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
- pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
- pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
- pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
- pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
- pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
- pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
-
-2020-05-11 Alan Modra <amodra@gmail.com>
-
- * ppc-opc.c (insert_imm32, extract_imm32): New functions.
- (insert_xts, extract_xts): New functions.
- (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
- (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
- (VXRC_MASK, VXSH_MASK): Define.
- (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
- vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
- vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
- vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
- vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
- (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
- xxblendvh, xxblendvw, xxblendvd, xxpermx.
-
-2020-05-11 Alan Modra <amodra@gmail.com>
-
- * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
- vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
- vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
- vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
- xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
-
-2020-05-11 Alan Modra <amodra@gmail.com>
-
- * ppc-opc.c (insert_xtp, extract_xtp): New functions.
- (XTP, DQXP, DQXP_MASK): Define.
- (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
- (prefix_opcodes): Add plxvp and pstxvp.
-
-2020-05-11 Alan Modra <amodra@gmail.com>
-
- * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
- vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
- vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
-
-2020-05-11 Peter Bergner <bergner@linux.ibm.com>
-
- * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
-
-2020-05-11 Peter Bergner <bergner@linux.ibm.com>
-
- * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
- (L1OPT): Define.
- (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
-
-2020-05-11 Peter Bergner <bergner@linux.ibm.com>
-
- * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
-
-2020-05-11 Alan Modra <amodra@gmail.com>
-
- * ppc-dis.c (powerpc_init_dialect): Default to "power10".
-
-2020-05-11 Alan Modra <amodra@gmail.com>
-
- * ppc-dis.c (ppc_opts): Add "power10" entry.
- (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
- * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
-
-2020-05-11 Nick Clifton <nickc@redhat.com>
-
- * po/fr.po: Updated French translation.
-
-2020-04-30 Alex Coplan <alex.coplan@arm.com>
-
- * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
- * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
- (operand_general_constraint_met_p): validate
- AARCH64_OPND_UNDEFINED.
- * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
- for FLD_imm16_2.
- * aarch64-asm-2.c: Regenerated.
- * aarch64-dis-2.c: Regenerated.
- * aarch64-opc-2.c: Regenerated.
-
-2020-04-29 Nick Clifton <nickc@redhat.com>
-
- PR 22699
- * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
- and SETRC insns.
-
-2020-04-29 Nick Clifton <nickc@redhat.com>
-
- * po/sv.po: Updated Swedish translation.
-
-2020-04-29 Nick Clifton <nickc@redhat.com>
-
- PR 22699
- * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
- IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
- * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
- IMM0_8U case.
-
-2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
-
- PR 25848
- * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
- cmpi only on m68020up and cpu32.
-
-2020-04-20 Sudakshina Das <sudi.das@arm.com>
-
- * aarch64-asm.c (aarch64_ins_none): New.
- * aarch64-asm.h (ins_none): New declaration.
- * aarch64-dis.c (aarch64_ext_none): New.
- * aarch64-dis.h (ext_none): New declaration.
- * aarch64-opc.c (aarch64_print_operand): Update case for
- AARCH64_OPND_BARRIER_PSB.
- * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
- (AARCH64_OPERANDS): Update inserter/extracter for
- AARCH64_OPND_BARRIER_PSB to use new dummy functions.
- * aarch64-asm-2.c: Regenerated.
- * aarch64-dis-2.c: Regenerated.
- * aarch64-opc-2.c: Regenerated.
-
-2020-04-20 Sudakshina Das <sudi.das@arm.com>
-
- * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
- (aarch64_feature_ras, RAS): Likewise.
- (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
- (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
- autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
- autiaz, autiasp, autibz, autibsp to be CORE_INSN.
- * aarch64-asm-2.c: Regenerated.
- * aarch64-dis-2.c: Regenerated.
- * aarch64-opc-2.c: Regenerated.
-
-2020-04-17 Fredrik Strupe <fredrik@strupe.net>
-
- * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
- (print_insn_neon): Support disassembly of conditional
- instructions.
-
-2020-02-16 David Faust <david.faust@oracle.com>
-
- * bpf-desc.c: Regenerate.
- * bpf-desc.h: Likewise.
- * bpf-opc.c: Regenerate.
- * bpf-opc.h: Likewise.
-
-2020-04-07 Lili Cui <lili.cui@intel.com>
-
- * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
- (prefix_table): New instructions (see prefixes above).
- (rm_table): Likewise
- * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
- CPU_ANY_TSXLDTRK_FLAGS.
- (cpu_flags): Add CpuTSXLDTRK.
- * i386-opc.h (enum): Add CpuTSXLDTRK.
- (i386_cpu_flags): Add cputsxldtrk.
- * i386-opc.tbl: Add XSUSPLDTRK insns.
- * i386-init.h: Regenerate.
- * i386-tbl.h: Likewise.
-
-2020-04-02 Lili Cui <lili.cui@intel.com>
-
- * i386-dis.c (prefix_table): New instructions serialize.
- * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
- CPU_ANY_SERIALIZE_FLAGS.
- (cpu_flags): Add CpuSERIALIZE.
- * i386-opc.h (enum): Add CpuSERIALIZE.
- (i386_cpu_flags): Add cpuserialize.
- * i386-opc.tbl: Add SERIALIZE insns.
- * i386-init.h: Regenerate.
- * i386-tbl.h: Likewise.
-
-2020-03-26 Alan Modra <amodra@gmail.com>
-
- * disassemble.h (opcodes_assert): Declare.
- (OPCODES_ASSERT): Define.
- * disassemble.c: Don't include assert.h. Include opintl.h.
- (opcodes_assert): New function.
- * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
- (bfd_h8_disassemble): Reduce size of data array. Correctly
- calculate maxlen. Omit insn decoding when insn length exceeds
- maxlen. Exit from nibble loop when looking for E, before
- accessing next data byte. Move processing of E outside loop.
- Replace tests of maxlen in loop with assertions.
-
-2020-03-26 Alan Modra <amodra@gmail.com>
-
- * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
-
-2020-03-25 Alan Modra <amodra@gmail.com>
-
- * z80-dis.c (suffix): Init mybuf.
-
-2020-03-22 Alan Modra <amodra@gmail.com>
-
- * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
- successflly read from section.
-
-2020-03-22 Alan Modra <amodra@gmail.com>
-
- * arc-dis.c (find_format): Use ISO C string concatenation rather
- than line continuation within a string. Don't access needs_limm
- before testing opcode != NULL.
-
-2020-03-22 Alan Modra <amodra@gmail.com>
-
- * ns32k-dis.c (print_insn_arg): Update comment.
- (print_insn_ns32k): Reduce size of index_offset array, and
- initialize, passing -1 to print_insn_arg for args that are not
- an index. Don't exit arg loop early. Abort on bad arg number.
-
-2020-03-22 Alan Modra <amodra@gmail.com>
-
- * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
- * s12z-opc.c: Formatting.
- (operands_f): Return an int.
- (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
- (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
- (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
- (exg_sex_discrim): Likewise.
- (create_immediate_operand, create_bitfield_operand),
- (create_register_operand_with_size, create_register_all_operand),
- (create_register_all16_operand, create_simple_memory_operand),
- (create_memory_operand, create_memory_auto_operand): Don't
- segfault on malloc failure.
- (z_ext24_decode): Return an int status, negative on fail, zero
- on success.
- (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
- (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
- (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
- (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
- (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
- (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
- (loop_primitive_decode, shift_decode, psh_pul_decode),
- (bit_field_decode): Similarly.
- (z_decode_signed_value, decode_signed_value): Similarly. Add arg
- to return value, update callers.
- (x_opr_decode_with_size): Check all reads, returning NULL on fail.
- Don't segfault on NULL operand.
- (decode_operation): Return OP_INVALID on first fail.
- (decode_s12z): Check all reads, returning -1 on fail.
-
-2020-03-20 Alan Modra <amodra@gmail.com>
-
- * metag-dis.c (print_insn_metag): Don't ignore status from
- read_memory_func.
-
-2020-03-20 Alan Modra <amodra@gmail.com>
-
- * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
- Initialize parts of buffer not written when handling a possible
- 2-byte insn at end of section. Don't attempt decoding of such
- an insn by the 4-byte machinery.
-
-2020-03-20 Alan Modra <amodra@gmail.com>
-
- * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
- partially filled buffer. Prevent lookup of 4-byte insns when
- only VLE 2-byte insns are possible due to section size. Print
- ".word" rather than ".long" for 2-byte leftovers.
-
-2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
-
- PR 25641
- * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
-
-2020-03-13 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (X86_64_0D): Rename to ...
- (X86_64_0E): ... this.
-
-2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
-
- * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
- * Makefile.in: Regenerated.
-
-2020-03-09 Jan Beulich <jbeulich@suse.com>
-
- * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
- 3-operand pseudos.
- * i386-tbl.h: Re-generate.
-
-2020-03-09 Jan Beulich <jbeulich@suse.com>
-
- * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
- vprot*, vpsha*, and vpshl*.
- * i386-tbl.h: Re-generate.
-
-2020-03-09 Jan Beulich <jbeulich@suse.com>
-
- * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
- vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
- * i386-tbl.h: Re-generate.
-
-2020-03-09 Jan Beulich <jbeulich@suse.com>
-
- * i386-gen.c (set_bitfield): Ignore zero-length field names.
- * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
- cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
- * i386-tbl.h: Re-generate.
-
-2020-03-09 Jan Beulich <jbeulich@suse.com>
-
- * i386-gen.c (struct template_arg, struct template_instance,
- struct template_param, struct template, templates,
- parse_template, expand_templates): New.
- (process_i386_opcodes): Various local variables moved to
- expand_templates. Call parse_template and expand_templates.
- * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
- * i386-tbl.h: Re-generate.
-
-2020-03-06 Jan Beulich <jbeulich@suse.com>
-
- * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
- vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
- register and memory source templates. Replace VexW= by VexW*
- where applicable.
- * i386-tbl.h: Re-generate.
-
-2020-03-06 Jan Beulich <jbeulich@suse.com>
-
- * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
- VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
- * i386-tbl.h: Re-generate.
-
-2020-03-06 Jan Beulich <jbeulich@suse.com>
-
- * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
- * i386-tbl.h: Re-generate.
-
-2020-03-06 Jan Beulich <jbeulich@suse.com>
-
- * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
- (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
- pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
- VexW0 on SSE2AVX variants.
- (vmovq): Drop NoRex64 from XMM/XMM variants.
- (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
- vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
- applicable use VexW0.
- * i386-tbl.h: Re-generate.
-
-2020-03-06 Jan Beulich <jbeulich@suse.com>
-
- * i386-gen.c (opcode_modifiers): Remove Rex64 field.
- * i386-opc.h (Rex64): Delete.
- (struct i386_opcode_modifier): Remove rex64 field.
- * i386-opc.tbl (crc32): Drop Rex64.
- Replace Rex64 with Size64 everywhere else.
- * i386-tbl.h: Re-generate.
-
-2020-03-06 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (OP_E_memory): Exclude recording of used address
- prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
- addressed memory operands for MPX insns.
-
-2020-03-06 Jan Beulich <jbeulich@suse.com>
-
- * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
- invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
- adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
- (ptwrite): Split into non-64-bit and 64-bit forms.
- * i386-tbl.h: Re-generate.
-
-2020-03-06 Jan Beulich <jbeulich@suse.com>
-
- * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
- template.
- * i386-tbl.h: Re-generate.
-
-2020-03-04 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
- (prefix_table): Move vmmcall here. Add vmgexit.
- (rm_table): Replace vmmcall entry by prefix_table[] escape.
- * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
- (cpu_flags): Add CpuSEV_ES entry.
- * i386-opc.h (CpuSEV_ES): New.
- (union i386_cpu_flags): Add cpusev_es field.
- * i386-opc.tbl (vmgexit): New.
- * i386-init.h, i386-tbl.h: Re-generate.
-
-2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
- with MnemonicSize.
- * i386-opc.h (IGNORESIZE): New.
- (DEFAULTSIZE): Likewise.
- (IgnoreSize): Removed.
- (DefaultSize): Likewise.
- (MnemonicSize): New.
- (i386_opcode_modifier): Replace ignoresize/defaultsize with
- mnemonicsize.
- * i386-opc.tbl (IgnoreSize): New.
- (DefaultSize): Likewise.
- * i386-tbl.h: Regenerated.
-
-2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
-
- PR 25627
- * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
- instructions.
-
-2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
-
- PR gas/25622
- * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
- vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
- * i386-tbl.h: Regenerated.
-
-2020-02-26 Alan Modra <amodra@gmail.com>
-
- * aarch64-asm.c: Indent labels correctly.
- * aarch64-dis.c: Likewise.
- * aarch64-gen.c: Likewise.
- * aarch64-opc.c: Likewise.
- * alpha-dis.c: Likewise.
- * i386-dis.c: Likewise.
- * nds32-asm.c: Likewise.
- * nfp-dis.c: Likewise.
- * visium-dis.c: Likewise.
-
-2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
-
- * arc-regs.h (int_vector_base): Make it available for all ARC
- CPUs.
-
-2020-02-20 Nelson Chu <nelson.chu@sifive.com>
-
- * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
- changed.
-
-2020-02-19 Nelson Chu <nelson.chu@sifive.com>
-
- * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
- c.mv/c.li if rs1 is zero.
-
-2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-gen.c (cpu_flag_init): Replace CpuABM with
- CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
- CPU_POPCNT_FLAGS.
- (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
- * i386-opc.h (CpuABM): Removed.
- (CpuPOPCNT): New.
- (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
- * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
- popcnt. Remove CpuABM from lzcnt.
- * i386-init.h: Regenerated.
- * i386-tbl.h: Likewise.
-
-2020-02-17 Jan Beulich <jbeulich@suse.com>
-
- * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
- Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
- VexW1 instead of open-coding them.
- * i386-tbl.h: Re-generate.
-
-2020-02-17 Jan Beulich <jbeulich@suse.com>
-
- * i386-opc.tbl (AddrPrefixOpReg): Define.
- (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
- umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
- templates. Drop NoRex64.
- * i386-tbl.h: Re-generate.
-
-2020-02-17 Jan Beulich <jbeulich@suse.com>
-
- PR gas/6518
- * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
- vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
- into Intel syntax instance (with Unpsecified) and AT&T one
- (without).
- (vcvtneps2bf16): Likewise, along with folding the two so far
- separate ones.
- * i386-tbl.h: Re-generate.
-
-2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
- CPU_ANY_SSE4A_FLAGS.
-
-2020-02-17 Alan Modra <amodra@gmail.com>
-
- * i386-gen.c (cpu_flag_init): Correct last change.
-
-2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
- CPU_ANY_SSE4_FLAGS.
-
-2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-opc.tbl (movsx): Remove Intel syntax comments.
- (movzx): Likewise.
-
-2020-02-14 Jan Beulich <jbeulich@suse.com>
-
- PR gas/25438
- * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
- destination for Cpu64-only variant.
- (movzx): Fold patterns.
- * i386-tbl.h: Re-generate.
-
-2020-02-13 Jan Beulich <jbeulich@suse.com>
-
- * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
- CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
- CPU_ANY_SSE4_FLAGS entry.
- * i386-init.h: Re-generate.
-
-2020-02-12 Jan Beulich <jbeulich@suse.com>
-
- * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
- with Unspecified, making the present one AT&T syntax only.
- * i386-tbl.h: Re-generate.
-
-2020-02-12 Jan Beulich <jbeulich@suse.com>
-
- * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
- * i386-tbl.h: Re-generate.
-
-2020-02-12 Jan Beulich <jbeulich@suse.com>
-
- PR gas/24546
- * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
- * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
- Amd64 and Intel64 templates.
- (call, jmp): Likewise for far indirect variants. Dro
- Unspecified.
- * i386-tbl.h: Re-generate.
-
-2020-02-11 Jan Beulich <jbeulich@suse.com>
-
- * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
- * i386-opc.h (ShortForm): Delete.
- (struct i386_opcode_modifier): Remove shortform field.
- * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
- fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
- fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
- ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
- Drop ShortForm.
- * i386-tbl.h: Re-generate.
-
-2020-02-11 Jan Beulich <jbeulich@suse.com>
-
- * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
- fucompi): Drop ShortForm from operand-less templates.
- * i386-tbl.h: Re-generate.
-
-2020-02-11 Alan Modra <amodra@gmail.com>
-
- * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
- * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
- * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
- * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
- * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
-
-2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
-
- * arm-dis.c (print_insn_cde): Define 'V' parse character.
- (cde_opcodes): Add VCX* instructions.
-
-2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
- Matthew Malcomson <matthew.malcomson@arm.com>
-
- * arm-dis.c (struct cdeopcode32): New.
- (CDE_OPCODE): New macro.
- (cde_opcodes): New disassembly table.
- (regnames): New option to table.
- (cde_coprocs): New global variable.
- (print_insn_cde): New
- (print_insn_thumb32): Use print_insn_cde.
- (parse_arm_disassembler_options): Parse coprocN args.
-
-2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
-
- PR gas/25516
- * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
- with ISA64.
- * i386-opc.h (AMD64): Removed.
- (Intel64): Likewose.
- (AMD64): New.
- (INTEL64): Likewise.
- (INTEL64ONLY): Likewise.
- (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
- * i386-opc.tbl (Amd64): New.
- (Intel64): Likewise.
- (Intel64Only): Likewise.
- Replace AMD64 with Amd64. Update sysenter/sysenter with
- Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
- * i386-tbl.h: Regenerated.
-
-2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
-
- PR 25469
- * z80-dis.c: Add support for GBZ80 opcodes.
-
-2020-02-04 Alan Modra <amodra@gmail.com>
-
- * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
-
-2020-02-03 Alan Modra <amodra@gmail.com>
-
- * m32c-ibld.c: Regenerate.
-
-2020-02-01 Alan Modra <amodra@gmail.com>
-
- * frv-ibld.c: Regenerate.
-
-2020-01-31 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
- (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
- (OP_E_memory): Replace xmm_mdq_mode case label by
- vex_scalar_w_dq_mode one.
- * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
-
-2020-01-31 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
- (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
- vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
- (intel_operand_size): Drop vex_w_dq_mode case label.
-
-2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
- Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
-
-2020-01-30 Alan Modra <amodra@gmail.com>
-
- * m32c-ibld.c: Regenerate.
-
-2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- * bpf-opc.c: Regenerate.
-
-2020-01-30 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
- (dis386): Use them to replace C2/C3 table entries.
- (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
- * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
- ones. Use Size64 instead of DefaultSize on Intel64 ones.
- * i386-tbl.h: Re-generate.
-
-2020-01-30 Jan Beulich <jbeulich@suse.com>
-
- * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
- forms.
- (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
- DefaultSize.
- * i386-tbl.h: Re-generate.
-
-2020-01-30 Alan Modra <amodra@gmail.com>
-
- * tic4x-dis.c (tic4x_dp): Make unsigned.
-
-2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
- Jan Beulich <jbeulich@suse.com>
-
- PR binutils/25445
- * i386-dis.c (MOVSXD_Fixup): New function.
- (movsxd_mode): New enum.
- (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
- (intel_operand_size): Handle movsxd_mode.
- (OP_E_register): Likewise.
- (OP_G): Likewise.
- * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
- register on movsxd. Add movsxd with 16-bit destination register
- for AMD64 and Intel64 ISAs.
- * i386-tbl.h: Regenerated.
-
-2020-01-27 Tamar Christina <tamar.christina@arm.com>
-
- PR 25403
- * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
- * aarch64-asm-2.c: Regenerate
- * aarch64-dis-2.c: Likewise.
- * aarch64-opc-2.c: Likewise.
-
-2020-01-21 Jan Beulich <jbeulich@suse.com>
-
- * i386-opc.tbl (sysret): Drop DefaultSize.
- * i386-tbl.h: Re-generate.
-
-2020-01-21 Jan Beulich <jbeulich@suse.com>
-
- * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
- Dword.
- (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
- * i386-tbl.h: Re-generate.
-
-2020-01-20 Nick Clifton <nickc@redhat.com>
-
- * po/de.po: Updated German translation.
- * po/pt_BR.po: Updated Brazilian Portuguese translation.
- * po/uk.po: Updated Ukranian translation.
-
-2020-01-20 Alan Modra <amodra@gmail.com>
-
- * hppa-dis.c (fput_const): Remove useless cast.
-
-2020-01-20 Alan Modra <amodra@gmail.com>
-
- * arm-dis.c (print_insn_arm): Wrap 'T' value.
-
-2020-01-18 Nick Clifton <nickc@redhat.com>
-
- * configure: Regenerate.
- * po/opcodes.pot: Regenerate.
-
-2020-01-18 Nick Clifton <nickc@redhat.com>
-
- Binutils 2.34 branch created.
-
-2020-01-17 Christian Biesinger <cbiesinger@google.com>
-
- * opintl.h: Fix spelling error (seperate).
-
-2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-opc.tbl: Add {vex} pseudo prefix.
- * i386-tbl.h: Regenerated.
-
-2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
-
- PR 25376
- * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
- (neon_opcodes): Likewise.
- (select_arm_features): Make sure we enable MVE bits when selecting
- armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
- any architecture.
-
-2020-01-16 Jan Beulich <jbeulich@suse.com>
-
- * i386-opc.tbl: Drop stale comment from XOP section.
-
-2020-01-16 Jan Beulich <jbeulich@suse.com>
-
- * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
- (extractps): Add VexWIG to SSE2AVX forms.
- * i386-tbl.h: Re-generate.
-
-2020-01-16 Jan Beulich <jbeulich@suse.com>
-
- * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
- Size64 from and use VexW1 on SSE2AVX forms.
- (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
- VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
- * i386-tbl.h: Re-generate.
-
-2020-01-15 Alan Modra <amodra@gmail.com>
-
- * tic4x-dis.c (tic4x_version): Make unsigned long.
- (optab, optab_special, registernames): New file scope vars.
- (tic4x_print_register): Set up registernames rather than
- malloc'd registertable.
- (tic4x_disassemble): Delete optable and optable_special. Use
- optab and optab_special instead. Throw away old optab,
- optab_special and registernames when info->mach changes.
-
-2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
-
- PR 25377
- * z80-dis.c (suffix): Use .db instruction to generate double
- prefix.
-
-2020-01-14 Alan Modra <amodra@gmail.com>
-
- * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
- values to unsigned before shifting.
-
-2020-01-13 Thomas Troeger <tstroege@gmx.de>
-
- * arm-dis.c (print_insn_arm): Fill in insn info fields for control
- flow instructions.
- (print_insn_thumb16, print_insn_thumb32): Likewise.
- (print_insn): Initialize the insn info.
- * i386-dis.c (print_insn): Initialize the insn info fields, and
- detect jumps.
-
-2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
-
- * arc-opc.c (C_NE): Make it required.
-
-2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
-
- * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
- reserved register name.
-
-2020-01-13 Alan Modra <amodra@gmail.com>
-
- * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
- (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
-
-2020-01-13 Alan Modra <amodra@gmail.com>
-
- * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
- result of wasm_read_leb128 in a uint64_t and check that bits
- are not lost when copying to other locals. Use uint32_t for
- most locals. Use PRId64 when printing int64_t.
-
-2020-01-13 Alan Modra <amodra@gmail.com>
-
- * score-dis.c: Formatting.
- * score7-dis.c: Formatting.
-
-2020-01-13 Alan Modra <amodra@gmail.com>
-
- * score-dis.c (print_insn_score48): Use unsigned variables for
- unsigned values. Don't left shift negative values.
- (print_insn_score32): Likewise.
- * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
-
-2020-01-13 Alan Modra <amodra@gmail.com>
-
- * tic4x-dis.c (tic4x_print_register): Remove dead code.
-
-2020-01-13 Alan Modra <amodra@gmail.com>
-
- * fr30-ibld.c: Regenerate.
-
-2020-01-13 Alan Modra <amodra@gmail.com>
-
- * xgate-dis.c (print_insn): Don't left shift signed value.
- (ripBits): Formatting, use 1u.
-
-2020-01-10 Alan Modra <amodra@gmail.com>
-
- * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
- * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
-
-2020-01-10 Alan Modra <amodra@gmail.com>
-
- * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
- and XRREG value earlier to avoid a shift with negative exponent.
- * m10200-dis.c (disassemble): Similarly.
-
-2020-01-09 Nick Clifton <nickc@redhat.com>
-
- PR 25224
- * z80-dis.c (ld_ii_ii): Use correct cast.
-
-2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
-
- PR 25224
- * z80-dis.c (ld_ii_ii): Use character constant when checking
- opcode byte value.
-
-2020-01-09 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (SEP_Fixup): New.
- (SEP): Define.
- (dis386_twobyte): Use it for sysenter/sysexit.
- (enum x86_64_isa): Change amd64 enumerator to value 1.
- (OP_J): Compare isa64 against intel64 instead of amd64.
- * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
- forms.
- * i386-tbl.h: Re-generate.
-
-2020-01-08 Alan Modra <amodra@gmail.com>
-
- * z8k-dis.c: Include libiberty.h
- (instr_data_s): Make max_fetched unsigned.
- (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
- Don't exceed byte_info bounds.
- (output_instr): Make num_bytes unsigned.
- (unpack_instr): Likewise for nibl_count and loop.
- * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
- idx unsigned.
- * z8k-opc.h: Regenerate.
-
-2020-01-07 Shahab Vahedi <shahab@synopsys.com>
-
- * arc-tbl.h (llock): Use 'LLOCK' as class.
- (llockd): Likewise.
- (scond): Use 'SCOND' as class.
- (scondd): Likewise.
- (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
- (scondd): Likewise.
-
-2020-01-06 Alan Modra <amodra@gmail.com>
-
- * m32c-ibld.c: Regenerate.
-
-2020-01-06 Alan Modra <amodra@gmail.com>
-
- PR 25344
- * z80-dis.c (suffix): Don't use a local struct buffer copy.
- Peek at next byte to prevent recursion on repeated prefix bytes.
- Ensure uninitialised "mybuf" is not accessed.
- (print_insn_z80): Don't zero n_fetch and n_used here,..
- (print_insn_z80_buf): ..do it here instead.
-
-2020-01-04 Alan Modra <amodra@gmail.com>
-
- * m32r-ibld.c: Regenerate.
-
-2020-01-04 Alan Modra <amodra@gmail.com>
-
- * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
-
-2020-01-04 Alan Modra <amodra@gmail.com>
-
- * crx-dis.c (match_opcode): Avoid shift left of signed value.
-
-2020-01-04 Alan Modra <amodra@gmail.com>
-
- * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
-
-2020-01-03 Jan Beulich <jbeulich@suse.com>
-
- * aarch64-tbl.h (aarch64_opcode_table): Use
- SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
-
-2020-01-03 Jan Beulich <jbeulich@suse.com>
-
- * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
- forms of SUDOT and USDOT.
-
-2020-01-03 Jan Beulich <jbeulich@suse.com>
-
- * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
- uzip{1,2}.
- * opcodes/aarch64-dis-2.c: Re-generate.
-
-2020-01-03 Jan Beulich <jbeulich@suse.com>
-
- * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
- FMMLA encoding.
- * opcodes/aarch64-dis-2.c: Re-generate.
-
-2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
-
- * z80-dis.c: Add support for eZ80 and Z80 instructions.
-
-2020-01-01 Alan Modra <amodra@gmail.com>
+2021-01-01 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
-For older changes see ChangeLog-2019
+For older changes see ChangeLog-2020
\f
-Copyright (C) 2020 Free Software Foundation, Inc.
+Copyright (C) 2021 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
projects / thirdparty / binutils-gdb.git / blobdiff