MIPS: Add CRC ASE support

[thirdparty/binutils-gdb.git] / opcodes / ChangeLog

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+2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
+           Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
+
+       * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
+       * mips-opc.c (CRC, CRC64): New macros.
+       (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
+       crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
+       crc32cd for CRC64.
+
+2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
+
+       PR 20319
+       * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
+       (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
+
+2018-06-06  Alan Modra  <amodra@gmail.com>
+
+       * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
+       setjmp.  Move init for some other vars later too.
+
+2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
+
+       * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
+       (dis_private): Add new fields for property section tracking.
+       (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
+       (xtensa_instruction_fits): New functions.
+       (fetch_data): Bump minimal fetch size to 4.
+       (print_insn_xtensa): Make struct dis_private static.
+       Load and prepare property table on section change.
+       Don't disassemble literals. Don't disassemble instructions that
+       cross property table boundaries.
+
+2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * configure: Regenerated.
+
+2018-06-01  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
+       * i386-tbl.h: Re-generate.
+
+2018-06-01  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-opc.tbl (sldt, str): Add NoRex64.
+       * i386-tbl.h: Re-generate.
+
+2018-06-01  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-opc.tbl (invpcid): Add Oword.
+       * i386-tbl.h: Re-generate.
+
+2018-06-01  Alan Modra  <amodra@gmail.com>
+
+       * sysdep.h (_bfd_error_handler): Don't declare.
+       * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
+       * rl78-decode.opc: Likewise.
+       * msp430-decode.c: Regenerate.
+       * rl78-decode.c: Regenerate.
+
 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 
        * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.