[include/opcode]

[thirdparty/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 50489cd28a49ce4bf2df50dfc7f02887c3a039fb..7abd573ce5d92b7d7dff0db6faaa6235f8ba5853 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,97 @@
+2010-07-29  DJ Delorie  <dj@redhat.com>
+
+       * rx-decode.opc (SRR): New.
+       (rx_decode_opcode): Use it for movbi and movbir.  Decode NOP2 (mov
+       r0,r0) and NOP3 (max r0,r0) special cases.
+       * rx-decode.c: Regenerate.
+       
+2010-07-28  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * i386-dis.c: Add 0F to VEX opcode enums.
+
+2010-07-27  DJ Delorie  <dj@redhat.com>
+
+       * rx-decode.opc (store_flags): Remove, replace with F_* macros.
+       (rx_decode_opcode): Likewise.
+       * rx-decode.c: Regenerate.
+
+2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
+           Ina Pandit  <ina.pandit@kpitcummins.com>
+
+       * v850-dis.c (v850_sreg_names): Updated structure for system
+       registers.
+       (float_cc_names): new structure for condition codes.
+       (print_value): Update the function that prints value.
+       (get_operand_value): New function to get the operand value.
+       (disassemble): Updated to handle the disassembly of instructions.
+       (print_insn_v850): Updated function to print instruction for different
+       families.
+       * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
+       extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
+       extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
+       insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
+       extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
+       extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
+       extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
+       insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
+       (insert_d8_7, insert_d5_4, insert_i5div): Remove.
+       (v850_operands): Update with the relocation name. Also update
+       the instructions with specific set of processors.
+
+2010-07-08 Tejas Belagod <tejas.belagod@arm.com>
+
+       * arm-dis.c (print_insn_arm): Add cases for printing more
+       symbolic operands.
+       (print_insn_thumb32): Likewise.
+
+2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
+
+       * mips-dis.c (print_insn_mips): Correct branch instruction type
+       determination.
+
+2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
+
+       * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
+       type and delay slot determination.
+       (print_insn_mips16): Extend branch instruction type and delay
+       slot determination to cover all instructions.
+       * mips16-opc.c (BR): Remove macro.
+       (UBR, CBR): New macros.
+       (mips16_opcodes): Update branch annotation for "b", "beqz",
+       "bnez", "bteqz" and "btnez".  Add branch annotation for "jalrc"
+       and "jrc".
+
+2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
+
+       AVX Programming Reference (June, 2010)
+       * i386-dis.c (mod_table): Replace rdrnd with rdrand.
+       * i386-opc.tbl: Likewise.
+       * i386-tbl.h: Regenerated.
+
+2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
+
+2010-07-03  Andreas Schwab  <schwab@linux-m68k.org>
+
+       * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
+       ppc_cpu_t before inverting.
+       (ppc_parse_cpu): Likewise.
+       (print_insn_powerpc): Likewise.
+
+2010-07-03  Alan Modra  <amodra@gmail.com>
+
+       * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
+       * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
+       (PPC64, MFDEC2): Update.
+       (NON32, NO371): Define.
+       (powerpc_opcode): Update to not use old opcode flags, and avoid
+       -m601 duplicates.
+
+2010-07-03  DJ Delorie  <dj@delorie.com>
+
+       * m32c-ibld.c: Regenerate.
+
 2010-07-03  Alan Modra  <amodra@gmail.com>
 
        * ppc-opc.c (PWR2COM): Define.
@@ -27,7 +121,7 @@
        (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
 
        * i386-opc.h (CpuXsaveopt): New.
-       (CpuFSGSBase):Likewise.
+       (CpuFSGSBase): Likewise.
        (CpuRdRnd): Likewise.
        (CpuF16C): Likewise.
        (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and