PowerPC: Add new xxmr and xxlnot extended mnemonics

[thirdparty/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 7a380dc0087eb11e086f2fb0334fe571a50c34d2..7ba0c02579dbaf196a4f93f5114491468c2c21a3 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,132 @@
+2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
+
+       * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
+
+2021-05-25  Alan Modra  <amodra@gmail.com>
+
+       * cris-desc.c: Regenerate.
+       * cris-desc.h: Regenerate.
+       * cris-opc.h: Regenerate.
+       * po/POTFILES.in: Regenerate.
+
+2021-05-24  Mike Frysinger  <vapier@gentoo.org>
+
+       * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
+       (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
+       (CGEN_CPUS): Add cris.
+       (CRIS_DEPS): Define.
+       (stamp-cris): New rule.
+       * cgen.sh: Handle desc action.
+       * configure.ac (bfd_cris_arch): Add cris-desc.lo.
+       * Makefile.in, configure: Regenerate.
+
+2021-05-18  Job Noorman  <mtvec@pm.me>
+
+       PR 27814
+       * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
+       the elf objects.
+
+2021-05-17  Alex Coplan  <alex.coplan@arm.com>
+
+       * arm-dis.c (mve_opcodes): Fix disassembly of
+       MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
+       (is_mve_encoding_conflict): MVE vector loads should not match
+       when P = W = 0.
+       (is_mve_unpredictable): It's not unpredictable to use the same
+       source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
+
+2021-05-11  Nick Clifton  <nickc@redhat.com>
+
+       PR 27840
+       * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
+       the end of the code buffer.
+
+2021-05-06  Stafford Horne  <shorne@gmail.com>
+
+       PR 21464
+       * or1k-asm.c: Regenerate.
+
+2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
+
+       * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
+       info->insn_info_valid.
+
+2021-04-26  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-opc.tbl (lea): Add Optimize.
+       * opcodes/i386-tbl.h: Re-generate.
+
+2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
+
+       * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
+       of l32r fetch and display referenced literal value.
+
+2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
+
+       * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
+       to 4 for literal disassembly.
+
+2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
+       for TLBI instruction.
+
+2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
+       DC instruction.
+
+2021-04-19  Jan Beulich  <jbeulich@suse.com>
+
+       * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
+       "qualifier".
+       (convert_mov_to_movewide): Add initializer for "value".
+
+2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * aarch64-opc.c: Add RME system registers.
+
+2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
+
+       * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
+       "addi d,CV,z" to "c.mv d,CV".
+
+2021-04-12  Alan Modra  <amodra@gmail.com>
+
+       * configure.ac (--enable-checking): Add support.
+       * config.in: Regenerate.
+       * configure: Regenerate.
+
+2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
+
+       * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
+       LD64/ST64 instructions to lse_atomic instead of ldstexcl.
+
+2021-04-09  Alan Modra  <amodra@gmail.com>
+
+       * ppc-dis.c (struct dis_private): Add "special".
+       (POWERPC_DIALECT): Delete.  Replace uses with..
+       (private_data): ..this.  New inline function.
+       (disassemble_init_powerpc): Init "special" names.
+       (skip_optional_operands): Add is_pcrel arg, set when detecting R
+       field of prefix instructions.
+       (bsearch_reloc, print_got_plt): New functions.
+       (print_insn_powerpc): For pcrel instructions, print target address
+       and symbol if known, and decode plt and got loads too.
+
+2021-04-08  Alan Modra  <amodra@gmail.com>
+
+       PR 27684
+       * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
+
+2021-04-08  Alan Modra  <amodra@gmail.com>
+
+       PR 27676
+       * ppc-opc.c (DCBT_EO): Move earlier.
+       (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
+       (powerpc_operands): Add THCT and THDS entries.
+       (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
+
 2021-04-06  Alan Modra  <amodra@gmail.com>
 
        * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.