[MIPS] Add Loongson 3A1000 proccessor support.

[thirdparty/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 1c9c1a11b578c6bb6aa21c4a20d207431888c2ec..a2c4b294ab8e416071cc3228aa5512f9ae961f53 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,141 @@
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
+       * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
+       loongson3a as an alias of gs464 for compatibility.
+       * mips-opc.c (mips_opcodes): Change Comments.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
+       * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
+       option.
+       (print_mips_disassembler_options): Document -M loongson-ext.
+       * mips-opc.c (LEXT2): New macro.
+       (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
+        * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
+        descriptors.
+        (parse_mips_ase_option): Handle -M loongson-ext option.
+        (print_mips_disassembler_options): Document -M loongson-ext.
+        * mips-opc.c (IL3A): Delete.
+        * mips-opc.c (LEXT): New macro.
+        (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
+        instructions.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
+       * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
+       descriptors.
+       (parse_mips_ase_option): Handle -M loongson-cam option.
+       (print_mips_disassembler_options): Document -M loongson-cam.
+       * mips-opc.c (LCAM): New macro.
+       (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
+       instructions.
+
+2018-08-21  Alan Modra  <amodra@gmail.com>
+
+       * ppc-dis.c (operand_value_powerpc): Init "invalid".
+       (skip_optional_operands): Count optional operands, and update
+       ppc_optional_operand_value call.
+       * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
+       (extract_vlensi): Likewise.
+       (extract_fxm): Return default value for missing optional operand.
+       (extract_ls, extract_raq, extract_tbr): Likewise.
+       (insert_sxl, extract_sxl): New functions.
+       (insert_esync, extract_esync): Remove Power9 handling and simplify.
+       (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
+       flag and extra entry.
+       (powerpc_operands <SXL>): Likewise, and use insert_sxl and
+       extract_sxl.
+
+2018-08-20  Alan Modra  <amodra@gmail.com>
+
+       * sh-opc.h (MASK): Simplify.
+
+2018-08-18  John Darrington  <john@darrington.wattle.id.au>
+
+       * s12z-dis.c (bm_decode): Deal with cases where the mode is
+       BM_RESERVED0 or BM_RESERVED1
+       (bm_rel_decode, bm_n_bytes): Ditto.
+
+2018-08-18  John Darrington  <john@darrington.wattle.id.au>
+
+       * s12z.h: Delete.
+
+2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
+       address with the addr32 prefix and without base nor index
+       registers.
+
+2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
+       CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
+       CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
+       (cpu_flags): Add CpuCMOV and CpuFXSR.
+       * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
+       fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
+       * i386-init.h: Regenerated.
+       * i386-tbl.h: Likewise.
+
+2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
+
+       * arc-regs.h: Update auxiliary registers.
+
+2018-08-06  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
+       (RegIP, RegIZ): Define.
+       * i386-reg.tbl: Adjust comments.
+       (rip): Use Qword instead of BaseIndex. Use RegIP.
+       (eip): Use Dword instead of BaseIndex. Use RegIP.
+       (riz): Add Qword. Use RegIZ.
+       (eiz): Add Dword. Use RegIZ.
+       * i386-tbl.h: Re-generate.
+
+2018-08-03  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
+       pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
+       vpmovzxdq, vpmovzxwd): Remove NoRex64.
+       * i386-tbl.h: Re-generate.
+
+2018-08-03  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-gen.c (operand_types): Remove Mem field.
+       * i386-opc.h (union i386_operand_type): Remove mem field.
+       * i386-init.h, i386-tbl.h: Re-generate.
+
+2018-08-01  Alan Modra  <amodra@gmail.com>
+
+       * po/POTFILES.in: Regenerate.
+
+2018-07-31  Nick Clifton  <nickc@redhat.com>
+
+       * po/sv.po: Updated Swedish translation.
+
+2018-07-31  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
+       * i386-init.h, i386-tbl.h: Re-generate.
+
+2018-07-31  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-opc.h (ZEROING_MASKING) Rename to ...
+       (DYNAMIC_MASKING): ... this. Adjust comment.
+       * i386-opc.tbl (MaskingMorZ): Define.
+       (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
+       vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
+       vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
+       vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
+       vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
+       vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
+       vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
+       vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
+       vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
+
 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 
        * i386-opc.tbl: Use element rather than vector size for AVX512*