+2020-07-04 Nick Clifton <nickc@redhat.com>
+
+ Binutils 2.35 branch created.
+
+2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (opcode_modifiers): Add VexSwapSources.
+ * i386-opc.h (VexSwapSources): New.
+ (i386_opcode_modifier): Add vexswapsources.
+ * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
+ with two source operands swapped.
+ * i386-tbl.h: Regenerated.
+
+2020-06-30 Nelson Chu <nelson.chu@sifive.com>
+
+ * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
+ unprivileged CSR can also be initialized.
+
+2020-06-29 Alan Modra <amodra@gmail.com>
+
+ * arm-dis.c: Use C style comments.
+ * cr16-opc.c: Likewise.
+ * ft32-dis.c: Likewise.
+ * moxie-opc.c: Likewise.
+ * tic54x-dis.c: Likewise.
+ * s12z-opc.c: Remove useless comment.
+ * xgate-dis.c: Likewise.
+
+2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl: Add a blank line.
+
+2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
+ (VecSIB128): Renamed to ...
+ (VECSIB128): This.
+ (VecSIB256): Renamed to ...
+ (VECSIB256): This.
+ (VecSIB512): Renamed to ...
+ (VECSIB512): This.
+ (VecSIB): Renamed to ...
+ (SIB): This.
+ (i386_opcode_modifier): Replace vecsib with sib.
+ * i386-opc.tbl (VecSIB128): New.
+ (VecSIB256): Likewise.
+ (VecSIB512): Likewise.
+ Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
+ and VecSIB512, respectively.
+
+2020-06-26 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c: Adjust description of I macro.
+ (x86_64_table): Drop use of I.
+ (float_mem): Replace use of I.
+ (putop): Remove handling of I. Adjust setting/clearing of "alt".
+
+2020-06-26 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c: (print_insn): Avoid straight assignment to
+ priv.orig_sizeflag when processing -M sub-options.
+
+2020-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c: Adjust description of J macro.
+ (dis386, x86_64_table, mod_table): Replace J.
+ (putop): Remove handling of J.
+
+2020-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
+
+2020-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c: Adjust description of "LQ" macro.
+ (dis386_twobyte): Use LQ for sysret.
+ (putop): Adjust handling of LQ.
+
+2020-06-22 Nelson Chu <nelson.chu@sifive.com>
+
+ * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
+ * riscv-dis.c: Include elfxx-riscv.h.
+
+2020-06-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (prefix_table): Revert the last vmgexit change.
+
+2020-06-17 Lili Cui <lili.cui@intel.com>
+
+ * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
+
+2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/26115
+ * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
+ * i386-opc.tbl: Likewise.
+ * i386-tbl.h: Regenerated.
+
+2020-06-12 Nelson Chu <nelson.chu@sifive.com>
+
+ * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
+
+2020-06-11 Alex Coplan <alex.coplan@arm.com>
+
+ * aarch64-opc.c (SYSREG): New macro for describing system registers.
+ (SR_CORE): Likewise.
+ (SR_FEAT): Likewise.
+ (SR_RNG): Likewise.
+ (SR_V8_1): Likewise.
+ (SR_V8_2): Likewise.
+ (SR_V8_3): Likewise.
+ (SR_V8_4): Likewise.
+ (SR_PAN): Likewise.
+ (SR_RAS): Likewise.
+ (SR_SSBS): Likewise.
+ (SR_SVE): Likewise.
+ (SR_ID_PFR2): Likewise.
+ (SR_PROFILE): Likewise.
+ (SR_MEMTAG): Likewise.
+ (SR_SCXTNUM): Likewise.
+ (aarch64_sys_regs): Refactor to store feature information in the table.
+ (aarch64_sys_reg_supported_p): Collapse logic for system registers
+ that now describe their own features.
+ (aarch64_pstatefield_supported_p): Likewise.
+
+2020-06-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (prefix_table): Fix a typo in comments.
+
+2020-06-09 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (rex_ignored): Delete.
+ (ckprefix): Drop rex_ignored initialization.
+ (get_valid_dis386): Drop setting of rex_ignored.
+ (print_insn): Drop checking of rex_ignored. Don't record data
+ size prefix as used with VEX-and-alike encodings.
+
+2020-06-09 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
+ MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
+ (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
+ (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
+ (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
+ VEX_0F12, and VEX_0F16.
+ (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
+ VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
+ (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
+ from movlps and movhlps. New MOD_0F12_PREFIX_2,
+ MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
+ MOD_VEX_0F16_PREFIX_2 entries.
+
+2020-06-09 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
+ MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
+ (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
+ PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
+ PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
+ PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
+ EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
+ EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
+ EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
+ EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
+ EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
+ EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
+ EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
+ EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
+ EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
+ EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
+ EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
+ EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
+ EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
+ EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
+ EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
+ EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
+ EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
+ EVEX_W_0FC6_P_2): Delete.
+ (print_insn): Add EVEX.W vs embedded prefix consistency check
+ to prefix validation.
+ * i386-dis-evex.h (evex_table): Don't further descend for
+ vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
+ and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
+ and 0F2B.
+ * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
+ * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
+ vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
+ vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
+ 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
+ Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
+ PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
+ PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
+ PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
+ * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
+ EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
+ EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
+ EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
+ EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
+ EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
+ EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
+ EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
+ EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
+ EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
+ EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
+ EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
+ EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
+ EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
+ EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
+ EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
+ EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
+ EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
+
+2020-06-09 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
+ vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
+ (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
+ vmovmskpX.
+ (print_insn): Drop pointless check against bad_opcode. Split
+ prefix validation into legacy and VEX-and-alike parts.
+ (putop): Re-work 'X' macro handling.
+
+2020-06-09 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (MOD_0F51): Rename to ...
+ (MOD_0F50): ... this.
+
+2020-06-08 Alex Coplan <alex.coplan@arm.com>
+
+ * arm-dis.c (arm_opcodes): Add dfb.
+ (thumb32_opcodes): Add dfb.
+
+2020-06-08 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.h (reg_entry): Const-qualify reg_name field.
+
+2020-06-06 Alan Modra <amodra@gmail.com>
+
+ * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
+
+2020-06-05 Alan Modra <amodra@gmail.com>
+
+ * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
+ size is large enough.
+
+2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * disassemble.c (disassemble_init_for_target): Set endian_code for
+ bpf targets.
+ * bpf-desc.c: Regenerate.
+ * bpf-opc.c: Likewise.
+ * bpf-dis.c: Likewise.
+
+2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
+ (cgen_put_insn_value): Likewise.
+ (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
+ * cgen-dis.in (print_insn): Likewise.
+ * cgen-ibld.in (insert_1): Likewise.
+ (insert_1): Likewise.
+ (insert_insn_normal): Likewise.
+ (extract_1): Likewise.
+ * bpf-dis.c: Regenerate.
+ * bpf-ibld.c: Likewise.
+ * bpf-ibld.c: Likewise.
+ * cgen-dis.in: Likewise.
+ * cgen-ibld.in: Likewise.
+ * cgen-opc.c: Likewise.
+ * epiphany-dis.c: Likewise.
+ * epiphany-ibld.c: Likewise.
+ * fr30-dis.c: Likewise.
+ * fr30-ibld.c: Likewise.
+ * frv-dis.c: Likewise.
+ * frv-ibld.c: Likewise.
+ * ip2k-dis.c: Likewise.
+ * ip2k-ibld.c: Likewise.
+ * iq2000-dis.c: Likewise.
+ * iq2000-ibld.c: Likewise.
+ * lm32-dis.c: Likewise.
+ * lm32-ibld.c: Likewise.
+ * m32c-dis.c: Likewise.
+ * m32c-ibld.c: Likewise.
+ * m32r-dis.c: Likewise.
+ * m32r-ibld.c: Likewise.
+ * mep-dis.c: Likewise.
+ * mep-ibld.c: Likewise.
+ * mt-dis.c: Likewise.
+ * mt-ibld.c: Likewise.
+ * or1k-dis.c: Likewise.
+ * or1k-ibld.c: Likewise.
+ * xc16x-dis.c: Likewise.
+ * xc16x-ibld.c: Likewise.
+ * xstormy16-dis.c: Likewise.
+ * xstormy16-ibld.c: Likewise.
+
+2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
+
+ * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
+ (print_insn_): Handle instruction endian.
+ * bpf-dis.c: Regenerate.
+ * bpf-desc.c: Regenerate.
+ * epiphany-dis.c: Likewise.
+ * epiphany-desc.c: Likewise.
+ * fr30-dis.c: Likewise.
+ * fr30-desc.c: Likewise.
+ * frv-dis.c: Likewise.
+ * frv-desc.c: Likewise.
+ * ip2k-dis.c: Likewise.
+ * ip2k-desc.c: Likewise.
+ * iq2000-dis.c: Likewise.
+ * iq2000-desc.c: Likewise.
+ * lm32-dis.c: Likewise.
+ * lm32-desc.c: Likewise.
+ * m32c-dis.c: Likewise.
+ * m32c-desc.c: Likewise.
+ * m32r-dis.c: Likewise.
+ * m32r-desc.c: Likewise.
+ * mep-dis.c: Likewise.
+ * mep-desc.c: Likewise.
+ * mt-dis.c: Likewise.
+ * mt-desc.c: Likewise.
+ * or1k-dis.c: Likewise.
+ * or1k-desc.c: Likewise.
+ * xc16x-dis.c: Likewise.
+ * xc16x-desc.c: Likewise.
+ * xstormy16-dis.c: Likewise.
+ * xstormy16-desc.c: Likewise.
+
+2020-06-03 Nick Clifton <nickc@redhat.com>
+
+ * po/sr.po: Updated Serbian translation.
+
+2020-06-03 Nelson Chu <nelson.chu@sifive.com>
+
+ * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
+ (riscv_get_priv_spec_class): Likewise.
+
+2020-06-01 Alan Modra <amodra@gmail.com>
+
+ * bpf-desc.c: Regenerate.
+
+2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
+ David Faust <david.faust@oracle.com>
+
+ * bpf-desc.c: Regenerate.
+ * bpf-opc.h: Likewise.
+ * bpf-opc.c: Likewise.
+ * bpf-dis.c: Likewise.
+
+2020-05-28 Alan Modra <amodra@gmail.com>
+
+ * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
+ values.
+
+2020-05-28 Alan Modra <amodra@gmail.com>
+
+ * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
+ immediates.
+ (print_insn_ns32k): Revert last change.
+
+2020-05-28 Nick Clifton <nickc@redhat.com>
+
+ * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
+ static.
+
+2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
+
+ Fix extraction of signed constants in nios2 disassembler (again).
+
+ * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
+ extractions of signed fields.
+
+2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
+
+ * s390-opc.txt: Relocate vector load/store instructions with
+ additional alignment parameter and change architecture level
+ constraint from z14 to z13.
+
+2020-05-21 Alan Modra <amodra@gmail.com>
+
+ * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
+ * sparc-dis.c: Likewise.
+ * tic4x-dis.c: Likewise.
+ * xtensa-dis.c: Likewise.
+ * bpf-desc.c: Regenerate.
+ * epiphany-desc.c: Regenerate.
+ * fr30-desc.c: Regenerate.
+ * frv-desc.c: Regenerate.
+ * ip2k-desc.c: Regenerate.
+ * iq2000-desc.c: Regenerate.
+ * lm32-desc.c: Regenerate.
+ * m32c-desc.c: Regenerate.
+ * m32r-desc.c: Regenerate.
+ * mep-asm.c: Regenerate.
+ * mep-desc.c: Regenerate.
+ * mt-desc.c: Regenerate.
+ * or1k-desc.c: Regenerate.
+ * xc16x-desc.c: Regenerate.
+ * xstormy16-desc.c: Regenerate.
+
+2020-05-20 Nelson Chu <nelson.chu@sifive.com>
+
+ * riscv-opc.c (riscv_ext_version_table): The table used to store
+ all information about the supported spec and the corresponding ISA
+ versions. Currently, only Zicsr is supported to verify the
+ correctness of Z sub extension settings. Others will be supported
+ in the future patches.
+ (struct isa_spec_t, isa_specs): List for all supported ISA spec
+ classes and the corresponding strings.
+ (riscv_get_isa_spec_class): New function. Get the corresponding ISA
+ spec class by giving a ISA spec string.
+ * riscv-opc.c (struct priv_spec_t): New structure.
+ (struct priv_spec_t priv_specs): List for all supported privilege spec
+ classes and the corresponding strings.
+ (riscv_get_priv_spec_class): New function. Get the corresponding
+ privilege spec class by giving a spec string.
+ (riscv_get_priv_spec_name): New function. Get the corresponding
+ privilege spec string by giving a CSR version class.
+ * riscv-dis.c: Updated since DECLARE_CSR is changed.
+ * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
+ according to the chosen version. Build a hash table riscv_csr_hash to
+ store the valid CSR for the chosen pirv verison. Dump the direct
+ CSR address rather than it's name if it is invalid.
+ (parse_riscv_dis_option_without_args): New function. Parse the options
+ without arguments.
+ (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
+ parse the options without arguments first, and then handle the options
+ with arguments. Add the new option -Mpriv-spec, which has argument.
+ * riscv-dis.c (print_riscv_disassembler_options): Add description
+ about the new OBJDUMP option.
+
+2020-05-19 Peter Bergner <bergner@linux.ibm.com>
+
+ * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
+ WC values on POWER10 sync, dcbf and wait instructions.
+ (insert_pl, extract_pl): New functions.
+ (L2OPT, LS, WC): Use insert_ls and extract_ls.
+ (LS3): New , 3-bit L for sync.
+ (LS3, L3OPT): New, 3-bit L for sync and dcbf.
+ (SC2, PL): New, 2-bit SC and PL for sync and wait.
+ (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
+ (XOPL3, XWCPL, XSYNCLS): New opcode macros.
+ (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
+ plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
+ <wait>: Enable PL operand on POWER10.
+ <dcbf>: Enable L3OPT operand on POWER10.
+ <sync>: Enable SC2 operand on POWER10.
+
+2020-05-19 Stafford Horne <shorne@gmail.com>
+
+ PR 25184
+ * or1k-asm.c: Regenerate.
+ * or1k-desc.c: Regenerate.
+ * or1k-desc.h: Regenerate.
+ * or1k-dis.c: Regenerate.
+ * or1k-ibld.c: Regenerate.
+ * or1k-opc.c: Regenerate.
+ * or1k-opc.h: Regenerate.
+ * or1k-opinst.c: Regenerate.
+
+2020-05-11 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
+ xsmaxcqp, xsmincqp.
+
+2020-05-11 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
+ stxvrbx, stxvrhx, stxvrwx, stxvrdx.
+
+2020-05-11 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
+
+2020-05-11 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
+ vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
+
+2020-05-11 Peter Bergner <bergner@linux.ibm.com>
+
+ * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
+ mnemonics.
+
+2020-05-11 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
+ (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
+ vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
+ (prefix_opcodes): Add xxeval.
+
+2020-05-11 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
+ xxgenpcvwm, xxgenpcvdm.
+
+2020-05-11 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c (MP, VXVAM_MASK): Define.
+ (VXVAPS_MASK): Use VXVA_MASK.
+ (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
+ vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
+ vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
+ vcntmbb, vcntmbh, vcntmbw, vcntmbd.
+
+2020-05-11 Alan Modra <amodra@gmail.com>
+ Peter Bergner <bergner@linux.ibm.com>
+
+ * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
+ New functions.
+ (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
+ YMSK2, XA6a, XA6ap, XB6a entries.
+ (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
+ (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
+ (PPCVSX4): Define.
+ (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
+ xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
+ xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
+ xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
+ xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
+ xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
+ xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
+ (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
+ pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
+ pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
+ pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
+ pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
+ pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
+ pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
+
+2020-05-11 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c (insert_imm32, extract_imm32): New functions.
+ (insert_xts, extract_xts): New functions.
+ (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
+ (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
+ (VXRC_MASK, VXSH_MASK): Define.
+ (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
+ vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
+ vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
+ vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
+ vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
+ (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
+ xxblendvh, xxblendvw, xxblendvd, xxpermx.
+
+2020-05-11 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
+ vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
+ vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
+ vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
+ xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
+
+2020-05-11 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c (insert_xtp, extract_xtp): New functions.
+ (XTP, DQXP, DQXP_MASK): Define.
+ (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
+ (prefix_opcodes): Add plxvp and pstxvp.
+
+2020-05-11 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
+ vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
+ vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
+
+2020-05-11 Peter Bergner <bergner@linux.ibm.com>
+
+ * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
+
+2020-05-11 Peter Bergner <bergner@linux.ibm.com>
+
+ * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
+ (L1OPT): Define.
+ (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
+
+2020-05-11 Peter Bergner <bergner@linux.ibm.com>
+
+ * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
+
+2020-05-11 Alan Modra <amodra@gmail.com>
+
+ * ppc-dis.c (powerpc_init_dialect): Default to "power10".
+
+2020-05-11 Alan Modra <amodra@gmail.com>
+
+ * ppc-dis.c (ppc_opts): Add "power10" entry.
+ (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
+ * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
+
+2020-05-11 Nick Clifton <nickc@redhat.com>
+
+ * po/fr.po: Updated French translation.
+
+2020-04-30 Alex Coplan <alex.coplan@arm.com>
+
+ * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
+ * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
+ (operand_general_constraint_met_p): validate
+ AARCH64_OPND_UNDEFINED.
+ * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
+ for FLD_imm16_2.
+ * aarch64-asm-2.c: Regenerated.
+ * aarch64-dis-2.c: Regenerated.
+ * aarch64-opc-2.c: Regenerated.
+
+2020-04-29 Nick Clifton <nickc@redhat.com>
+
+ PR 22699
+ * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
+ and SETRC insns.
+
+2020-04-29 Nick Clifton <nickc@redhat.com>
+
+ * po/sv.po: Updated Swedish translation.
+
+2020-04-29 Nick Clifton <nickc@redhat.com>
+
+ PR 22699
+ * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
+ IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
+ * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
+ IMM0_8U case.
+
+2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
+
+ PR 25848
+ * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
+ cmpi only on m68020up and cpu32.
+
+2020-04-20 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-asm.c (aarch64_ins_none): New.
+ * aarch64-asm.h (ins_none): New declaration.
+ * aarch64-dis.c (aarch64_ext_none): New.
+ * aarch64-dis.h (ext_none): New declaration.
+ * aarch64-opc.c (aarch64_print_operand): Update case for
+ AARCH64_OPND_BARRIER_PSB.
+ * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
+ (AARCH64_OPERANDS): Update inserter/extracter for
+ AARCH64_OPND_BARRIER_PSB to use new dummy functions.
+ * aarch64-asm-2.c: Regenerated.
+ * aarch64-dis-2.c: Regenerated.
+ * aarch64-opc-2.c: Regenerated.
+
+2020-04-20 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
+ (aarch64_feature_ras, RAS): Likewise.
+ (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
+ (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
+ autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
+ autiaz, autiasp, autibz, autibsp to be CORE_INSN.
+ * aarch64-asm-2.c: Regenerated.
+ * aarch64-dis-2.c: Regenerated.
+ * aarch64-opc-2.c: Regenerated.
+
+2020-04-17 Fredrik Strupe <fredrik@strupe.net>
+
+ * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
+ (print_insn_neon): Support disassembly of conditional
+ instructions.
+
+2020-02-16 David Faust <david.faust@oracle.com>
+
+ * bpf-desc.c: Regenerate.
+ * bpf-desc.h: Likewise.
+ * bpf-opc.c: Regenerate.
+ * bpf-opc.h: Likewise.
+
2020-04-07 Lili Cui <lili.cui@intel.com>
* i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
projects / thirdparty / binutils-gdb.git / blobdiff