+2021-03-31 Alan Modra <amodra@gmail.com>
+
+ * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
+ * aarch64-dis.h: Likewise.
+ * aarch64-opc.c: Likewise.
+ * avr-dis.c: Likewise.
+ * csky-dis.c: Likewise.
+ * nds32-asm.c: Likewise.
+ * nds32-dis.c: Likewise.
+ * nfp-dis.c: Likewise.
+ * riscv-dis.c: Likewise.
+ * s12z-dis.c: Likewise.
+ * wasm32-dis.c: Likewise.
+
+2021-03-30 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
+ (i386_seg_prefixes): New.
+ * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
+ (i386_seg_prefixes): Declare.
+
+2021-03-30 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
+
+2021-03-30 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
+ * i386-reg.tbl (st): Move down.
+ (st(0)): Delete. Extend comment.
+ * i386-tbl.h: Re-generate.
+
+2021-03-29 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
+ (cmpsd): Move next to cmps.
+ (movsd): Move next to movs.
+ (cmpxchg16b): Move to separate section.
+ (fisttp, fisttpll): Likewise.
+ (monitor, mwait): Likewise.
+ * i386-tbl.h: Re-generate.
+
+2021-03-29 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (psadbw): Add <sse2:comm>.
+ (vpsadbw): Add C.
+ * i386-tbl.h: Re-generate.
+
+2021-03-29 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
+ pclmul, gfni): New templates. Use them wherever possible. Move
+ SSE4.1 pextrw into respective section.
+ * i386-tbl.h: Re-generate.
+
+2021-03-29 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
+ strtoull(). Bump upper loop bound. Widen masks. Sanity check
+ "length".
+ * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
+ Convert all of their uses to representation in opcode.
+
+2021-03-29 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.h (struct insn_template): Shrink base_opcode to 16
+ bits. Shrink extension_opcode to 9 bits. Make it signed. Change
+ value of None. Shrink operands to 3 bits.
+
+2021-03-29 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (process_i386_opcode_modifier): New parameter
+ "space".
+ (output_i386_opcode): New local variable "space". Adjust
+ process_i386_opcode_modifier() invocation.
+ (process_i386_opcodes): Adjust process_i386_opcode_modifier()
+ invocation.
+ * i386-tbl.h: Re-generate.
+
+2021-03-29 Alan Modra <amodra@gmail.com>
+
+ * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
+ (fp_qualifier_p, get_data_pattern): Likewise.
+ (aarch64_get_operand_modifier_from_value): Likewise.
+ (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
+ (operand_variant_qualifier_p): Likewise.
+ (qualifier_value_in_range_constraint_p): Likewise.
+ (aarch64_get_qualifier_esize): Likewise.
+ (aarch64_get_qualifier_nelem): Likewise.
+ (aarch64_get_qualifier_standard_value): Likewise.
+ (get_lower_bound, get_upper_bound): Likewise.
+ (aarch64_find_best_match, match_operands_qualifier): Likewise.
+ (aarch64_print_operand): Likewise.
+ * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
+ (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
+ (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
+ * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
+ * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
+ (print_insn_tic6x): Likewise.
+
+2021-03-29 Alan Modra <amodra@gmail.com>
+
+ * arc-dis.c (extract_operand_value): Correct NULL cast.
+ * frv-opc.h: Regenerate.
+
+2021-03-26 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
+ MMX form.
+ * i386-tbl.h: Re-generate.
+
+2021-03-25 Abid Qadeer <abidh@codesourcery.com>
+
+ * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
+ immediate in br.n instruction.
+
+2021-03-25 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (XMGatherD, VexGatherD): New.
+ (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
+ (print_insn): Check masking for S/G insns.
+ (OP_E_memory): New local variable check_gather. Extend mandatory
+ SIB check. Check register conflicts for (EVEX-encoded) gathers.
+ Extend check for disallowed 16-bit addressing.
+ (OP_VEX): New local variables modrm_reg and sib_index. Convert
+ if()s to switch(). Check register conflicts for (VEX-encoded)
+ gathers. Drop no longer reachable cases.
+ * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
+ vgatherdp*.
+
+2021-03-25 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
+ zeroing-masking without masking.
+
+2021-03-25 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (invlpgb): Fix multi-operand form.
+ (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
+ single-operand forms as deprecated.
+ * i386-tbl.h: Re-generate.
+
+2021-03-25 Alan Modra <amodra@gmail.com>
+
+ PR 27647
+ * ppc-opc.c (XLOCB_MASK): Delete.
+ (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
+ XLBH_MASK.
+ (powerpc_opcodes): Accept a BH field on all extended forms of
+ bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
+
+2021-03-24 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (output_i386_opcode): Drop processing of
+ opcode_length. Calculate length from base_opcode. Adjust prefix
+ encoding determination.
+ (process_i386_opcodes): Drop output of fake opcode_length.
+ * i386-opc.h (struct insn_template): Drop opcode_length field.
+ * i386-opc.tbl: Drop opcode length field from all templates.
+ * i386-tbl.h: Re-generate.
+
+2021-03-24 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (process_i386_opcode_modifier): Return void. New
+ parameter "prefix". Drop local variable "regular_encoding".
+ Record prefix setting / check for consistency.
+ (output_i386_opcode): Parse opcode_length and base_opcode
+ earlier. Derive prefix encoding. Drop no longer applicable
+ consistency checking. Adjust process_i386_opcode_modifier()
+ invocation.
+ (process_i386_opcodes): Adjust process_i386_opcode_modifier()
+ invocation.
+ * i386-tbl.h: Re-generate.
+
+2021-03-24 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
+ check.
+ * i386-opc.h (Prefix_*): Move #define-s.
+ * i386-opc.tbl: Move pseudo prefix enumerator values to
+ extension opcode field. Introduce pseudopfx template.
+ * i386-tbl.h: Re-generate.
+
+2021-03-23 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
+ comment.
+ * i386-tbl.h: Re-generate.
+
+2021-03-23 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.h (struct insn_template): Move cpu_flags field past
+ opcode_modifier one.
+ * i386-tbl.h: Re-generate.
+
+2021-03-23 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
+ * i386-opc.h (OpcodeSpace): New enumerator.
+ (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
+ (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
+ SPACE_XOP09, SPACE_XOP0A): ... respectively.
+ (struct i386_opcode_modifier): New field opcodespace. Shrink
+ opcodeprefix field.
+ i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
+ SpaceXOP09, SpaceXOP0A): Define. Use them to replace
+ OpcodePrefix uses.
+ * i386-tbl.h: Re-generate.
+
+2021-03-22 Martin Liska <mliska@suse.cz>
+
+ * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
+ * arc-dis.c (parse_option): Likewise.
+ * arm-dis.c (parse_arm_disassembler_options): Likewise.
+ * cris-dis.c (print_with_operands): Likewise.
+ * h8300-dis.c (bfd_h8_disassemble): Likewise.
+ * i386-dis.c (print_insn): Likewise.
+ * ia64-gen.c (fetch_insn_class): Likewise.
+ (parse_resource_users): Likewise.
+ (in_iclass): Likewise.
+ (lookup_specifier): Likewise.
+ (insert_opcode_dependencies): Likewise.
+ * mips-dis.c (parse_mips_ase_option): Likewise.
+ (parse_mips_dis_option): Likewise.
+ * s390-dis.c (disassemble_init_s390): Likewise.
+ * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
+
+2021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
+
+ * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
+
+2021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
+ icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
+
+2021-03-12 Alan Modra <amodra@gmail.com>
+
+ * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
+
+2021-03-11 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (OP_XMM): Re-order checks.
+
+2021-03-11 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (putop): Drop need_vex check when also checking
+ vex.evex.
+ (intel_operand_size, OP_E_memory): Drop vex.evex check when also
+ checking vex.b.
+
+2021-03-11 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
+ checks. Move case label past broadcast check.
+
+2021-03-10 Jan Beulich <jbeulich@suse.com>
+
+ * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
+ vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
+ REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
+ EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
+ EVEX_W_0F38C7_M_0_L_2): Delete.
+ (REG_EVEX_0F38C7_M_0_L_2): New.
+ (intel_operand_size): Handle VEX and EVEX the same for
+ vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
+ vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
+ (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
+ vex_vsib_q_w_d_mode uses.
+ * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
+ 0F38A1, and 0F38A3 entries.
+ * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
+ entry.
+ * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
+ * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
+ 0F38A3 entries.
+
+2021-03-10 Jan Beulich <jbeulich@suse.com>
+
+ * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
+ REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
+ MOD_VEX_0FXOP_09_12): Rename to ...
+ (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
+ REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
+ (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
+ RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
+ X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
+ X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
+ (reg_table): Adjust comments.
+ (x86_64_table): Move X86_64_0F24, X86_64_0F26,
+ X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
+ X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
+ (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
+ (vex_len_table): Adjust opcode 0A_12 entry.
+ (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
+ MOD_C5_32BIT, and MOD_XOP_09_12 entries.
+ (rm_table): Move hreset entry.
+
+2021-03-10 Jan Beulich <jbeulich@suse.com>
+
+ * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
+ EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
+ EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
+ EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
+ EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
+ (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
+ (get_valid_dis386): Also handle 512-bit vector length when
+ vectoring into vex_len_table[].
+ * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
+ 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
+ entries.
+ * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
+ 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
+ * i386-dis-evex-prefix.h: Adjust 0F7E entry.
+ * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
+ entries.
+
+2021-03-10 Jan Beulich <jbeulich@suse.com>
+
+ * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
+ Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
+ EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
+ * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
+ entries.
+ * i386-dis-evex-len.h (evex_len_table): Likewise.
+ * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
+
2021-03-10 Jan Beulich <jbeulich@suse.com>
* opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
projects / thirdparty / binutils-gdb.git / blobdiff