/* aarch64-asm.c -- AArch64 assembler support.
- Copyright (C) 2012-2019 Free Software Foundation, Inc.
+ Copyright (C) 2012-2021 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of the GNU opcodes library.
/* Operand inserters. */
+/* Insert nothing. */
+bfd_boolean
+aarch64_ins_none (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ const aarch64_opnd_info *info ATTRIBUTE_UNUSED,
+ aarch64_insn *code ATTRIBUTE_UNUSED,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+ return TRUE;
+}
+
/* Insert register number. */
bfd_boolean
aarch64_ins_regno (const aarch64_operand *self, const aarch64_opnd_info *info,
switch (info->qualifier)
{
case AARCH64_OPND_QLF_S_4B:
+ case AARCH64_OPND_QLF_S_2H:
/* L:H */
assert (reglane_index < 4);
insert_fields (code, reglane_index, 0, 2, FLD_L, FLD_H);
return TRUE;
}
+/* Encode the memory barrier option operand for DSB <option>nXS|#<imm>. */
+
+bfd_boolean
+aarch64_ins_barrier_dsb_nxs (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ const aarch64_opnd_info *info, aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+ /* For the DSB nXS barrier variant: is a 5-bit unsigned immediate,
+ encoded in CRm<3:2>. */
+ aarch64_insn value = (info->barrier->value >> 2) - 4;
+ insert_field (FLD_CRm_dsb_nxs, code, value, 0);
+ return TRUE;
+}
+
/* Encode the prefetch operation option operand for e.g.
PRFM <prfop>, [<Xn|SP>{, #<pimm>}]. */
0, 2, FLD_SVE_tszl_19, FLD_SVE_sz);
break;
- case sve_size_013:
- variant = aarch64_get_variant (inst);
+ case sve_size_13:
+ variant = aarch64_get_variant (inst) + 1;
if (variant == 2)
variant = 3;
insert_field (FLD_size, &inst->value, variant, 0);
break;
}
-convert_to_real_return:
+ convert_to_real_return:
aarch64_replace_opcode (inst, real);
}
}
-encoding_exit:
+ encoding_exit:
DEBUG_TRACE ("exit with %s", opcode->name);
*code = inst->value;