/* aarch64-opc.c -- AArch64 opcode support.
- Copyright (C) 2009-2020 Free Software Foundation, Inc.
+ Copyright (C) 2009-2021 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of the GNU opcodes library.
case AARCH64_OPND_Rt2:
case AARCH64_OPND_Rs:
case AARCH64_OPND_Ra:
+ case AARCH64_OPND_Rt_LS64:
case AARCH64_OPND_Rt_SYS:
case AARCH64_OPND_PAIRREG:
case AARCH64_OPND_SVE_Rm:
SR_RAS ("erxaddr_el1", CPENC (3,0,C5,C4,3), 0),
SR_RAS ("erxmisc0_el1", CPENC (3,0,C5,C5,0), 0),
SR_RAS ("erxmisc1_el1", CPENC (3,0,C5,C5,1), 0),
+ SR_RAS ("erxmisc2_el1", CPENC (3,0,C5,C5,2), 0),
+ SR_RAS ("erxmisc3_el1", CPENC (3,0,C5,C5,3), 0),
+ SR_RAS ("erxpfgcdn_el1", CPENC (3,0,C5,C4,6), 0),
+ SR_RAS ("erxpfgctl_el1", CPENC (3,0,C5,C4,5), 0),
+ SR_RAS ("erxpfgf_el1", CPENC (3,0,C5,C4,4), F_REG_READ),
SR_CORE ("far_el1", CPENC (3,0,C6,C0,0), 0),
SR_CORE ("far_el2", CPENC (3,4,C6,C0,0), 0),
SR_CORE ("far_el3", CPENC (3,6,C6,C0,0), 0),
SR_CORE ("brbinf30_el1", CPENC (2,1,C8,C14,4), F_REG_READ),
SR_CORE ("brbinf31_el1", CPENC (2,1,C8,C15,4), F_REG_READ),
+ SR_CORE ("accdata_el1", CPENC (3,0,C13,C0,5), 0),
+
{ 0, CPENC (0,0,0,0,0), 0, 0 }
};